[MachineOperand][MIR] Add isRenamable to MachineOperand.

Summary:
Add isRenamable() predicate to MachineOperand.  This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand.  Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).

Reviewers: qcolombet, MatzeB, hfinkel

Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D39400

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320503 91177308-0d34-0410-b5e6-96231b3b80d8

11 files changed, 46 insertions, 30 deletions

diff --git a/test/CodeGen/AArch64/arm64-misched-multimmo.ll b/test/CodeGen/AArch64/arm64-misched-multimmo.ll
index bdd4f49d174..47f2ec790c7 100644
--- a/test/CodeGen/AArch64/arm64-misched-multimmo.ll
+++ b/test/CodeGen/AArch64/arm64-misched-multimmo.ll
@@ -8,11 +8,11 @@
 ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
 ;
 ; CHECK-LABEL: # Machine code for function foo:
-; CHECK: SU(2):   %w{{[0-9]+}}, %w{{[0-9]+}} = LDPWi
+; CHECK: SU(2):   renamable %w{{[0-9]+}}, renamable %w{{[0-9]+}} = LDPWi
 ; CHECK: Successors:
 ; CHECK-NOT: ch SU(4)
 ; CHECK: SU(3)
-; CHECK: SU(4):   STRWui %wzr, %x{{[0-9]+}}
+; CHECK: SU(4):   STRWui %wzr, renamable %x{{[0-9]+}}
 define i32 @foo() {
 entry:
   %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4
diff --git a/test/CodeGen/AMDGPU/shrink-carry.mir b/test/CodeGen/AMDGPU/shrink-carry.mir
index cf000ffa774..d499b2192e9 100644
--- a/test/CodeGen/AMDGPU/shrink-carry.mir
+++ b/test/CodeGen/AMDGPU/shrink-carry.mir
@@ -1,7 +1,7 @@
 # RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: subbrev{{$}}
-# GCN:       V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec
+# GCN:       V_SUBBREV_U32_e64 0, undef %vgpr0, killed renamable %vcc, implicit %exec
 
 ---
 name:            subbrev
@@ -25,7 +25,7 @@ body:             |
 ...
 
 # GCN-LABEL: name: subb{{$}}
-# GCN:       V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec
+# GCN:       V_SUBB_U32_e64 undef %vgpr0, 0, killed renamable %vcc, implicit %exec
 
 ---
 name:            subb
@@ -49,7 +49,7 @@ body:             |
 ...
 
 # GCN-LABEL: name: addc{{$}}
-# GCN:       V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
+# GCN:       V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
 
 ---
 name:            addc
@@ -73,7 +73,7 @@ body:             |
 ...
 
 # GCN-LABEL: name: addc2{{$}}
-# GCN:       V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
+# GCN:       V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
 
 ---
 name:            addc2
diff --git a/test/CodeGen/AMDGPU/splitkit.mir b/test/CodeGen/AMDGPU/splitkit.mir
index 41782af40e3..45a9c41c381 100644
--- a/test/CodeGen/AMDGPU/splitkit.mir
+++ b/test/CodeGen/AMDGPU/splitkit.mir
@@ -37,13 +37,13 @@ body: |
 # CHECK: [[REG0:%sgpr[0-9]+]] = COPY %sgpr0
 # CHECK: [[REG1:%sgpr[0-9]+]] = COPY %sgpr2
 # CHECK: S_NOP 0
-# CHECK: S_NOP 0, implicit [[REG0]]
-# CHECK: S_NOP 0, implicit [[REG1]]
-# CHECK: %sgpr0 = COPY [[REG0]]
-# CHECK: %sgpr2 = COPY [[REG1]]
+# CHECK: S_NOP 0, implicit renamable [[REG0]]
+# CHECK: S_NOP 0, implicit renamable [[REG1]]
+# CHECK: %sgpr0 = COPY renamable [[REG0]]
+# CHECK: %sgpr2 = COPY renamable [[REG1]]
 # CHECK: S_NOP
-# CHECK: S_NOP 0, implicit %sgpr0
-# CHECK: S_NOP 0, implicit %sgpr2
+# CHECK: S_NOP 0, implicit renamable %sgpr0
+# CHECK: S_NOP 0, implicit renamable %sgpr2
 name: func1
 tracksRegLiveness: true
 body: |
@@ -67,8 +67,8 @@ body: |
 # Check that copy hoisting out of loops works. This mainly should not crash the
 # compiler when it hoists a subreg copy sequence.
 # CHECK-LABEL: name: splitHoist
-# CHECK: S_NOP 0, implicit-def %sgpr0
-# CHECK: S_NOP 0, implicit-def %sgpr3
+# CHECK: S_NOP 0, implicit-def renamable %sgpr0
+# CHECK: S_NOP 0, implicit-def renamable %sgpr3
 # CHECK-NEXT: SI_SPILL_S128_SAVE
 name: splitHoist
 tracksRegLiveness: true
diff --git a/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir b/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
index b41e6ac6fd5..d5bf6a1eb8c 100644
--- a/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
+++ b/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
@@ -9,10 +9,10 @@
 # CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
 # CHECK-NEXT: stack-id: 1,
 
-# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)
+# CHECK: SI_SPILL_V32_SAVE killed renamable %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)
 # CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0)
 
-# CHECK: SI_SPILL_S32_SAVE killed %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)
+# CHECK: SI_SPILL_S32_SAVE killed renamable %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)
 # CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (load 4 from %stack.1)
 
 name: no_merge_sgpr_vgpr_spill_slot
diff --git a/test/CodeGen/AMDGPU/subreg_interference.mir b/test/CodeGen/AMDGPU/subreg_interference.mir
index 6fc22c8d189..3575e41c2b7 100644
--- a/test/CodeGen/AMDGPU/subreg_interference.mir
+++ b/test/CodeGen/AMDGPU/subreg_interference.mir
@@ -12,12 +12,12 @@
 # sgpr0-sgpr3.
 #
 # CHECK-LABEL: func0
-# CHECK: S_NOP 0, implicit-def %sgpr0
-# CHECK: S_NOP 0, implicit-def %sgpr3
-# CHECK: S_NOP 0, implicit-def %sgpr1
-# CHECK: S_NOP 0, implicit-def %sgpr2
-# CHECK: S_NOP 0, implicit %sgpr0, implicit %sgpr3
-# CHECK: S_NOP 0, implicit %sgpr1, implicit %sgpr2
+# CHECK: S_NOP 0, implicit-def renamable %sgpr0
+# CHECK: S_NOP 0, implicit-def renamable %sgpr3
+# CHECK: S_NOP 0, implicit-def renamable %sgpr1
+# CHECK: S_NOP 0, implicit-def renamable %sgpr2
+# CHECK: S_NOP 0, implicit renamable %sgpr0, implicit renamable %sgpr3
+# CHECK: S_NOP 0, implicit renamable %sgpr1, implicit renamable %sgpr2
 name: func0
 body: |
   bb.0:
diff --git a/test/CodeGen/AMDGPU/syncscopes.ll b/test/CodeGen/AMDGPU/syncscopes.ll
index 6e356f69e05..5cea1588d4b 100644
--- a/test/CodeGen/AMDGPU/syncscopes.ll
+++ b/test/CodeGen/AMDGPU/syncscopes.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s
 
 ; GCN-LABEL: name: syncscopes
-; GCN: FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
-; GCN: FLAT_STORE_DWORD killed %vgpr4_vgpr5, killed %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
-; GCN: FLAT_STORE_DWORD killed %vgpr7_vgpr8, killed %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr1_vgpr2, killed renamable %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr4_vgpr5, killed renamable %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
+; GCN: FLAT_STORE_DWORD killed renamable %vgpr7_vgpr8, killed renamable %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
 define void @syncscopes(
     i32 %agent,
     i32 addrspace(4)* %agent_out,
diff --git a/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/test/CodeGen/Hexagon/regalloc-bad-undef.mir
index 7e18011a523..720f504098d 100644
--- a/test/CodeGen/Hexagon/regalloc-bad-undef.mir
+++ b/test/CodeGen/Hexagon/regalloc-bad-undef.mir
@@ -153,7 +153,7 @@ body:             |
     %13 = S2_asl_r_p_acc %13, %47, %8.isub_lo
     %51 = A2_tfrpi 0
 
-    ; CHECK: %d2 = S2_extractup undef %d0, 6, 25
+    ; CHECK: %d2 = S2_extractup undef renamable %d0, 6, 25
     ; CHECK: %d0 = A2_tfrpi 2
     ; CHECK: %d13 = A2_tfrpi -1
     ; CHECK-NOT: undef %r4
diff --git a/test/CodeGen/MIR/X86/renamable-register-flag.mir b/test/CodeGen/MIR/X86/renamable-register-flag.mir
new file mode 100644
index 00000000000..3854a2877c0
--- /dev/null
+++ b/test/CodeGen/MIR/X86/renamable-register-flag.mir
@@ -0,0 +1,16 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses the 'renamable' register flags
+# correctly.
+
+--- |
+  define void @foo() { ret void }
+...
+---
+name:            foo
+body: |
+  ; CHECK: bb.0:
+  bb.0:
+    ; CHECK: renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    RETQ %eax
+...
diff --git a/test/CodeGen/PowerPC/byval-agg-info.ll b/test/CodeGen/PowerPC/byval-agg-info.ll
index 141edb57967..6e0b167757f 100644
--- a/test/CodeGen/PowerPC/byval-agg-info.ll
+++ b/test/CodeGen/PowerPC/byval-agg-info.ll
@@ -13,5 +13,5 @@ entry:
 
 ; Make sure that the MMO on the store has no offset from the byval
 ; variable itself (we used to have mem:ST8[%v+64]).
-; CHECK: STD killed %x5, 176, %x1; mem:ST8[%v](align=16)
+; CHECK: STD killed renamable %x5, 176, %x1; mem:ST8[%v](align=16)
 
diff --git a/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir b/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
index 8bf2b5575e8..29173d1274c 100644
--- a/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
+++ b/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
@@ -18,11 +18,11 @@ registers:
   - { id: 1, class: gr64bit }
   - { id: 2, class: addr64bit }
 # CHECK: %r0q = L128
-# CHECK-NEXT: %r0l = COPY %r1l
+# CHECK-NEXT: %r0l = COPY renamable %r1l
 # Although R0L partially redefines R0Q, it must not mark R0Q as kill
 # because R1D is still live through that instruction.
 # CHECK-NOT: implicit killed %r0q
-# CHECK-NEXT: %r2d = COPY %r1d
+# CHECK-NEXT: %r2d = COPY renamable %r1d
 # CHECK-NEXT: LARL
 body:             |
   bb.0:
diff --git a/test/CodeGen/X86/tail-merge-debugloc.ll b/test/CodeGen/X86/tail-merge-debugloc.ll
index 197b0b80325..85ba0ab6261 100644
--- a/test/CodeGen/X86/tail-merge-debugloc.ll
+++ b/test/CodeGen/X86/tail-merge-debugloc.ll
@@ -6,7 +6,7 @@
 ; location info.
 ; 
 ; CHECK:      [[DLOC:![0-9]+]] = !DILocation(line: 2, column: 2, scope: !{{[0-9]+}})
-; CHECK:      TEST64rr{{.*}}%rsi, %rsi, implicit-def %eflags
+; CHECK:      TEST64rr{{.*}}%rsi, renamable %rsi, implicit-def %eflags
 ; CHECK-NEXT: JNE_1{{.*}}, debug-location [[DLOC]]
 
 target triple = "x86_64-unknown-linux-gnu"