[mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support

Differential Revision: http://reviews.llvm.org/D18824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275050 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 164 insertions, 13 deletions

diff --git a/test/CodeGen/Mips/cconv/callee-saved-float.ll b/test/CodeGen/Mips/cconv/callee-saved-float.ll
index 9b503fc938e..30a5727f344 100644
--- a/test/CodeGen/Mips/cconv/callee-saved-float.ll
+++ b/test/CodeGen/Mips/cconv/callee-saved-float.ll
@@ -18,6 +18,8 @@
 ; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
 ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s
 
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-insn -arch mips -mcpu=mips32r6 -mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s
+
 ; Test the the callee-saved registers are callee-saved as specified by section
 ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
 
@@ -109,3 +111,6 @@ entry:
 ; N64-DAG:       ldc1 [[F30]], [[OFF30]]($sp)
 ; N64-DAG:       ldc1 [[F31]], [[OFF31]]($sp)
 ; N64:           addiu $sp, $sp, 64
+
+; Check the mapping between LDC164 and LDC1_64_MMR6.
+; MM32R6: ldc1
diff --git a/test/CodeGen/Mips/micromips-lwc1-swc1.ll b/test/CodeGen/Mips/micromips-lwc1-swc1.ll
new file mode 100644
index 00000000000..a1a10a5de25
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-lwc1-swc1.ll
@@ -0,0 +1,50 @@
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \
+; RUN:   -relocation-model=pic < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MM32
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MM32
+; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \
+; RUN:   -relocation-model=pic < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MM64
+
+@gf0 = external global float
+
+define float @test_lwc1() {
+entry:
+; CHECK-LABEL: test_lwc1
+; MM32:      lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM32:      addiu   $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM32:      addu    $[[R2:[0-9]+]], $[[R1]], $25
+; MM32:      lw      $[[R3:[0-9]+]], %got(gf0)($[[R2]])
+; MM32:      lwc1    $f0, 0($[[R3]])
+
+; MM64:      lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1)))
+; MM64:      daddu   $[[R1:[0-9]+]], $[[R0]], $25
+; MM64:      daddiu  $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1)))
+; MM64:      ld      $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
+; MM64:      lwc1    $f0, 0($[[R3]])
+
+  %0 = load float, float* @gf0, align 4
+  ret float %0
+}
+
+define void @test_swc1(float %a) {
+entry:
+; CHECK-LABEL: test_swc1
+; MM32:      lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM32:      addiu   $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM32:      addu    $[[R2:[0-9]+]], $[[R1]], $25
+; MM32:      lw      $[[R3:[0-9]+]], %got(gf0)($[[R2]])
+; MM32:      swc1    $f12, 0($[[R3]])
+
+; MM64:      lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1)))
+; MM64:      daddu   $[[R1:[0-9]+]], $[[R0]], $25
+; MM64:      daddiu  $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1)))
+; MM64:      ld      $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
+; MM64:      swc1    $f12, 0($[[R3]])
+
+  store float %a, float* @gf0, align 4
+  ret void
+}
+
diff --git a/test/CodeGen/Mips/mips64fpldst.ll b/test/CodeGen/Mips/mips64fpldst.ll
index baca9c84760..564ffdd2f69 100644
--- a/test/CodeGen/Mips/mips64fpldst.ll
+++ b/test/CodeGen/Mips/mips64fpldst.ll
@@ -2,6 +2,8 @@
 ; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc  < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc  < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
 
 @f0 = common global float 0.000000e+00, align 4
 @d0 = common global double 0.000000e+00, align 8
@@ -12,10 +14,10 @@ define float @funcfl1() nounwind readonly {
 entry:
 ; CHECK-N64: funcfl1
 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
-; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]]) 
+; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]])
 ; CHECK-N32: funcfl1
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
-; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]]) 
+; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
   %0 = load float, float* @f0, align 4
   ret float %0
 }
@@ -24,11 +26,11 @@ define double @funcfl2() nounwind readonly {
 entry:
 ; CHECK-N64: funcfl2
 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
-; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]]) 
+; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]])
 ; CHECK-N32: funcfl2
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
-; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]]) 
-  %0 = load double, double* @d0, align 8 
+; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]])
+  %0 = load double, double* @d0, align 8
   ret double %0
 }
 
@@ -36,12 +38,12 @@ define void @funcfs1() nounwind {
 entry:
 ; CHECK-N64: funcfs1
 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
-; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]]) 
+; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]])
 ; CHECK-N32: funcfs1
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
-; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]]) 
-  %0 = load float, float* @f1, align 4 
-  store float %0, float* @f0, align 4 
+; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
+  %0 = load float, float* @f1, align 4
+  store float %0, float* @f0, align 4
   ret void
 }
 
@@ -49,12 +51,12 @@ define void @funcfs2() nounwind {
 entry:
 ; CHECK-N64: funcfs2
 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
-; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]]) 
+; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]])
 ; CHECK-N32: funcfs2
 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
-; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]]) 
-  %0 = load double, double* @d1, align 8 
-  store double %0, double* @d0, align 8 
+; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]])
+  %0 = load double, double* @d1, align 8
+  store double %0, double* @d0, align 8
   ret void
 }
 
diff --git a/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/test/CodeGen/Mips/mno-ldc1-sdc1.ll
index 0bc8fb01eed..9663138d4c8 100644
--- a/test/CodeGen/Mips/mno-ldc1-sdc1.ll
+++ b/test/CodeGen/Mips/mno-ldc1-sdc1.ll
@@ -5,6 +5,10 @@
 ; RUN:   FileCheck %s -check-prefixes=ALL,32R2-LDXC1
 ; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,32R6-LDC1
+; RUN: llc -march=mipsel -mcpu=mips32r3 -mattr=+micromips \
+; RUN:   -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM
+; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM
 
 ; Check that -mno-ldc1-sdc1 disables [sl]dc1
 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
@@ -16,6 +20,12 @@
 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
 ; RUN:   -mcpu=mips32r6 < %s | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-PIC
+; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
+; RUN:   -mattr=+micromips < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC
+; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
+; RUN:   -mattr=+micromips < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC
 
 ; Check again for big-endian
 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
@@ -27,6 +37,12 @@
 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
 ; RUN:   -mcpu=mips32r6 < %s | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,32R6,32R6-BE,32R6-BE-PIC
+; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
+; RUN:   -mattr=+micromips < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC
+; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
+; RUN:   -mattr=+micromips < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC
 
 ; Check again for the static relocation model
 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
@@ -38,6 +54,10 @@
 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
 ; RUN:   -mcpu=mips32r6 < %s | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-STATIC
+; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r3 \
+; RUN:   -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC_PIC
+; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
+; RUN:   -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC-PIC
 
 @g0 = common global double 0.000000e+00, align 8
 
@@ -100,6 +120,26 @@
 
 ; 32R6-LDC1:          ldc1 $f0, 0(${{[0-9]+}})
 
+; MM:                 lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM:                 addiu   $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM:                 addu    $[[R2:[0-9]+]], $[[R1]], $25
+; MM:                 lw      $[[R3:[0-9]+]], %got(g0)($[[R2]])
+; MM:                 ldc1    $f0, 0($[[R3]])
+
+; MM-MNO-PIC:         lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM-MNO-PIC:         addiu   $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM-MNO-PIC:         addu    $[[R2:[0-9]+]], $[[R1]], $25
+; MM-MNO-PIC:         lw      $[[R3:[0-9]+]], %got(g0)($[[R2]])
+; MM-MNO-PIC:         lw16    $[[R4:[0-9]+]], 0($[[R3]])
+; MM-MNO-PIC:         lw16    $[[R5:[0-9]+]], 4($[[R3]])
+; MM-MNO-LE-PIC:      mtc1    $[[R4]], $f0
+; MM-MNO-LE-PIC:      mthc1   $[[R5]], $f0
+; MM-MNO-BE-PIC:      mtc1    $[[R5]], $f0
+; MM-MNO-BE-PIC:      mthc1   $[[R4]], $f0
+
+; MM-STATIC-PIC:      lui     $[[R0:[0-9]+]], %hi(g0)
+; MM-STATIC-PIC:      ldc1    $f0, %lo(g0)($[[R0]])
+
 define double @test_ldc1() {
 entry:
   %0 = load double, double* @g0, align 8
@@ -165,6 +205,26 @@ entry:
 
 ; 32R6-LDC1:          sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
 
+; MM:                 lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM:                 addiu   $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM:                 addu    $[[R2:[0-9]+]], $[[R1]], $25
+; MM:                 lw      $[[R3:[0-9]+]], %got(g0)($[[R2]])
+; MM:                 sdc1    $f12, 0($[[R3]])
+
+; MM-MNO-PIC:         lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; MM-MNO-PIC:         addiu   $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
+; MM-MNO-PIC:         addu    $[[R2:[0-9]+]], $[[R1]], $25
+; MM-MNO-LE-PIC:      mfc1    $[[R3:[0-9]+]], $f12
+; MM-MNO-BE-PIC:      mfhc1   $[[R3:[0-9]+]], $f12
+; MM-MNO-PIC:         lw      $[[R4:[0-9]+]], %got(g0)($[[R2]])
+; MM-MNO-PIC:         sw16    $[[R3]], 0($[[R4]])
+; MM-MNO-LE-PIC:      mfhc1   $[[R5:[0-9]+]], $f12
+; MM-MNO-BE-PIC:      mfc1    $[[R5:[0-9]+]], $f12
+; MM-MNO-PIC:         sw16    $[[R5]], 4($[[R4]])
+
+; MM-STATIC-PIC:      lui     $[[R0:[0-9]+]], %hi(g0)
+; MM-STATIC-PIC:      sdc1    $f12, %lo(g0)($[[R0]])
+
 define void @test_sdc1(double %a) {
 entry:
   store double %a, double* @g0, align 8
@@ -201,6 +261,23 @@ entry:
 
 ; 32R6-LDC1:     ldc1 $f0, 0(${{[0-9]+}})
 
+; MM:            sll16   $[[R0:[0-9]+]], $5, 3
+; MM:            addu16  $[[R1:[0-9]+]], $4, $[[R0]]
+; MM:            ldc1    $f0, 0($[[R1]])
+
+; MM-MNO-PIC:    sll16   $[[R0:[0-9]+]], $5, 3
+; MM-MNO-PIC:    addu16  $[[R1:[0-9]+]], $4, $[[R0]]
+; MM-MNO-PIC:    lw16    $[[R2:[0-9]+]], 0($[[R1]])
+; MM-MNO-PIC:    lw16    $[[R3:[0-9]+]], 4($[[R1]])
+; MM-MNO-LE-PIC: mtc1    $[[R2]], $f0
+; MM-MNO-LE-PIC: mthc1   $[[R3]], $f0
+; MM-MNO-BE-PIC: mtc1    $[[R3]], $f0
+; MM-MNO-BE-PIC: mthc1   $[[R2]], $f0
+
+; MM-STATIC-PIC: sll16   $[[R0:[0-9]+]], $5, 3
+; MM-STATIC-PIC: addu16  $[[R1:[0-9]+]], $4, $[[R0]]
+; MM-STATIC-PIC: ldc1    $f0, 0($[[R1]])
+
 define double @test_ldxc1(double* nocapture readonly %a, i32 %i) {
 entry:
   %arrayidx = getelementptr inbounds double, double* %a, i32 %i
@@ -232,6 +309,23 @@ entry:
 
 ; 32R6-LDC1:     sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
 
+; MM:            sll16   $[[R0:[0-9]+]], $7, 3
+; MM:            addu16  $[[R1:[0-9]+]], $6, $[[R0]]
+; MM:            sdc1    $f12, 0($[[R1]])
+
+; MM-MNO-PIC:    sll16   $[[R0:[0-9]+]], $7, 3
+; MM-MNO-PIC:    addu16  $[[R1:[0-9]+]], $6, $[[R0]]
+; MM-MNO-LE-PIC: mfc1    $[[R2:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfhc1   $[[R2:[0-9]+]], $f12
+; MM-MNO-PIC:    sw16    $[[R2]], 0($[[R1]])
+; MM-MNO-LE-PIC: mfhc1   $[[R3:[0-9]+]], $f12
+; MM-MNO-BE-PIC: mfc1    $[[R3:[0-9]+]], $f12
+; MM-MNO-PIC:    sw16    $[[R3]], 4($[[R1]])
+
+; MM-STATIC-PIC: sll16   $[[R0:[0-9]+]], $7, 3
+; MM-STATIC-PIC: addu16  $[[R1:[0-9]+]], $6, $[[R0]]
+; MM-STATIC-PIC: sdc1    $f12, 0($[[R1]])
+
 define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) {
 entry:
   %arrayidx = getelementptr inbounds double, double* %a, i32 %i