diff options
| author | Evgeny Astigeevich <evgeny.astigeevich@arm.com> | 2017-08-24 10:00:25 +0000 |
|---|---|---|
| committer | Evgeny Astigeevich <evgeny.astigeevich@arm.com> | 2017-08-24 10:00:25 +0000 |
| commit | 6e59618ef939347c31fe79437278383ea46ced7d (patch) | |
| tree | 074278ca2f55f88615bd72705eaf7ded9313e4c2 /test/CodeGen/Thumb | |
| parent | 2050a0312db6c29518c48cbd0a98039b55808314 (diff) | |
[ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting illegal modes
ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes
for the Thumb1 target. This causes generation of redundant code and affects
performance.
This fixes PR34106: https://bugs.llvm.org/show_bug.cgi?id=34106
Differential Revision: https://reviews.llvm.org/D36467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311649 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb')
| -rw-r--r-- | test/CodeGen/Thumb/addr-modes.ll | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/test/CodeGen/Thumb/addr-modes.ll b/test/CodeGen/Thumb/addr-modes.ll new file mode 100644 index 00000000000..e6ed01d0547 --- /dev/null +++ b/test/CodeGen/Thumb/addr-modes.ll @@ -0,0 +1,45 @@ +; REQUIRES: asserts +; RUN: llc < %s -debug-only=codegenprepare -o /dev/null 2>&1 | FileCheck %s + +; These are regression tests for +; https://bugs.llvm.org/show_bug.cgi?id=34106 +; "ARMTargetLowering::isLegalAddressingMode can accept incorrect +; addressing modes for Thumb1 target" +; +; The Thumb1 target addressing modes don't support scaling. +; It supports: r1 + r2, where r1 and r2 can be the same register. + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "thumbv6m-arm-none-eabi" + +; Test case 01: %n is scaled by 4 (size of i32). +; Expected: GEP cannot be folded into LOAD. +; CHECK: local addrmode: [Base:%arrayidx] +define i32 @load01(i32* %p, i32 %n) nounwind { +entry: + %arrayidx = getelementptr inbounds i32, i32* %p, i32 %n + %0 = load i32, i32* %arrayidx, align 4 + ret i32 %0 +} + +; Test case 02: No scale of %n is needed because the size of i8 is 1. +; Expected: GEP can be folded into LOAD. +; CHECK: local addrmode: [Base:%p + 1*%n] +define i8 @load02(i8* %p, i32 %n) nounwind { +entry: + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %n + %0 = load i8, i8* %arrayidx + ret i8 %0 +} + +; Test case 03: 2*%x can be represented as %x + %x. +; Expected: GEP can be folded into LOAD. +; CHECK: local addrmode: [2*%x] +define i32 @load03(i32 %x) nounwind { +entry: + %mul = shl nsw i32 %x, 1 + %0 = inttoptr i32 %mul to i32* + %1 = load i32, i32* %0, align 4 + ret i32 %1 +} + |