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author | Roger Ferrer Ibanez <roger.ferreribanez@arm.com> | 2017-12-15 09:24:46 +0000 |
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committer | Roger Ferrer Ibanez <roger.ferreribanez@arm.com> | 2017-12-15 09:24:46 +0000 |
commit | 452fd43f7b41e042d90610a63022e44b9dd06fff (patch) | |
tree | f6b11039fc7f3e2aa9ec1c2c4562a21c4713b311 /test/CodeGen/Thumb | |
parent | 72044ef693b2feac283e28db0e6aa9b2dfc39a14 (diff) |
[ARM] Add tests for D34515
This is NFC and a preparatory step for D34515.
Differential Revision: https://reviews.llvm.org/D41122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320795 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb')
-rw-r--r-- | test/CodeGen/Thumb/branchless-cmp.ll | 149 | ||||
-rw-r--r-- | test/CodeGen/Thumb/long-setcc.ll | 26 |
2 files changed, 165 insertions, 10 deletions
diff --git a/test/CodeGen/Thumb/branchless-cmp.ll b/test/CodeGen/Thumb/branchless-cmp.ll new file mode 100644 index 00000000000..6d700997ada --- /dev/null +++ b/test/CodeGen/Thumb/branchless-cmp.ll @@ -0,0 +1,149 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -verify-machineinstrs -o - | FileCheck %s + +define i32 @test1a(i32 %a, i32 %b) { +; CHECK-LABEL: test1a: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: mov r2, r0 +; CHECK-NEXT: movs r0, #1 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: cmp r2, r1 +; CHECK-NEXT: bne .LBB0_2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: mov r0, r3 +; CHECK-NEXT: .LBB0_2: @ %entry +; CHECK-NEXT: bx lr +entry: + %cmp = icmp ne i32 %a, %b + %cond = zext i1 %cmp to i32 + ret i32 %cond +} + +define i32 @test1b(i32 %a, i32 %b) { +; CHECK-LABEL: test1b: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: mov r2, r0 +; CHECK-NEXT: movs r0, #1 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: cmp r2, r1 +; CHECK-NEXT: beq .LBB1_2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: mov r0, r3 +; CHECK-NEXT: .LBB1_2: @ %entry +; CHECK-NEXT: bx lr +entry: + %cmp = icmp eq i32 %a, %b + %cond = zext i1 %cmp to i32 + ret i32 %cond +} + +define i32 @test2a(i32 %a, i32 %b) { +; CHECK-LABEL: test2a: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: mov r2, r0 +; CHECK-NEXT: movs r0, #1 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: cmp r2, r1 +; CHECK-NEXT: beq .LBB2_2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: mov r0, r3 +; CHECK-NEXT: .LBB2_2: @ %entry +; CHECK-NEXT: bx lr +entry: + %cmp = icmp eq i32 %a, %b + %cond = zext i1 %cmp to i32 + ret i32 %cond +} + +define i32 @test2b(i32 %a, i32 %b) { +; CHECK-LABEL: test2b: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: mov r2, r0 +; CHECK-NEXT: movs r0, #1 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: cmp r2, r1 +; CHECK-NEXT: bne .LBB3_2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: mov r0, r3 +; CHECK-NEXT: .LBB3_2: @ %entry +; CHECK-NEXT: bx lr +entry: + %cmp = icmp ne i32 %a, %b + %cond = zext i1 %cmp to i32 + ret i32 %cond +} + +define i32 @test3a(i32 %a, i32 %b) { +; CHECK-LABEL: test3a: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: mov r2, r0 +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: movs r3, #4 +; CHECK-NEXT: cmp r2, r1 +; CHECK-NEXT: beq .LBB4_2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: mov r0, r3 +; CHECK-NEXT: .LBB4_2: @ %entry +; CHECK-NEXT: bx lr +entry: + %cmp = icmp eq i32 %a, %b + %cond = select i1 %cmp, i32 0, i32 4 + ret i32 %cond +} + +define i32 @test3b(i32 %a, i32 %b) { +; CHECK-LABEL: test3b: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: movs r2, #1 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: cmp r0, r1 +; CHECK-NEXT: beq .LBB5_2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: mov r2, r3 +; CHECK-NEXT: .LBB5_2: @ %entry +; CHECK-NEXT: lsls r0, r2, #2 +; CHECK-NEXT: bx lr +entry: + %cmp = icmp eq i32 %a, %b + %cond = select i1 %cmp, i32 4, i32 0 + ret i32 %cond +} + +; FIXME: This one hasn't changed actually +; but could look like test3b +define i32 @test4a(i32 %a, i32 %b) { +; CHECK-LABEL: test4a: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: mov r2, r0 +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: movs r3, #4 +; CHECK-NEXT: cmp r2, r1 +; CHECK-NEXT: bne .LBB6_2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: mov r0, r3 +; CHECK-NEXT: .LBB6_2: @ %entry +; CHECK-NEXT: bx lr +entry: + %cmp = icmp ne i32 %a, %b + %cond = select i1 %cmp, i32 0, i32 4 + ret i32 %cond +} + +define i32 @test4b(i32 %a, i32 %b) { +; CHECK-LABEL: test4b: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: movs r2, #1 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: cmp r0, r1 +; CHECK-NEXT: bne .LBB7_2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: mov r2, r3 +; CHECK-NEXT: .LBB7_2: @ %entry +; CHECK-NEXT: lsls r0, r2, #2 +; CHECK-NEXT: bx lr +entry: + %cmp = icmp ne i32 %a, %b + %cond = select i1 %cmp, i32 4, i32 0 + ret i32 %cond +} + diff --git a/test/CodeGen/Thumb/long-setcc.ll b/test/CodeGen/Thumb/long-setcc.ll index 7db06d0ae35..1f999f778c9 100644 --- a/test/CodeGen/Thumb/long-setcc.ll +++ b/test/CodeGen/Thumb/long-setcc.ll @@ -1,22 +1,28 @@ ; RUN: llc -mtriple=thumb-eabi < %s | FileCheck %s define i1 @t1(i64 %x) { - %B = icmp slt i64 %x, 0 - ret i1 %B +; CHECK-LABEL: t1: +; CHECK: lsrs r0, r1, #31 + %B = icmp slt i64 %x, 0 + ret i1 %B } define i1 @t2(i64 %x) { - %tmp = icmp ult i64 %x, 4294967296 - ret i1 %tmp +; CHECK-LABEL: t2: +; CHECK: movs r0, #1 +; CHECK: movs r2, #0 +; CHECK: cmp r1, #0 +; CHECK: beq .LBB1_2 + %tmp = icmp ult i64 %x, 4294967296 + ret i1 %tmp } define i1 @t3(i32 %x) { - %tmp = icmp ugt i32 %x, -1 - ret i1 %tmp +; CHECK-LABEL: t3: +; CHECK: movs r0, #0 + %tmp = icmp ugt i32 %x, -1 + ret i1 %tmp } -; CHECK: cmp -; CHECK-NOT: cmp - - +; CHECK-NOT: cmp |