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| author | James Molloy <james.molloy@arm.com> | 2016-09-13 12:12:32 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2016-09-13 12:12:32 +0000 |
| commit | e81b6f315310c64fc7d3c5e30ef463191a10eabd (patch) | |
| tree | a4a8a2a95675ea756ce3fbbc0451d597858daae4 /test/CodeGen/Thumb2 | |
| parent | 7d764370b0442d522df00ec3d55f8a8550f353e7 (diff) | |
[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently
For the common pattern (CMPZ (AND x, #bitmask), #0), we can do some more efficient instruction selection if the bitmask is one consecutive sequence of set bits (32 - clz(bm) - ctz(bm) == popcount(bm)).
1) If the bitmask touches the LSB, then we can remove all the upper bits and set the flags by doing one LSLS.
2) If the bitmask touches the MSB, then we can remove all the lower bits and set the flags with one LSRS.
3) If the bitmask has popcount == 1 (only one set bit), we can shift that bit into the sign bit with one LSLS and change the condition query from NE/EQ to MI/PL (we could also implement this by shifting into the carry bit and branching on BCC/BCS).
4) Otherwise, we can emit a sequence of LSLS+LSRS to remove the upper and lower zero bits of the mask.
1-3 require only one 16-bit instruction and can elide the CMP. 4 requires two 16-bit instructions but can elide the CMP and doesn't require materializing a complex immediate, so is also a win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281323 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Thumb2')
| -rw-r--r-- | test/CodeGen/Thumb2/float-ops.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/Thumb2/float-ops.ll b/test/CodeGen/Thumb2/float-ops.ll index c9f93f2d613..f4c0ef08e84 100644 --- a/test/CodeGen/Thumb2/float-ops.ll +++ b/test/CodeGen/Thumb2/float-ops.ll @@ -259,9 +259,9 @@ define i64 @bitcast_d_to_i(double %a) { define float @select_f(float %a, float %b, i1 %c) { ; CHECK-LABEL: select_f: -; NONE: tst.w r2, #1 +; NONE: lsls r2, r2, #31 ; NONE: moveq r0, r1 -; HARD: tst.w r0, #1 +; HARD: lsls r0, r0, #31 ; VFP4-ALL: vmovne.f32 s1, s0 ; VFP4-ALL: vmov.f32 s0, s1 ; FP-ARMv8: vseleq.f32 s0, s1, s0 @@ -271,18 +271,18 @@ define float @select_f(float %a, float %b, i1 %c) { define double @select_d(double %a, double %b, i1 %c) { ; CHECK-LABEL: select_d: -; NONE: ldr.w [[REG:r[0-9]+]], [sp] -; NONE: ands [[REG]], [[REG]], #1 +; NONE: ldr{{(.w)?}} [[REG:r[0-9]+]], [sp] +; NONE: lsls{{(.w)?}} [[REG]], [[REG]], #31 ; NONE: moveq r0, r2 ; NONE: moveq r1, r3 -; SP: ands r0, r0, #1 +; SP: lsls r0, r0, #31 ; SP-DAG: vmov [[ALO:r[0-9]+]], [[AHI:r[0-9]+]], d0 ; SP-DAG: vmov [[BLO:r[0-9]+]], [[BHI:r[0-9]+]], d1 ; SP: itt ne ; SP-DAG: movne [[BLO]], [[ALO]] ; SP-DAG: movne [[BHI]], [[AHI]] ; SP: vmov d0, [[BLO]], [[BHI]] -; DP: tst.w r0, #1 +; DP: lsls r0, r0, #31 ; VFP4-DP: vmovne.f64 d1, d0 ; VFP4-DP: vmov.f64 d0, d1 ; FP-ARMV8: vseleq.f64 d0, d1, d0 |