[CodeGen] Always use `printReg` to print registers in both MIR and debug

output

As part of the unification of the debug format and the MIR format,
always use `printReg` to print all kinds of registers.

Updated the tests using '_' instead of '%noreg' until we decide which
one we want to be the default one.

Differential Revision: https://reviews.llvm.org/D40421

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319445 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 23 insertions, 23 deletions

diff --git a/test/CodeGen/Thumb2/bicbfi.ll b/test/CodeGen/Thumb2/bicbfi.ll
index fcdb1225db5..5f51f8c46f8 100644
--- a/test/CodeGen/Thumb2/bicbfi.ll
+++ b/test/CodeGen/Thumb2/bicbfi.ll
@@ -14,4 +14,4 @@ define void @f(i32* nocapture %b, i32* nocapture %c, i32 %a) {
   %5 = add nsw i32 %4, %3
   store i32 %5, i32* %b, align 4
   ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir b/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
index a44604372e6..5ba1fc174fe 100644
--- a/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
+++ b/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
@@ -6,23 +6,23 @@ body:             |
     successors: %bb.2, %bb.1
     liveins: %d0, %r0, %r1
 
-    t2CMPri killed %r1, 0, 14, _, implicit-def %cpsr
+    t2CMPri killed %r1, 0, 14, %noreg, implicit-def %cpsr
     t2Bcc %bb.2, 0, killed %cpsr
 
   bb.1:
     liveins: %d0, %r0
 
-    %d16 = VDUP32d killed %r0, 14, _
+    %d16 = VDUP32d killed %r0, 14, %noreg
     ; Verify that the neon instructions haven't been conditionalized:
     ; CHECK-LABEL: NeonVdupMul
     ; CHECK: vdup.32
     ; CHECK: vmul.i32
-    %d0 = VMULv2i32 killed %d16, killed %d0, 14, _
+    %d0 = VMULv2i32 killed %d16, killed %d0, 14, %noreg
 
   bb.2:
     liveins: %d0
 
-    tBX_RET 14, _, implicit %d0
+    tBX_RET 14, %noreg, implicit %d0
 
 ...
 ---
@@ -32,23 +32,23 @@ body:             |
     successors: %bb.1, %bb.2
     liveins: %r0, %r1
 
-    t2CMPri killed %r1, 0, 14, _, implicit-def %cpsr
+    t2CMPri killed %r1, 0, 14, %noreg, implicit-def %cpsr
     t2Bcc %bb.2, 1, killed %cpsr
 
   bb.1:
-    %d0 = VMOVv2i32 0, 14, _
-    tBX_RET 14, _, implicit %d0
+    %d0 = VMOVv2i32 0, 14, %noreg
+    tBX_RET 14, %noreg, implicit %d0
 
   bb.2:
     liveins: %r0
 
-    %d0 = VLDRD killed %r0, 0, 14, _
+    %d0 = VLDRD killed %r0, 0, 14, %noreg
     ; Verify that the neon instruction VMOVv2i32 hasn't been conditionalized,
     ; but the VLDR instruction that is available both in the VFP and Advanced
     ; SIMD extensions has.
     ; CHECK-LABEL: NeonVmovVfpLdr
     ; CHECK-DAG: vmov.i32 d0, #0x0
     ; CHECK-DAG: vldr{{ne|eq}} d0, [r0]
-    tBX_RET 14, _, implicit %d0
+    tBX_RET 14, %noreg, implicit %d0
 
 ...
diff --git a/test/CodeGen/Thumb2/tbb-removeadd.mir b/test/CodeGen/Thumb2/tbb-removeadd.mir
index 10606679134..9798401d9df 100644
--- a/test/CodeGen/Thumb2/tbb-removeadd.mir
+++ b/test/CodeGen/Thumb2/tbb-removeadd.mir
@@ -77,47 +77,47 @@ body:             |
     successors: %bb.6.sw.epilog(0x0ccccccb), %bb.1.entry(0x73333335)
     liveins: %r0, %r1
   
-    tCMPi8 %r0, 4, 14, _, implicit-def %cpsr
+    tCMPi8 %r0, 4, 14, %noreg, implicit-def %cpsr
     t2Bcc %bb.6.sw.epilog, 8, killed %cpsr
   
   bb.1.entry:
     successors: %bb.2.sw.bb(0x1c71c71c), %bb.3.sw.bb1(0x1c71c71c), %bb.5.sw.epilog.sink.split(0x1c71c71c), %bb.6.sw.epilog(0x0e38e38e), %bb.4.sw.bb3(0x1c71c71c)
     liveins: %r0, %r1
   
-    %r2 = t2LEApcrelJT %jump-table.0, 14, _
-    %r3 = t2ADDrs killed %r2, %r0, 18, 14, _, _
-    %r2, dead %cpsr = tMOVi8 1, 14, _
+    %r2 = t2LEApcrelJT %jump-table.0, 14, %noreg
+    %r3 = t2ADDrs killed %r2, %r0, 18, 14, %noreg, %noreg
+    %r2, dead %cpsr = tMOVi8 1, 14, %noreg
     t2BR_JT killed %r3, killed %r0, %jump-table.0
   
   bb.2.sw.bb:
     successors: %bb.5.sw.epilog.sink.split(0x80000000)
     liveins: %r1
   
-    %r2, dead %cpsr = tMOVi8 0, 14, _
-    t2B %bb.5.sw.epilog.sink.split, 14, _
+    %r2, dead %cpsr = tMOVi8 0, 14, %noreg
+    t2B %bb.5.sw.epilog.sink.split, 14, %noreg
   
   bb.3.sw.bb1:
     successors: %bb.5.sw.epilog.sink.split(0x80000000)
     liveins: %r1
   
-    %r0, dead %cpsr = tMOVi8 0, 14, _
-    %r2, dead %cpsr = tMOVi8 1, 14, _
-    tSTRi killed %r0, %r1, 0, 14, _ :: (store 4 into %ir.p)
-    t2B %bb.5.sw.epilog.sink.split, 14, _
+    %r0, dead %cpsr = tMOVi8 0, 14, %noreg
+    %r2, dead %cpsr = tMOVi8 1, 14, %noreg
+    tSTRi killed %r0, %r1, 0, 14, %noreg :: (store 4 into %ir.p)
+    t2B %bb.5.sw.epilog.sink.split, 14, %noreg
   
   bb.4.sw.bb3:
     successors: %bb.5.sw.epilog.sink.split(0x80000000)
     liveins: %r1
   
-    %r2, dead %cpsr = tMOVi8 2, 14, _
+    %r2, dead %cpsr = tMOVi8 2, 14, %noreg
   
   bb.5.sw.epilog.sink.split:
     successors: %bb.6.sw.epilog(0x80000000)
     liveins: %r1, %r2
   
-    tSTRi killed %r2, killed %r1, 0, 14, _ :: (store 4 into %ir.p)
+    tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.p)
   
   bb.6.sw.epilog:
-    tBX_RET 14, _
+    tBX_RET 14, %noreg
 
 ...