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author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2017-09-29 14:31:39 +0000 |
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committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2017-09-29 14:31:39 +0000 |
commit | e2ff20cbface83819e447eef1345ddaa9bfec441 (patch) | |
tree | afb341e3ec2e33ad65aebc6827c37602b1f0d111 /test/CodeGen/SystemZ | |
parent | 1be91bb29f0fc97083ee5eeee701f1a5a9388e50 (diff) |
[SystemZ] implement shouldCoalesce()
Implement shouldCoalesce() to help regalloc avoid running out of GR128
registers.
If a COPY involving a subreg of a GR128 is coalesced, the live range of the
GR128 virtual register will be extended. If this happens where there are
enough phys-reg clobbers present, regalloc will run out of registers (if
there is not a single GR128 allocatable register available).
This patch tries to allow coalescing only when it can prove that this will be
safe by checking the (local) interval in question.
Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D37899
https://bugs.llvm.org/show_bug.cgi?id=34610
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314516 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ')
-rw-r--r-- | test/CodeGen/SystemZ/regalloc-GR128.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/regalloc-GR128.ll b/test/CodeGen/SystemZ/regalloc-GR128.ll new file mode 100644 index 00000000000..e84e23613d9 --- /dev/null +++ b/test/CodeGen/SystemZ/regalloc-GR128.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -O3 -o /dev/null +; +; Test that regalloc does not run out of registers + +; This test will include a GR128 virtual reg. +define void @test0(i64 %dividend, i64 %divisor) { + %rem = urem i64 %dividend, %divisor + call void asm sideeffect "", "{r0},{r1},{r2},{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14}"(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 %rem) + ret void +} + +; This test will include an ADDR128 virtual reg. +define i64 @test1(i64 %dividend, i64 %divisor) { +%rem = urem i64 %dividend, %divisor +call void asm sideeffect "", "{r2},{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14}"(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 %rem) +%ret = add i64 %rem, 1 +ret i64 %ret +} |