[CodeGen] Unify MBB reference format in both MIR and debug output

As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665 91177308-0d34-0410-b5e6-96231b3b80d8

10 files changed, 93 insertions, 93 deletions

diff --git a/test/CodeGen/SystemZ/DAGCombiner_isAlias.ll b/test/CodeGen/SystemZ/DAGCombiner_isAlias.ll
index 8c31f073276..a42f625a536 100644
--- a/test/CodeGen/SystemZ/DAGCombiner_isAlias.ll
+++ b/test/CodeGen/SystemZ/DAGCombiner_isAlias.ll
@@ -9,7 +9,7 @@
 ; store i1 true, i1* %g_717.sink.i, align 4
 ; %.b = load i1, i1* @g_2, align 4
 
-; CHECK: # BB#6: # %crc32_gentab.exit
+; CHECK: # %bb.6: # %crc32_gentab.exit
 ; CHECK:        larl    %r2, g_2
 ; CHECK-NEXT:   llc     %r3, 0(%r2)
 ; CHECK-NOT:    %r2
diff --git a/test/CodeGen/SystemZ/dag-combine-02.ll b/test/CodeGen/SystemZ/dag-combine-02.ll
index b20133facb8..2d96aafb938 100644
--- a/test/CodeGen/SystemZ/dag-combine-02.ll
+++ b/test/CodeGen/SystemZ/dag-combine-02.ll
@@ -93,7 +93,7 @@ define signext i32 @main(i32 signext, i8** nocapture readonly) local_unnamed_add
   br i1 %60, label %61, label %13
 
 ; <label>:61:                                     ; preds = %13
-; CHECK-LABEL: BB#6:
+; CHECK-LABEL: %bb.6:
 ; CHECK: stgrl   %r1, g_56
 ; CHECK: llhrl   %r1, g_56+6
 ; CHECK: stgrl   %r2, g_56
diff --git a/test/CodeGen/SystemZ/int-cmp-51.ll b/test/CodeGen/SystemZ/int-cmp-51.ll
index 85a0e4b4d3a..6d00dd843ae 100644
--- a/test/CodeGen/SystemZ/int-cmp-51.ll
+++ b/test/CodeGen/SystemZ/int-cmp-51.ll
@@ -8,7 +8,7 @@ declare void @bar(i8)
 
 ; Check the low end of the CH range.
 define void @f1(i32 %lhs) {
-; CHECK-LABEL: BB#1:
+; CHECK-LABEL: %bb.1:
 ; CHECK-NOT: cijlh %r0, 1, .LBB0_3
 
 entry:
diff --git a/test/CodeGen/SystemZ/pr32372.ll b/test/CodeGen/SystemZ/pr32372.ll
index c18e238fbaf..d252a9a96de 100644
--- a/test/CodeGen/SystemZ/pr32372.ll
+++ b/test/CodeGen/SystemZ/pr32372.ll
@@ -3,7 +3,7 @@
 
 define void @pr32372(i8*) {
 ; CHECK-LABEL: pr32372:
-; CHECK:       # BB#0: # %BB
+; CHECK:       # %bb.0: # %BB
 ; CHECK-NEXT:    llc %r1, 0(%r2)
 ; CHECK-NEXT:    mvhhi 0(%r1), -3825
 ; CHECK-NEXT:    llill %r0, 0
diff --git a/test/CodeGen/SystemZ/pr32505.ll b/test/CodeGen/SystemZ/pr32505.ll
index c5382b27181..288d0b83863 100644
--- a/test/CodeGen/SystemZ/pr32505.ll
+++ b/test/CodeGen/SystemZ/pr32505.ll
@@ -5,7 +5,7 @@ target triple = "s390x-ibm-linux"
 
 define <2 x float> @pr32505(<2 x i8> * %a) {
 ; CHECK-LABEL: pr32505:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lbh %r0, 1(%r2)
 ; CHECK-NEXT:    lbh %r1, 0(%r2)
 ; CHECK-NEXT:    ldgr %f0, %r1
diff --git a/test/CodeGen/SystemZ/strcmp-01.ll b/test/CodeGen/SystemZ/strcmp-01.ll
index a30663a13f1..ef05d832e73 100644
--- a/test/CodeGen/SystemZ/strcmp-01.ll
+++ b/test/CodeGen/SystemZ/strcmp-01.ll
@@ -11,7 +11,7 @@ define i32 @f1(i8 *%src1, i8 *%src2) {
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: clst %r2, %r3
 ; CHECK-NEXT: jo [[LABEL]]
-; CHECK-NEXT: BB#{{[0-9]+}}
+; CHECK-NEXT: %bb.{{[0-9]+}}
 ; CHECK-NEXT: ipm [[REG:%r[0-5]]]
 ; CHECK: srl [[REG]], 28
 ; CHECK: rll %r2, [[REG]], 31
@@ -27,7 +27,7 @@ define void @f2(i8 *%src1, i8 *%src2, i32 *%dest) {
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: clst %r2, %r3
 ; CHECK-NEXT: jo [[LABEL]]
-; CHECK-NEXT: BB#{{[0-9]+}}
+; CHECK-NEXT: %bb.{{[0-9]+}}
 ; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %res = call i32 @strcmp(i8 *%src1, i8 *%src2)
@@ -50,7 +50,7 @@ define i32 @f3(i8 *%src1, i8 *%src2, i32 *%dest) {
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: clst %r2, %r3
 ; CHECK-NEXT: jo [[LABEL]]
-; CHECK-NEXT: BB#{{[0-9]+}}
+; CHECK-NEXT: %bb.{{[0-9]+}}
 ; CHECK-NEXT: ipm [[REG:%r[0-5]]]
 ; CHECK: srl [[REG]], 28
 ; CHECK: rll %r2, [[REG]], 31
diff --git a/test/CodeGen/SystemZ/strlen-01.ll b/test/CodeGen/SystemZ/strlen-01.ll
index 16161d4d2c8..2fb63425fe0 100644
--- a/test/CodeGen/SystemZ/strlen-01.ll
+++ b/test/CodeGen/SystemZ/strlen-01.ll
@@ -15,7 +15,7 @@ define i64 @f1(i32 %dummy, i8 *%src) {
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK-NEXT: srst %r2, [[REG]]
 ; CHECK-NEXT: jo [[LABEL]]
-; CHECK-NEXT: BB#{{[0-9]+}}
+; CHECK-NEXT: %bb.{{[0-9]+}}
 ; CHECK-NEXT: sgr %r2, %r3
 ; CHECK: br %r14
   %res = call i64 @strlen(i8 *%src)
@@ -31,7 +31,7 @@ define i64 @f2(i64 %len, i8 *%src) {
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK-NEXT: srst %r2, [[REG]]
 ; CHECK-NEXT: jo [[LABEL]]
-; CHECK-NEXT: BB#{{[0-9]+}}
+; CHECK-NEXT: %bb.{{[0-9]+}}
 ; CHECK-NEXT: sgr %r2, %r3
 ; CHECK: br %r14
   %res = call i64 @strnlen(i8 *%src, i64 %len)
diff --git a/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll b/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
index eafb0122e90..ac12861603a 100644
--- a/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
+++ b/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll
@@ -7,7 +7,7 @@
 
 define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
 ; CHECK-LABEL: fun0:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
@@ -22,7 +22,7 @@ define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %
 
 define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
 ; CHECK-LABEL: fun1:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
@@ -38,7 +38,7 @@ define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8>
 
 define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
 ; CHECK-LABEL: fun2:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v30, %v27
 ; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v25
 ; CHECK-DAG:     vceqb [[REG2:%v[0-9]+]], %v24, %v26
@@ -55,7 +55,7 @@ define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x
 
 define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
 ; CHECK-LABEL: fun3:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vuphb [[REG2:%v[0-9]+]], [[REG0]]
 ; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
@@ -78,7 +78,7 @@ define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16
 
 define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4, <32 x i8> %val5, <32 x i8> %val6) {
 ; CHECK-LABEL: fun4:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v28
 ; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v26, %v30
 ; CHECK-DAG:     vceqb [[REG2:%v[0-9]+]], %v25, %v29
@@ -101,7 +101,7 @@ define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x
 
 define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
 ; CHECK-LABEL: fun5:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vpkh [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
 ; CHECK-DAG:     vceqb [[REG2:%v[0-9]+]], %v28, %v30
@@ -117,7 +117,7 @@ define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8>
 
 define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
 ; CHECK-LABEL: fun6:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqb %v1, %v28, %v30
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vuphb %v1, %v1
@@ -133,7 +133,7 @@ define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8
 
 define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i32> %val5, <2 x i32> %val6) {
 ; CHECK-LABEL: fun7:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqb %v1, %v28, %v30
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vuphb %v1, %v1
@@ -150,7 +150,7 @@ define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8
 
 define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i8> %val5, <8 x i8> %val6) {
 ; CHECK-LABEL: fun8:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
@@ -166,7 +166,7 @@ define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i1
 
 define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i16> %val5, <8 x i16> %val6) {
 ; CHECK-LABEL: fun9:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
@@ -181,7 +181,7 @@ define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i
 
 define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i32> %val5, <8 x i32> %val6) {
 ; CHECK-LABEL: fun10:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vx [[REG2:%v[0-9]+]], [[REG0]], [[REG1]]
@@ -200,7 +200,7 @@ define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x
 
 define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i8> %val5, <16 x i8> %val6) {
 ; CHECK-LABEL: fun11:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vl [[REG0:%v[0-9]+]], 192(%r15)
 ; CHECK-DAG:     vl [[REG1:%v[0-9]+]], 208(%r15)
 ; CHECK-DAG:     vl [[REG2:%v[0-9]+]], 160(%r15)
@@ -229,7 +229,7 @@ define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <1
 
 define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i16> %val5, <16 x i16> %val6) {
 ; CHECK-LABEL: fun12:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vl [[REG0:%v[0-9]+]], 192(%r15)
 ; CHECK-DAG:     vl [[REG1:%v[0-9]+]], 208(%r15)
 ; CHECK-DAG:     vl [[REG2:%v[0-9]+]], 160(%r15)
@@ -260,7 +260,7 @@ define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <
 
 define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i16> %val5, <2 x i16> %val6) {
 ; CHECK-LABEL: fun13:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqg %v1, %v28, %v30
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vpkg %v1, %v1, %v1
@@ -277,7 +277,7 @@ define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x
 
 define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
 ; CHECK-LABEL: fun14:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqg %v1, %v28, %v30
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vpkg %v1, %v1, %v1
@@ -293,7 +293,7 @@ define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x
 
 define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
 ; CHECK-LABEL: fun15:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vuphf [[REG1:%v[0-9]+]], [[REG0]]
 ; CHECK-DAG:     vceqg [[REG2:%v[0-9]+]], %v28, %v30
@@ -309,7 +309,7 @@ define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x
 
 define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i16> %val5, <4 x i16> %val6) {
 ; CHECK-LABEL: fun16:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vpkf [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
 ; CHECK-DAG:     vceqh [[REG2:%v[0-9]+]], %v28, %v30
@@ -325,7 +325,7 @@ define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
 
 define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i32> %val5, <4 x i32> %val6) {
 ; CHECK-LABEL: fun17:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqh %v1, %v28, %v30
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vuphh %v1, %v1
@@ -341,7 +341,7 @@ define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
 
 define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i64> %val5, <4 x i64> %val6) {
 ; CHECK-LABEL: fun18:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqh %v1, %v28, %v30
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vuphh %v1, %v1
@@ -361,7 +361,7 @@ define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
 
 define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i16> %val5, <8 x i16> %val6) {
 ; CHECK-LABEL: fun19:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v28
 ; CHECK-DAG:     vceqf [[REG1:%v[0-9]+]], %v26, %v30
 ; CHECK-DAG:     vceqf [[REG2:%v[0-9]+]], %v25, %v29
@@ -382,7 +382,7 @@ define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x
 
 define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i32> %val5, <8 x i32> %val6) {
 ; CHECK-LABEL: fun20:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v28
 ; CHECK-DAG:     vceqf [[REG1:%v[0-9]+]], %v26, %v30
 ; CHECK-DAG:     vceqf [[REG2:%v[0-9]+]], %v25, %v29
@@ -405,7 +405,7 @@ define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x
 
 define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
 ; CHECK-LABEL: fun21:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqg [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vceqg [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
@@ -421,7 +421,7 @@ define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x
 
 define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
 ; CHECK-LABEL: fun22:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqg [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vceqg [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
@@ -436,7 +436,7 @@ define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x
 
 define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i32> %val5, <4 x i32> %val6) {
 ; CHECK-LABEL: fun23:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqg %v0, %v26, %v30
 ; CHECK-NEXT:    vceqg %v1, %v24, %v28
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
@@ -453,7 +453,7 @@ define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x
 
 define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i64> %val5, <4 x i64> %val6) {
 ; CHECK-LABEL: fun24:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqf [[REG0:%v[0-9]+]], %v25, %v27
 ; CHECK-NEXT:    vuphf [[REG1:%v[0-9]+]], [[REG0]]
 ; CHECK-NEXT:    vmrlg [[REG2:%v[0-9]+]], [[REG0]], [[REG0]]
@@ -476,7 +476,7 @@ define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x
 
 define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
 ; CHECK-LABEL: fun25:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
@@ -495,7 +495,7 @@ define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %va
 ; CHECK-NEXT:    br %r14
 ;
 ; CHECK-Z14-LABEL: fun25:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchdb %v1, %v28, %v30
 ; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
 ; CHECK-Z14-NEXT:    vpkg %v1, %v1, %v1
@@ -511,7 +511,7 @@ define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %va
 
 define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {
 ; CHECK-LABEL: fun26:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
@@ -530,7 +530,7 @@ define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %v
 ; CHECK-NEXT:    br %r14
 ;
 ; CHECK-Z14-LABEL: fun26:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
 ; CHECK-Z14-NEXT:    vuphf %v0, %v0
 ; CHECK-Z14-NEXT:    vfchdb %v1, %v28, %v30
@@ -547,7 +547,7 @@ define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %v
 ; Also check a widening select of a vector of floats
 define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x float> %val5, <2 x float> %val6) {
 ; CHECK-LABEL: fun27:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vo %v0, [[REG0]], [[REG1]]
@@ -564,7 +564,7 @@ define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i
 
 define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
 ; CHECK-LABEL: fun28:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vmrlf [[REG0:%v[0-9]+]], %v26, %v26
 ; CHECK-DAG:     vmrlf [[REG1:%v[0-9]+]], %v24, %v24
 ; CHECK-DAG:     vldeb [[REG2:%v[0-9]+]], [[REG0]]
@@ -592,7 +592,7 @@ define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val
 ; CHECK-NEXT:    br %r14
 ;
 ; CHECK-Z14-LABEL: fun28:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
 ; CHECK-Z14-NEXT:    vfchsb %v1, %v28, %v30
 ; CHECK-Z14-NEXT:    vx %v0, %v0, %v1
@@ -607,7 +607,7 @@ define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val
 
 define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
 ; CHECK-LABEL: fun29:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
@@ -639,7 +639,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %va
 ; CHECK-NEXT:    br %r14
 ;
 ; CHECK-Z14-LABEL: fun29:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
 ; CHECK-Z14-NEXT:    vfchsb %v1, %v28, %v30
 ; CHECK-Z14-NEXT:    vx %v0, %v0, %v1
@@ -658,7 +658,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %va
 
 define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %val3, <8 x double> %val4, <8 x float> %val5, <8 x float> %val6) {
 ; CHECK-LABEL: fun30:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmrlf %v16, %v28, %v28
 ; CHECK-NEXT:    vmrlf %v17, %v24, %v24
 ; CHECK-NEXT:    vldeb %v16, %v16
@@ -702,7 +702,7 @@ define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %va
 ; CHECK-NEXT:    br %r14
 ;
 ; CHECK-Z14-LABEL: fun30:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vl %v4, 192(%r15)
 ; CHECK-Z14-NEXT:    vl %v5, 208(%r15)
 ; CHECK-Z14-NEXT:    vl %v6, 160(%r15)
@@ -733,7 +733,7 @@ define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %va
 
 define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
 ; CHECK-LABEL: fun31:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vfchdb [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vfchdb [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
@@ -749,7 +749,7 @@ define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x double> %
 
 define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {
 ; CHECK-LABEL: fun32:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vfchdb [[REG0:%v[0-9]+]], %v24, %v26
 ; CHECK-DAG:     vfchdb [[REG1:%v[0-9]+]], %v28, %v30
 ; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
@@ -764,7 +764,7 @@ define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double>
 
 define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
 ; CHECK-LABEL: fun33:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vfchdb %v0, %v26, %v30
 ; CHECK-NEXT:    vfchdb %v1, %v24, %v28
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
@@ -784,7 +784,7 @@ define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %v
 ; CHECK-NEXT:    br %r14
 ;
 ; CHECK-Z14-LABEL: fun33:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchdb %v0, %v26, %v30
 ; CHECK-Z14-NEXT:    vfchdb %v1, %v24, %v28
 ; CHECK-Z14-NEXT:    vpkg %v0, %v1, %v0
@@ -801,7 +801,7 @@ define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %v
 
 define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
 ; CHECK-LABEL: fun34:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmrlf [[REG0:%v[0-9]+]], %v27, %v27
 ; CHECK-NEXT:    vmrlf [[REG1:%v[0-9]+]], %v25, %v25
 ; CHECK-NEXT:    vldeb [[REG2:%v[0-9]+]], [[REG0]]
@@ -827,7 +827,7 @@ define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %
 ; CHECK-NEXT:    br %r14
 ;
 ; CHECK-Z14-LABEL: fun34:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchsb %v4, %v25, %v27
 ; CHECK-Z14-NEXT:    vuphf %v5, %v4
 ; CHECK-Z14-NEXT:    vmrlg %v4, %v4, %v4
diff --git a/test/CodeGen/SystemZ/vec-cmpsel.ll b/test/CodeGen/SystemZ/vec-cmpsel.ll
index fb8ee56b990..200c25179d3 100644
--- a/test/CodeGen/SystemZ/vec-cmpsel.ll
+++ b/test/CodeGen/SystemZ/vec-cmpsel.ll
@@ -6,7 +6,7 @@
 
 define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4) {
 ; CHECK-LABEL: fun0:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqb %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
@@ -17,7 +17,7 @@ define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %
 
 define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i16> %val3, <2 x i16> %val4) {
 ; CHECK-LABEL: fun1:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqb %v0, %v24, %v26
 ; CHECK-NEXT:    vuphb %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
@@ -29,7 +29,7 @@ define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i16> %val3, <2 x i16
 
 define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4) {
 ; CHECK-LABEL: fun2:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqb %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
@@ -40,7 +40,7 @@ define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x
 
 define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4) {
 ; CHECK-LABEL: fun3:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqb %v0, %v24, %v26
 ; CHECK-DAG:     vuphb [[REG0:%v[0-9]+]], %v0
 ; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
@@ -55,7 +55,7 @@ define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16
 
 define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4) {
 ; CHECK-LABEL: fun4:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v26, %v30
 ; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v24, %v28
 ; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
@@ -68,7 +68,7 @@ define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x
 
 define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4) {
 ; CHECK-LABEL: fun5:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vpkh %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
@@ -80,7 +80,7 @@ define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8>
 
 define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4) {
 ; CHECK-LABEL: fun6:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
@@ -91,7 +91,7 @@ define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i
 
 define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i32> %val3, <2 x i32> %val4) {
 ; CHECK-LABEL: fun7:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vuphh %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
@@ -103,7 +103,7 @@ define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i32> %val3, <2 x i
 
 define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i8> %val3, <8 x i8> %val4) {
 ; CHECK-LABEL: fun8:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vpkh %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
@@ -115,7 +115,7 @@ define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i8> %val3, <8 x i8>
 
 define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4) {
 ; CHECK-LABEL: fun9:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
@@ -126,7 +126,7 @@ define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i
 
 define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x i32> %val4) {
 ; CHECK-LABEL: fun10:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqh %v0, %v24, %v26
 ; CHECK-DAG:     vuphh [[REG0:%v[0-9]+]], %v0
 ; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
@@ -141,7 +141,7 @@ define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x
 
 define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i8> %val3, <16 x i8> %val4) {
 ; CHECK-LABEL: fun11:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqh %v0, %v26, %v30
 ; CHECK-NEXT:    vceqh %v1, %v24, %v28
 ; CHECK-NEXT:    vpkh %v0, %v1, %v0
@@ -154,7 +154,7 @@ define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i8> %val3, <16
 
 define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4) {
 ; CHECK-LABEL: fun12:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v26, %v30
 ; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v24, %v28
 ; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
@@ -167,7 +167,7 @@ define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <
 
 define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i16> %val3, <2 x i16> %val4) {
 ; CHECK-LABEL: fun13:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vpkf %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
@@ -179,7 +179,7 @@ define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i16> %val3, <2 x
 
 define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4) {
 ; CHECK-LABEL: fun14:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
@@ -190,7 +190,7 @@ define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x
 
 define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4) {
 ; CHECK-LABEL: fun15:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vuphf %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
@@ -202,7 +202,7 @@ define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x
 
 define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4) {
 ; CHECK-LABEL: fun16:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vpkf %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
@@ -214,7 +214,7 @@ define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x
 
 define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4) {
 ; CHECK-LABEL: fun17:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
@@ -225,7 +225,7 @@ define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x
 
 define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x i64> %val4) {
 ; CHECK-LABEL: fun18:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqf %v0, %v24, %v26
 ; CHECK-DAG:     vuphf [[REG0:%v[0-9]+]], %v0
 ; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
@@ -240,7 +240,7 @@ define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x
 
 define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i16> %val3, <8 x i16> %val4) {
 ; CHECK-LABEL: fun19:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqf %v0, %v26, %v30
 ; CHECK-NEXT:    vceqf %v1, %v24, %v28
 ; CHECK-NEXT:    vpkf %v0, %v1, %v0
@@ -253,7 +253,7 @@ define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i16> %val3, <8 x
 
 define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4) {
 ; CHECK-LABEL: fun20:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v26, %v30
 ; CHECK-DAG:     vceqf [[REG1:%v[0-9]+]], %v24, %v28
 ; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
@@ -266,7 +266,7 @@ define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x
 
 define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i32> %val3, <2 x i32> %val4) {
 ; CHECK-LABEL: fun21:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqg %v0, %v24, %v26
 ; CHECK-NEXT:    vpkg %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
@@ -278,7 +278,7 @@ define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i32> %val3, <2 x
 
 define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4) {
 ; CHECK-LABEL: fun22:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqg %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
@@ -289,7 +289,7 @@ define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x
 
 define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4) {
 ; CHECK-LABEL: fun23:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqg %v0, %v26, %v30
 ; CHECK-NEXT:    vceqg %v1, %v24, %v28
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
@@ -302,7 +302,7 @@ define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x
 
 define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4) {
 ; CHECK-LABEL: fun24:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vceqg [[REG0:%v[0-9]+]], %v26, %v30
 ; CHECK-DAG:     vceqg [[REG1:%v[0-9]+]], %v24, %v28
 ; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
@@ -315,7 +315,7 @@ define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x
 
 define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x float> %val3, <2 x float> %val4) {
 ; CHECK-LABEL: fun25:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
@@ -331,7 +331,7 @@ define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x float> %val
 ; CHECK-NEXT:    br %r14
 
 ; CHECK-Z14-LABEL: fun25:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
 ; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v30, %v0
 ; CHECK-Z14-NEXT:    br %r14
@@ -343,7 +343,7 @@ define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x float> %val
 
 define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4) {
 ; CHECK-LABEL: fun26:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
@@ -360,7 +360,7 @@ define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %v
 ; CHECK-NEXT:    br %r14
 
 ; CHECK-Z14-LABEL: fun26:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
 ; CHECK-Z14-NEXT:    vuphf   %v0, %v0
 ; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v30, %v0
@@ -374,7 +374,7 @@ define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %v
 ; Test a widening select of floats.
 define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x float> %val3, <2 x float> %val4) {
 ; CHECK-LABEL: fun27:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vceqb %v0, %v24, %v26
 ; CHECK-NEXT:    vuphb %v0, %v0
 ; CHECK-NEXT:    vuphh %v0, %v0
@@ -388,7 +388,7 @@ define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x float> %val3, <2
 
 define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4) {
 ; CHECK-LABEL: fun28:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
@@ -404,7 +404,7 @@ define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val
 ; CHECK-NEXT:    br %r14
 
 ; CHECK-Z14-LABEL: fun28:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
 ; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v30, %v0
 ; CHECK-Z14-NEXT:    br %r14
@@ -416,7 +416,7 @@ define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val
 
 define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x double> %val3, <4 x double> %val4) {
 ; CHECK-LABEL: fun29:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmrlf %v0, %v26, %v26
 ; CHECK-NEXT:    vmrlf %v1, %v24, %v24
 ; CHECK-NEXT:    vldeb %v0, %v0
@@ -436,7 +436,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x double> %v
 ; CHECK-NEXT:    br %r14
 
 ; CHECK-Z14-LABEL: fun29:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
 ; CHECK-Z14-DAG:     vuphf   [[REG0:%v[0-9]+]], %v0
 ; CHECK-Z14-DAG:     vmrlg   [[REG1:%v[0-9]+]], %v0, %v0
@@ -452,7 +452,7 @@ define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x double> %v
 
 define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x float> %val3, <8 x float> %val4) {
 ; CHECK-Z14-LABEL: fun30:
-; CHECK-Z14:       # BB#0:
+; CHECK-Z14:       # %bb.0:
 ; CHECK-Z14-DAG:     vfchsb  [[REG0:%v[0-9]+]], %v26, %v30
 ; CHECK-Z14-DAG:     vfchsb  [[REG1:%v[0-9]+]], %v24, %v28
 ; CHECK-Z14-DAG:     vsel    %v24, %v25, %v29, [[REG1]]
@@ -465,7 +465,7 @@ define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x float> %val
 
 define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x float> %val3, <2 x float> %val4) {
 ; CHECK-LABEL: fun31:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vfchdb %v0, %v24, %v26
 ; CHECK-NEXT:    vpkg %v0, %v0, %v0
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
@@ -478,7 +478,7 @@ define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x float> %v
 
 define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4) {
 ; CHECK-LABEL: fun32:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vfchdb %v0, %v24, %v26
 ; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
 ; CHECK-NEXT:    br %r14
@@ -489,7 +489,7 @@ define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double>
 
 define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4) {
 ; CHECK-LABEL: fun33:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vfchdb %v0, %v26, %v30
 ; CHECK-NEXT:    vfchdb %v1, %v24, %v28
 ; CHECK-NEXT:    vpkg %v0, %v1, %v0
@@ -502,7 +502,7 @@ define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %v
 
 define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x double> %val3, <4 x double> %val4) {
 ; CHECK-LABEL: fun34:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-DAG:     vfchdb [[REG0:%v[0-9]+]], %v26, %v30
 ; CHECK-DAG:     vfchdb [[REG1:%v[0-9]+]], %v24, %v28
 ; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
diff --git a/test/CodeGen/SystemZ/vec-trunc-to-i1.ll b/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
index 705fe3dbac9..73d4c47a840 100644
--- a/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
+++ b/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
@@ -7,7 +7,7 @@
 
 define void @pr32275(<4 x i8> %B15) {
 ; CHECK-LABEL: pr32275:
-; CHECK:       # BB#0: # %BB
+; CHECK:       # %bb.0: # %BB
 ; CHECK-NEXT:    vrepif %v0, 1
 ; CHECK-NEXT:  .LBB0_1: # %CF34
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -22,7 +22,7 @@ define void @pr32275(<4 x i8> %B15) {
 ; CHECK-NEXT:    vlgvf %r0, %v1, 3
 ; CHECK-NEXT:    tmll %r0, 1
 ; CHECK-NEXT:    jne .LBB0_1
-; CHECK-NEXT:  # BB#2: # %CF36
+; CHECK-NEXT:  # %bb.2: # %CF36
 ; CHECK-NEXT:    br %r14
 BB:
   br label %CF34