diff options
| author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2016-10-20 08:27:16 +0000 |
|---|---|---|
| committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2016-10-20 08:27:16 +0000 |
| commit | a0075169373b99a016f3cf5f00f7e11d723583c2 (patch) | |
| tree | 296242c112b211911ea7f277f1397fa703ed6cbf /test/CodeGen/SystemZ | |
| parent | 3e0be6fc226444c3fd7e896dee28f17642aa321a (diff) | |
[SystemZ] Post-RA scheduler implementation
Post-RA sched strategy and scheduling instruction annotations for z196, zEC12
and z13.
This scheduler optimizes decoder grouping and balances processor resources
(including side steering the FPd unit instructions).
The SystemZHazardRecognizer keeps track of the scheduling state, which can
be dumped with -debug-only=misched.
Reviers: Ulrich Weigand, Andrew Trick.
https://reviews.llvm.org/D17260
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284704 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ')
| -rw-r--r-- | test/CodeGen/SystemZ/vec-args-06.ll | 32 | ||||
| -rw-r--r-- | test/CodeGen/SystemZ/vec-perm-12.ll | 6 |
2 files changed, 19 insertions, 19 deletions
diff --git a/test/CodeGen/SystemZ/vec-args-06.ll b/test/CodeGen/SystemZ/vec-args-06.ll index b26131ca1d4..e8b59c697fd 100644 --- a/test/CodeGen/SystemZ/vec-args-06.ll +++ b/test/CodeGen/SystemZ/vec-args-06.ll @@ -42,29 +42,29 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double>, ; CHECK-LABEL: f2: ; CHECK: larl [[TMP:%r[0-5]]], .LCPI ; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) -; CHECK: vst [[VTMP]], 128(%r2) -; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK-DAG: vst [[VTMP]], 128(%r2) +; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI ; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) -; CHECK: vst [[VTMP]], 112(%r2) -; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK-DAG: vst [[VTMP]], 112(%r2) +; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI ; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) -; CHECK: vst [[VTMP]], 96(%r2) -; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK-DAG: vst [[VTMP]], 96(%r2) +; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI ; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) -; CHECK: vst [[VTMP]], 80(%r2) -; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK-DAG: vst [[VTMP]], 80(%r2) +; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI ; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) -; CHECK: vst [[VTMP]], 64(%r2) -; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK-DAG: vst [[VTMP]], 64(%r2) +; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI ; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) -; CHECK: vst [[VTMP]], 48(%r2) -; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK-DAG: vst [[VTMP]], 48(%r2) +; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI ; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) -; CHECK: vst [[VTMP]], 32(%r2) -; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK-DAG: vst [[VTMP]], 32(%r2) +; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI ; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) -; CHECK: vst [[VTMP]], 16(%r2) -; CHECK: larl [[TMP:%r[0-5]]], .LCPI +; CHECK-DAG: vst [[VTMP]], 16(%r2) +; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI ; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]]) ; CHECK: vst [[VTMP]], 0(%r2) ; CHECK: br %r14 diff --git a/test/CodeGen/SystemZ/vec-perm-12.ll b/test/CodeGen/SystemZ/vec-perm-12.ll index b70b13d9068..c6af5d051b8 100644 --- a/test/CodeGen/SystemZ/vec-perm-12.ll +++ b/test/CodeGen/SystemZ/vec-perm-12.ll @@ -7,9 +7,9 @@ define <4 x i32> @f1(<4 x i32> %x, i64 %y) { ; CHECK-CODE-LABEL: f1: -; CHECK-CODE: vlvgf [[ELT:%v[0-9]+]], %r2, 0 -; CHECK-CODE: larl [[REG:%r[0-5]]], -; CHECK-CODE: vl [[MASK:%v[0-9]+]], 0([[REG]]) +; CHECK-CODE-DAG: vlvgf [[ELT:%v[0-9]+]], %r2, 0 +; CHECK-CODE-DAG: larl [[REG:%r[0-5]]], +; CHECK-CODE-DAG: vl [[MASK:%v[0-9]+]], 0([[REG]]) ; CHECK-CODE: vperm %v24, %v24, [[ELT]], [[MASK]] ; CHECK-CODE: br %r14 |