Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.

This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8

314 files changed, 2901 insertions, 2901 deletions

diff --git a/test/CodeGen/SystemZ/addr-01.ll b/test/CodeGen/SystemZ/addr-01.ll
index bf2ad7bda9c..cf4ed891525 100644
--- a/test/CodeGen/SystemZ/addr-01.ll
+++ b/test/CodeGen/SystemZ/addr-01.ll
@@ -5,7 +5,7 @@
 
 ; A simple index address.
 define void @f1(i64 %addr, i64 %index) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
   %add = add i64 %addr, %index
@@ -16,7 +16,7 @@ define void @f1(i64 %addr, i64 %index) {
 
 ; An address with an index and a displacement (order 1).
 define void @f2(i64 %addr, i64 %index) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -28,7 +28,7 @@ define void @f2(i64 %addr, i64 %index) {
 
 ; An address with an index and a displacement (order 2).
 define void @f3(i64 %addr, i64 %index) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, 100
@@ -40,7 +40,7 @@ define void @f3(i64 %addr, i64 %index) {
 
 ; An address with an index and a subtracted displacement (order 1).
 define void @f4(i64 %addr, i64 %index) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -52,7 +52,7 @@ define void @f4(i64 %addr, i64 %index) {
 
 ; An address with an index and a subtracted displacement (order 2).
 define void @f5(i64 %addr, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = sub i64 %addr, 100
@@ -64,7 +64,7 @@ define void @f5(i64 %addr, i64 %index) {
 
 ; An address with an index and a displacement added using OR.
 define void @f6(i64 %addr, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
 ; CHECK: lb %r0, 6(%r3,[[BASE]])
 ; CHECK: br %r14
@@ -78,7 +78,7 @@ define void @f6(i64 %addr, i64 %index) {
 
 ; Like f6, but without the masking.  This OR doesn't count as a displacement.
 define void @f7(i64 %addr, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oill %r2, 6
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
@@ -92,7 +92,7 @@ define void @f7(i64 %addr, i64 %index) {
 ; Like f6, but with the OR applied after the index.  We don't know anything
 ; about the alignment of %add here.
 define void @f8(i64 %addr, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
 ; CHECK: agr [[BASE]], %r3
 ; CHECK: oill [[BASE]], 6
diff --git a/test/CodeGen/SystemZ/addr-02.ll b/test/CodeGen/SystemZ/addr-02.ll
index 6e5c92f3a1a..66a798679b9 100644
--- a/test/CodeGen/SystemZ/addr-02.ll
+++ b/test/CodeGen/SystemZ/addr-02.ll
@@ -6,7 +6,7 @@
 
 ; A simple index address.
 define void @f1(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
   %add = add i64 %addr, %index
@@ -18,7 +18,7 @@ define void @f1(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a displacement (order 1).
 define void @f2(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -31,7 +31,7 @@ define void @f2(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a displacement (order 2).
 define void @f3(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, 100
@@ -44,7 +44,7 @@ define void @f3(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a subtracted displacement (order 1).
 define void @f4(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -57,7 +57,7 @@ define void @f4(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a subtracted displacement (order 2).
 define void @f5(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = sub i64 %addr, 100
@@ -70,7 +70,7 @@ define void @f5(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a displacement added using OR.
 define void @f6(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
 ; CHECK: lb %r0, 6(%r3,[[BASE]])
 ; CHECK: br %r14
@@ -85,7 +85,7 @@ define void @f6(i64 %addr, i64 %index, i8 **%dst) {
 
 ; Like f6, but without the masking.  This OR doesn't count as a displacement.
 define void @f7(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oill %r2, 6
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define void @f7(i64 %addr, i64 %index, i8 **%dst) {
 ; Like f6, but with the OR applied after the index.  We don't know anything
 ; about the alignment of %add here.
 define void @f8(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
 ; CHECK: agr [[BASE]], %r3
 ; CHECK: oill [[BASE]], 6
diff --git a/test/CodeGen/SystemZ/addr-03.ll b/test/CodeGen/SystemZ/addr-03.ll
index dbdb9f15b4f..1146926a4c2 100644
--- a/test/CodeGen/SystemZ/addr-03.ll
+++ b/test/CodeGen/SystemZ/addr-03.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lb %r0, 0
 ; CHECK: br %r14
   %ptr = inttoptr i64 0 to i8 *
@@ -12,7 +12,7 @@ define void @f1() {
 }
 
 define void @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lb %r0, -524288
 ; CHECK: br %r14
   %ptr = inttoptr i64 -524288 to i8 *
@@ -21,7 +21,7 @@ define void @f2() {
 }
 
 define void @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: lb %r0, -524289
 ; CHECK: br %r14
   %ptr = inttoptr i64 -524289 to i8 *
@@ -30,7 +30,7 @@ define void @f3() {
 }
 
 define void @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r0, 524287
 ; CHECK: br %r14
   %ptr = inttoptr i64 524287 to i8 *
@@ -39,7 +39,7 @@ define void @f4() {
 }
 
 define void @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: lb %r0, 524288
 ; CHECK: br %r14
   %ptr = inttoptr i64 524288 to i8 *
diff --git a/test/CodeGen/SystemZ/alloca-01.ll b/test/CodeGen/SystemZ/alloca-01.ll
index df14e27f1ea..2cd9a3a2420 100644
--- a/test/CodeGen/SystemZ/alloca-01.ll
+++ b/test/CodeGen/SystemZ/alloca-01.ll
@@ -21,34 +21,34 @@ define i64 @f1(i64 %length, i64 %index) {
 ;    risbg %r1, %r1, 0, 188, 0
 ;    lgr %r15, %r1
 ;
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
 ; CHECK-DAG: risbg [[REG2:%r[0-5]]], [[REG1]], 0, 188, 0
 ; CHECK-DAG: lgr [[REG3:%r[0-5]]], %r15
 ; CHECK: sgr [[REG3]], [[REG2]]
 ; CHECK: lgr %r15, [[REG3]]
 ;
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
 ; CHECK-A: lgr %r15, %r1
 ; CHECK-A: la %r2, 176(%r1)
 ;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
 ; CHECK-B: lgr %r15, %r1
 ; CHECK-B: la %r3, 177(%r1)
 ;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
 ; CHECK-C: lgr %r15, %r1
 ; CHECK-C: la %r4, 4095({{%r3,%r1|%r1,%r3}})
 ;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
 ; CHECK-D: lgr %r15, %r1
 ; CHECK-D: lay %r5, 4096({{%r3,%r1|%r1,%r3}})
 ;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
 ; CHECK-E: lgr %r15, %r1
 ; CHECK-E: lay %r6, 4271({{%r3,%r1|%r1,%r3}})
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: lgr %r11, %r15
 ; CHECK-FP: lmg %r6, %r15, 224(%r11)
   %a = alloca i8, i64 %length
diff --git a/test/CodeGen/SystemZ/alloca-02.ll b/test/CodeGen/SystemZ/alloca-02.ll
index 41c987a3f8a..b6ed7f7741d 100644
--- a/test/CodeGen/SystemZ/alloca-02.ll
+++ b/test/CodeGen/SystemZ/alloca-02.ll
@@ -9,27 +9,27 @@
 declare i64 @bar(i8 *%a)
 
 define i64 @f1(i64 %length, i64 %index) {
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
 ; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-A: la %r2, 160([[ADDR]])
 ; CHECK-A: mvi 0(%r2), 0
 ;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
 ; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-B: la %r2, 160([[ADDR]])
 ; CHECK-B: mvi 4095(%r2), 1
 ;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
 ; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-C: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
 ; CHECK-C: mvi 0([[TMP]]), 2
 ;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
 ; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-D: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
 ; CHECK-D: mvi 4095([[TMP]]), 3
 ;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
 ; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
 ; CHECK-E: mviy 4096([[TMP]]), 4
diff --git a/test/CodeGen/SystemZ/and-01.ll b/test/CodeGen/SystemZ/and-01.ll
index 0da13f9dd7c..f89314809f6 100644
--- a/test/CodeGen/SystemZ/and-01.ll
+++ b/test/CodeGen/SystemZ/and-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check NR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: nr %r2, %r3
 ; CHECK: br %r14
   %and = and i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the N range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned N range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: n %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use NY instead of N.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ny %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned NY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ny %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned NY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ny %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the NY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ny %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that N allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: n %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that NY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: ny %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that ANDs of spilled values can use N rather than NR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: n %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/and-02.ll b/test/CodeGen/SystemZ/and-02.ll
index 152c1b84fbc..0f39e185150 100644
--- a/test/CodeGen/SystemZ/and-02.ll
+++ b/test/CodeGen/SystemZ/and-02.ll
@@ -4,7 +4,7 @@
 
 ; ANDs with 1 should use RISBG
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: risbg %r2, %r2, 63, 191, 0
 ; CHECK: br %r14
   %and = and i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; ...same for 2.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: risbg %r2, %r2, 62, 190, 0
 ; CHECK: br %r14
   %and = and i32 %a, 2
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; ...and 3.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg %r2, %r2, 62, 191, 0
 ; CHECK: br %r14
   %and = and i32 %a, 3
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; ...and 4.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 61, 189, 0
 ; CHECK: br %r14
   %and = and i32 %a, 4
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a) {
 
 ; Check the lowest useful NILF value.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilf %r2, 5
 ; CHECK: br %r14
   %and = and i32 %a, 5
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the highest 16-bit constant that must be handled by NILF.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilf %r2, 65533
 ; CHECK: br %r14
   %and = and i32 %a, 65533
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a) {
 
 ; ANDs of 0xffff are zero extensions from i16.
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llhr %r2, %r2
 ; CHECK: br %r14
   %and = and i32 %a, 65535
@@ -67,7 +67,7 @@ define i32 @f7(i32 %a) {
 
 ; Check the next value up, which can use RISBG.
 define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: risbg %r2, %r2, 47, 175, 0
 ; CHECK: br %r14
   %and = and i32 %a, 65536
@@ -76,7 +76,7 @@ define i32 @f8(i32 %a) {
 
 ; Check the next value up, which must again use NILF.
 define i32 @f9(i32 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: nilf %r2, 65537
 ; CHECK: br %r14
   %and = and i32 %a, 65537
@@ -85,7 +85,7 @@ define i32 @f9(i32 %a) {
 
 ; This value is in range of NILH, but we use RISBG instead.
 define i32 @f10(i32 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: risbg %r2, %r2, 47, 191, 0
 ; CHECK: br %r14
   %and = and i32 %a, 131071
@@ -94,7 +94,7 @@ define i32 @f10(i32 %a) {
 
 ; Check the lowest useful NILH value.
 define i32 @f11(i32 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: nilh %r2, 2
 ; CHECK: br %r14
   %and = and i32 %a, 196607
@@ -103,7 +103,7 @@ define i32 @f11(i32 %a) {
 
 ; Check the highest useful NILH value.
 define i32 @f12(i32 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: nilh %r2, 65530
 ; CHECK: br %r14
   %and = and i32 %a, -327681
@@ -112,7 +112,7 @@ define i32 @f12(i32 %a) {
 
 ; Check the equivalent of NILH of 65531, which can use RISBG.
 define i32 @f13(i32 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: risbg %r2, %r2, 46, 172, 0
 ; CHECK: br %r14
   %and = and i32 %a, -262145
@@ -121,7 +121,7 @@ define i32 @f13(i32 %a) {
 
 ; ...same for 65532.
 define i32 @f14(i32 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: risbg %r2, %r2, 48, 173, 0
 ; CHECK: br %r14
   %and = and i32 %a, -196609
@@ -130,7 +130,7 @@ define i32 @f14(i32 %a) {
 
 ; ...and 65533.
 define i32 @f15(i32 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: risbg %r2, %r2, 47, 173, 0
 ; CHECK: br %r14
   %and = and i32 %a, -131073
@@ -139,7 +139,7 @@ define i32 @f15(i32 %a) {
 
 ; Check the highest useful NILF value.
 define i32 @f16(i32 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: nilf %r2, 4294901758
 ; CHECK: br %r14
   %and = and i32 %a, -65538
@@ -149,7 +149,7 @@ define i32 @f16(i32 %a) {
 ; Check the next value up, which is the equivalent of an NILH of 65534.
 ; We use RISBG instead.
 define i32 @f17(i32 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: risbg %r2, %r2, 48, 174, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65537
@@ -158,7 +158,7 @@ define i32 @f17(i32 %a) {
 
 ; Check the next value up, which can also use RISBG.
 define i32 @f18(i32 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: risbg %r2, %r2, 32, 175, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65536
@@ -167,7 +167,7 @@ define i32 @f18(i32 %a) {
 
 ; ...and again.
 define i32 @f19(i32 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: risbg %r2, %r2, 63, 175, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65535
@@ -176,7 +176,7 @@ define i32 @f19(i32 %a) {
 
 ; Check the next value up again, which is the lowest useful NILL value.
 define i32 @f20(i32 %a) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: nill %r2, 2
 ; CHECK: br %r14
   %and = and i32 %a, -65534
@@ -185,7 +185,7 @@ define i32 @f20(i32 %a) {
 
 ; Check the highest useful NILL value.
 define i32 @f21(i32 %a) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: nill %r2, 65530
 ; CHECK: br %r14
   %and = and i32 %a, -6
@@ -194,7 +194,7 @@ define i32 @f21(i32 %a) {
 
 ; Check the next value up, which can use RISBG.
 define i32 @f22(i32 %a) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: risbg %r2, %r2, 62, 188, 0
 ; CHECK: br %r14
   %and = and i32 %a, -5
@@ -203,7 +203,7 @@ define i32 @f22(i32 %a) {
 
 ; ...and again.
 define i32 @f23(i32 %a) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: risbg %r2, %r2, 32, 189, 0
 ; CHECK: br %r14
   %and = and i32 %a, -4
@@ -212,7 +212,7 @@ define i32 @f23(i32 %a) {
 
 ; ...and again.
 define i32 @f24(i32 %a) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: risbg %r2, %r2, 63, 189, 0
 ; CHECK: br %r14
   %and = and i32 %a, -3
@@ -221,7 +221,7 @@ define i32 @f24(i32 %a) {
 
 ; Check the last useful mask.
 define i32 @f25(i32 %a) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK: risbg %r2, %r2, 32, 190, 0
 ; CHECK: br %r14
   %and = and i32 %a, -2
diff --git a/test/CodeGen/SystemZ/and-03.ll b/test/CodeGen/SystemZ/and-03.ll
index 172098befb9..ca262cfb459 100644
--- a/test/CodeGen/SystemZ/and-03.ll
+++ b/test/CodeGen/SystemZ/and-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check NGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ngr %r2, %r3
 ; CHECK: br %r14
   %and = and i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check NG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned NG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ng %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned NG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ng %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the NG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ng %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that NG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ng %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that ANDs of spilled values can use NG rather than NGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ng %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/and-04.ll b/test/CodeGen/SystemZ/and-04.ll
index e94def69159..9c2f4a65d9f 100644
--- a/test/CodeGen/SystemZ/and-04.ll
+++ b/test/CodeGen/SystemZ/and-04.ll
@@ -4,7 +4,7 @@
 
 ; Use RISBG for a single bit.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: risbg %r2, %r2, 63, 191, 0
 ; CHECK: br %r14
   %and = and i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Likewise 0xfffe.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: risbg %r2, %r2, 48, 190, 0
 ; CHECK: br %r14
   %and = and i64 %a, 65534
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; ...but 0xffff is a 16-bit zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llghr %r2, %r2
 ; CHECK: br %r14
   %and = and i64 %a, 65535
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the next value up, which can again use RISBG.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 47, 175, 0
 ; CHECK: br %r14
   %and = and i64 %a, 65536
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
 
 ; Check 0xfffffffe, which can also use RISBG.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: risbg %r2, %r2, 32, 190, 0
 ; CHECK: br %r14
   %and = and i64 %a, 4294967294
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the next value up, which is a 32-bit zero extension.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: llgfr %r2, %r2
 ; CHECK: br %r14
   %and = and i64 %a, 4294967295
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the lowest useful NIHF value (0x00000002_ffffffff).
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nihf %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, 12884901887
@@ -67,7 +67,7 @@ define i64 @f7(i64 %a) {
 
 ; Check the lowest useful NIHH value (0x0002ffff_ffffffff).
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nihh %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, 844424930131967
@@ -76,7 +76,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the highest useful NIHH value (0xfffaffff_ffffffff).
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: nihh %r2, 65530
 ; CHECK: br %r14
   %and = and i64 %a, -1407374883553281
@@ -85,7 +85,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the highest useful NIHF value (0xfffefffe_ffffffff).
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: nihf %r2, 4294901758
 ; CHECK: br %r14
   %and = and i64 %a, -281479271677953
@@ -94,7 +94,7 @@ define i64 @f10(i64 %a) {
 
 ; Check the lowest useful NIHL value (0xffff0002_ffffffff).
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: nihl %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, -281462091808769
@@ -103,7 +103,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the highest useful NIHL value (0xfffffffa_ffffffff).
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: nihl %r2, 65530
 ; CHECK: br %r14
   %and = and i64 %a, -21474836481
@@ -112,7 +112,7 @@ define i64 @f12(i64 %a) {
 
 ; Check the lowest useful NILF range (0xffffffff_00000002).
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: nilf %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, -4294967294
@@ -121,7 +121,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the low end of the NILH range (0xffffffff_0002ffff).
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: nilh %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, -4294770689
@@ -130,7 +130,7 @@ define i64 @f14(i64 %a) {
 
 ; Check the next value up, which must use NILF.
 define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: nilf %r2, 196608
 ; CHECK: br %r14
   %and = and i64 %a, -4294770688
@@ -139,7 +139,7 @@ define i64 @f15(i64 %a) {
 
 ; Check the highest useful NILH value (0xffffffff_fffaffff).
 define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: nilh %r2, 65530
 ; CHECK: br %r14
   %and = and i64 %a, -327681
@@ -148,7 +148,7 @@ define i64 @f16(i64 %a) {
 
 ; Check the maximum useful NILF value (0xffffffff_fffefffe).
 define i64 @f17(i64 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: nilf %r2, 4294901758
 ; CHECK: br %r14
   %and = and i64 %a, -65538
@@ -157,7 +157,7 @@ define i64 @f17(i64 %a) {
 
 ; Check the lowest useful NILL value (0xffffffff_ffff0002).
 define i64 @f18(i64 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: nill %r2, 2
 ; CHECK: br %r14
   %and = and i64 %a, -65534
@@ -166,7 +166,7 @@ define i64 @f18(i64 %a) {
 
 ; Check the highest useful NILL value.
 define i64 @f19(i64 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: nill %r2, 65530
 ; CHECK: br %r14
   %and = and i64 %a, -6
diff --git a/test/CodeGen/SystemZ/and-05.ll b/test/CodeGen/SystemZ/and-05.ll
index 457391165d5..dafd9d5c51b 100644
--- a/test/CodeGen/SystemZ/and-05.ll
+++ b/test/CodeGen/SystemZ/and-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful constant, expressed as a signed integer.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ni 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a signed integer.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the lowest useful constant, expressed as an unsigned integer.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ni 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a unsigned integer.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check the high end of the NI range.
 define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ni 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
 
 ; Check the next byte up, which should use NIY instead of NI.
 define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: niy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
 
 ; Check the high end of the NIY range.
 define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: niy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: ni 0(%r2), 127
 ; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
 
 ; Check the high end of the negative NIY range.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: niy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
 
 ; Check the low end of the NIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: niy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -524289
 ; CHECK: ni 0(%r2), 127
 ; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
 
 ; Check that NI does not allow an index
 define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r2, %r3
 ; CHECK: ni 4095(%r2), 127
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
 
 ; Check that NIY does not allow an index
 define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agr %r2, %r3
 ; CHECK: niy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/and-06.ll b/test/CodeGen/SystemZ/and-06.ll
index bbb5e7b7b9d..f796618dd4f 100644
--- a/test/CodeGen/SystemZ/and-06.ll
+++ b/test/CodeGen/SystemZ/and-06.ll
@@ -5,7 +5,7 @@
 
 ; Zero extension to 32 bits, negative constant.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
 
 ; Zero extension to 64 bits, negative constant.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
 
 ; Zero extension to 32 bits, positive constant.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
 
 ; Zero extension to 64 bits, positive constant.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
 
 ; Sign extension to 32 bits, negative constant.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
 
 ; Sign extension to 64 bits, negative constant.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
 
 ; Sign extension to 32 bits, positive constant.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
 
 ; Sign extension to 64 bits, positive constant.
 define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/args-01.ll b/test/CodeGen/SystemZ/args-01.ll
index 50e80031f0e..3105503eda5 100644
--- a/test/CodeGen/SystemZ/args-01.ll
+++ b/test/CodeGen/SystemZ/args-01.ll
@@ -20,7 +20,7 @@ declare void @bar(i8, i16, i32, i64, float, double, fp128, i64,
 ; The order of the CHECK-STACK stores doesn't matter.  It would be OK to reorder
 ; them in response to future code changes.
 define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
 ; CHECK-INT-DAG: lhi %r2, 1
 ; CHECK-INT-DAG: lhi %r3, 2
 ; CHECK-INT-DAG: lhi %r4, 3
@@ -28,31 +28,31 @@ define void @foo() {
 ; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
 ; CHECK-INT: brasl %r14, bar@PLT
 ;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
 ; CHECK-FLOAT: lzer %f0
 ; CHECK-FLOAT: lcebr %f4, %f0
 ; CHECK-FLOAT: brasl %r14, bar@PLT
 ;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
 ; CHECK-DOUBLE: lzdr %f2
 ; CHECK-DOUBLE: lcdbr %f6, %f2
 ; CHECK-DOUBLE: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
 ; CHECK-FP128-1: aghi %r15, -256
 ; CHECK-FP128-1: lzxr %f0
 ; CHECK-FP128-1-DAG: std %f0, 224(%r15)
 ; CHECK-FP128-1-DAG: std %f2, 232(%r15)
 ; CHECK-FP128-1: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
 ; CHECK-FP128-2: aghi %r15, -256
 ; CHECK-FP128-2: lzxr %f0
 ; CHECK-FP128-2-DAG: std %f0, 240(%r15)
 ; CHECK-FP128-2-DAG: std %f2, 248(%r15)
 ; CHECK-FP128-2: brasl %r14, bar@PLT
 ;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
 ; CHECK-STACK: aghi %r15, -256
 ; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
 ; CHECK-STACK: stg [[REGISTER]], 216(%r15)
diff --git a/test/CodeGen/SystemZ/args-02.ll b/test/CodeGen/SystemZ/args-02.ll
index b964d516fa1..8686df88e67 100644
--- a/test/CodeGen/SystemZ/args-02.ll
+++ b/test/CodeGen/SystemZ/args-02.ll
@@ -21,7 +21,7 @@ declare void @bar(i8 signext, i16 signext, i32 signext, i64, float, double,
 ; The order of the CHECK-STACK stores doesn't matter.  It would be OK to reorder
 ; them in response to future code changes.
 define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
 ; CHECK-INT-DAG: lghi %r2, -1
 ; CHECK-INT-DAG: lghi %r3, -2
 ; CHECK-INT-DAG: lghi %r4, -3
@@ -29,31 +29,31 @@ define void @foo() {
 ; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
 ; CHECK-INT: brasl %r14, bar@PLT
 ;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
 ; CHECK-FLOAT: lzer %f0
 ; CHECK-FLOAT: lcebr %f4, %f0
 ; CHECK-FLOAT: brasl %r14, bar@PLT
 ;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
 ; CHECK-DOUBLE: lzdr %f2
 ; CHECK-DOUBLE: lcdbr %f6, %f2
 ; CHECK-DOUBLE: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
 ; CHECK-FP128-1: aghi %r15, -256
 ; CHECK-FP128-1: lzxr %f0
 ; CHECK-FP128-1-DAG: std %f0, 224(%r15)
 ; CHECK-FP128-1-DAG: std %f2, 232(%r15)
 ; CHECK-FP128-1: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
 ; CHECK-FP128-2: aghi %r15, -256
 ; CHECK-FP128-2: lzxr %f0
 ; CHECK-FP128-2-DAG: std %f0, 240(%r15)
 ; CHECK-FP128-2-DAG: std %f2, 248(%r15)
 ; CHECK-FP128-2: brasl %r14, bar@PLT
 ;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
 ; CHECK-STACK: aghi %r15, -256
 ; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
 ; CHECK-STACK: stg [[REGISTER]], 216(%r15)
diff --git a/test/CodeGen/SystemZ/args-03.ll b/test/CodeGen/SystemZ/args-03.ll
index 28c33388dc3..d7d3ea105df 100644
--- a/test/CodeGen/SystemZ/args-03.ll
+++ b/test/CodeGen/SystemZ/args-03.ll
@@ -21,7 +21,7 @@ declare void @bar(i8 zeroext, i16 zeroext, i32 zeroext, i64, float, double,
 ; The order of the CHECK-STACK stores doesn't matter.  It would be OK to reorder
 ; them in response to future code changes.
 define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
 ; CHECK-INT-DAG: lghi %r2, 255
 ; CHECK-INT-DAG: llill %r3, 65534
 ; CHECK-INT-DAG: llilf %r4, 4294967293
@@ -29,31 +29,31 @@ define void @foo() {
 ; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
 ; CHECK-INT: brasl %r14, bar@PLT
 ;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
 ; CHECK-FLOAT: lzer %f0
 ; CHECK-FLOAT: lcebr %f4, %f0
 ; CHECK-FLOAT: brasl %r14, bar@PLT
 ;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
 ; CHECK-DOUBLE: lzdr %f2
 ; CHECK-DOUBLE: lcdbr %f6, %f2
 ; CHECK-DOUBLE: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
 ; CHECK-FP128-1: aghi %r15, -256
 ; CHECK-FP128-1: lzxr %f0
 ; CHECK-FP128-1-DAG: std %f0, 224(%r15)
 ; CHECK-FP128-1-DAG: std %f2, 232(%r15)
 ; CHECK-FP128-1: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
 ; CHECK-FP128-2: aghi %r15, -256
 ; CHECK-FP128-2: lzxr %f0
 ; CHECK-FP128-2-DAG: std %f0, 240(%r15)
 ; CHECK-FP128-2-DAG: std %f2, 248(%r15)
 ; CHECK-FP128-2: brasl %r14, bar@PLT
 ;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
 ; CHECK-STACK: aghi %r15, -256
 ; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
 ; CHECK-STACK: stg [[REGISTER]], 216(%r15)
diff --git a/test/CodeGen/SystemZ/args-04.ll b/test/CodeGen/SystemZ/args-04.ll
index 8340494ff4d..1178bb4dafd 100644
--- a/test/CodeGen/SystemZ/args-04.ll
+++ b/test/CodeGen/SystemZ/args-04.ll
@@ -5,7 +5,7 @@
 
 ; Do some arithmetic so that we can see the register being used.
 define i8 @f1(i8 %r2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ahi %r2, 1
 ; CHECK: br %r14
   %y = add i8 %r2, 1
@@ -13,21 +13,21 @@ define i8 @f1(i8 %r2) {
 }
 
 define i16 @f2(i8 %r2, i16 %r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: {{lr|lgr}} %r2, %r3
 ; CHECK: br %r14
   ret i16 %r3
 }
 
 define i32 @f3(i8 %r2, i16 %r3, i32 %r4) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: {{lr|lgr}} %r2, %r4
 ; CHECK: br %r14
   ret i32 %r4
 }
 
 define i64 @f4(i8 %r2, i16 %r3, i32 %r4, i64 %r5) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: {{lr|lgr}} %r2, %r5
 ; CHECK: br %r14
   ret i64 %r5
@@ -35,7 +35,7 @@ define i64 @f4(i8 %r2, i16 %r3, i32 %r4, i64 %r5) {
 
 ; Do some arithmetic so that we can see the register being used.
 define float @f5(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aebr %f0, %f0
 ; CHECK: br %r14
   %y = fadd float %f0, %f0
@@ -43,7 +43,7 @@ define float @f5(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0) {
 }
 
 define double @f6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   ret double %f2
@@ -54,7 +54,7 @@ define double @f6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2) {
 ; be copied.
 define void @f7(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                 fp128 %r6) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ld %f0, 0(%r6)
 ; CHECK: ld %f2, 8(%r6)
 ; CHECK: axbr %f0, %f0
@@ -68,7 +68,7 @@ define void @f7(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define i64 @f8(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                fp128 %r6, i64 %s1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lg %r2, 160(%r15)
 ; CHECK: br %r14
   ret i64 %s1
@@ -76,7 +76,7 @@ define i64 @f8(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define float @f9(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                  fp128 %r6, i64 %s1, float %f4) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ler %f0, %f4
 ; CHECK: br %r14
   ret float %f4
@@ -84,7 +84,7 @@ define float @f9(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define double @f10(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                    fp128 %r6, i64 %s1, float %f4, double %f6) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ldr %f0, %f6
 ; CHECK: br %r14
   ret double %f6
@@ -92,7 +92,7 @@ define double @f10(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define i64 @f11(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                 fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lg %r2, 168(%r15)
 ; CHECK: br %r14
   ret i64 %s2
@@ -102,7 +102,7 @@ define i64 @f11(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 define float @f12(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                   fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
                   float %s3) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: le %f0, 180(%r15)
 ; CHECK: br %r14
   ret float %s3
@@ -112,7 +112,7 @@ define float @f12(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 define void @f13(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                  fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
                  float %s3, fp128 %s4) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: lg [[REGISTER:%r[1-5]+]], 184(%r15)
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
diff --git a/test/CodeGen/SystemZ/args-05.ll b/test/CodeGen/SystemZ/args-05.ll
index 9fa193a68e5..8a6ef4c54ff 100644
--- a/test/CodeGen/SystemZ/args-05.ll
+++ b/test/CodeGen/SystemZ/args-05.ll
@@ -4,7 +4,7 @@
 
 ; Zero extension of something that is already zero-extended.
 define void @f1(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: stg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define void @f1(i32 zeroext %r2, i64 *%r3) {
 
 ; Sign extension of something that is already sign-extended.
 define void @f2(i32 signext %r2, i64 *%r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: stg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define void @f2(i32 signext %r2, i64 *%r3) {
 
 ; Sign extension of something that is already zero-extended.
 define void @f3(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgfr [[REGISTER:%r[0-5]+]], %r2
 ; CHECK: stg [[REGISTER]], 0(%r3)
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define void @f3(i32 zeroext %r2, i64 *%r3) {
 
 ; Zero extension of something that is already sign-extended.
 define void @f4(i32 signext %r2, i64 *%r3) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgfr [[REGISTER:%r[0-5]+]], %r2
 ; CHECK: stg [[REGISTER]], 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/args-06.ll b/test/CodeGen/SystemZ/args-06.ll
index b2f8bee2c6b..a89fe9b7c23 100644
--- a/test/CodeGen/SystemZ/args-06.ll
+++ b/test/CodeGen/SystemZ/args-06.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
@@ -22,7 +22,7 @@ define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
 }
 
 define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
@@ -40,7 +40,7 @@ define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) {
 }
 
 define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
@@ -58,7 +58,7 @@ define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
 }
 
 define i64 @f4(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agr %r2, %r3
 ; CHECK: agr %r2, %r4
 ; CHECK: agr %r2, %r5
diff --git a/test/CodeGen/SystemZ/asm-01.ll b/test/CodeGen/SystemZ/asm-01.ll
index 016d04c614c..801378c5fcb 100644
--- a/test/CodeGen/SystemZ/asm-01.ll
+++ b/test/CodeGen/SystemZ/asm-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the lowest range.
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
@@ -15,7 +15,7 @@ define void @f1(i64 %base) {
 
 ; Check the next lowest byte.
 define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r2, -1
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i64 %base) {
 
 ; Check the highest range.
 define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah 4095(%r2)
 ; CHECK: br %r14
   %add = add i64 %base, 4095
@@ -38,7 +38,7 @@ define void @f3(i64 %base) {
 
 ; Check the next highest byte.
 define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f4(i64 %base) {
 
 ; Check that indices aren't allowed
 define void @f5(i64 %base, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agr %r2, %r3
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-02.ll b/test/CodeGen/SystemZ/asm-02.ll
index 12d8bec161c..ad1e35bb362 100644
--- a/test/CodeGen/SystemZ/asm-02.ll
+++ b/test/CodeGen/SystemZ/asm-02.ll
@@ -5,7 +5,7 @@
 
 ; Check the lowest range.
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
@@ -15,7 +15,7 @@ define void @f1(i64 %base) {
 
 ; Check the next lowest byte.
 define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r2, -1
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i64 %base) {
 
 ; Check the highest range.
 define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah 4095(%r2)
 ; CHECK: br %r14
   %add = add i64 %base, 4095
@@ -38,7 +38,7 @@ define void @f3(i64 %base) {
 
 ; Check the next highest byte.
 define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-03.ll b/test/CodeGen/SystemZ/asm-03.ll
index a6f3f2a5cb6..fa3e1a7d01d 100644
--- a/test/CodeGen/SystemZ/asm-03.ll
+++ b/test/CodeGen/SystemZ/asm-03.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
diff --git a/test/CodeGen/SystemZ/asm-04.ll b/test/CodeGen/SystemZ/asm-04.ll
index 0560949eb06..af7ea9fdef9 100644
--- a/test/CodeGen/SystemZ/asm-04.ll
+++ b/test/CodeGen/SystemZ/asm-04.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
diff --git a/test/CodeGen/SystemZ/asm-05.ll b/test/CodeGen/SystemZ/asm-05.ll
index dae90b09eaf..e18cb757b14 100644
--- a/test/CodeGen/SystemZ/asm-05.ll
+++ b/test/CodeGen/SystemZ/asm-05.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
diff --git a/test/CodeGen/SystemZ/asm-06.ll b/test/CodeGen/SystemZ/asm-06.ll
index c0e24a36648..f9848a2df6f 100644
--- a/test/CodeGen/SystemZ/asm-06.ll
+++ b/test/CodeGen/SystemZ/asm-06.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r1, 1
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r1, 2
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r1, 3
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lghi %r1, 4
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-07.ll b/test/CodeGen/SystemZ/asm-07.ll
index e07286d9a4d..bf63150cd81 100644
--- a/test/CodeGen/SystemZ/asm-07.ll
+++ b/test/CodeGen/SystemZ/asm-07.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r0, 1
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 2
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r0, 3
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lghi %r0, 4
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-08.ll b/test/CodeGen/SystemZ/asm-08.ll
index 15abc4d0d2e..166233752db 100644
--- a/test/CodeGen/SystemZ/asm-08.ll
+++ b/test/CodeGen/SystemZ/asm-08.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r0, 1
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 2
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r0, 3
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lghi %r0, 4
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-09.ll b/test/CodeGen/SystemZ/asm-09.ll
index 1541170924b..5cd7efb9400 100644
--- a/test/CodeGen/SystemZ/asm-09.ll
+++ b/test/CodeGen/SystemZ/asm-09.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i32 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r0, 100
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
@@ -14,7 +14,7 @@ define void @f1(i32 *%dst) {
 }
 
 define void @f2(i32 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 101
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
@@ -25,7 +25,7 @@ define void @f2(i32 *%dst) {
 }
 
 define void @f3(i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r0, 102
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
@@ -37,7 +37,7 @@ define void @f3(i32 *%dst) {
 
 ; FIXME: this uses "lhi %r0, 103", but should use "lghi %r0, 103".
 define void @f4(i32 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +47,7 @@ define void @f4(i32 *%dst) {
 }
 
 define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lghi %r2, 104
 ; CHECK: blah %r2
 ; CHECK: br %r14
@@ -56,7 +56,7 @@ define i64 @f5() {
 }
 
 define i64 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lghi %r2, 105
 ; CHECK: blah %r2
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define i64 @f6() {
 }
 
 define i64 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lghi %r2, 106
 ; CHECK: blah %r2
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define i64 @f7() {
 }
 
 define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lghi %r2, 107
 ; CHECK: blah %r2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-10.ll b/test/CodeGen/SystemZ/asm-10.ll
index 676c2028b05..0eccc197218 100644
--- a/test/CodeGen/SystemZ/asm-10.ll
+++ b/test/CodeGen/SystemZ/asm-10.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lzer %f1
 ; CHECK: blah %f0 %f1
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define float @f1() {
 }
 
 define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lzdr %f1
 ; CHECK: blah %f0 %f1
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define double @f2() {
 }
 
 define double @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzxr %f1
 ; CHECK: blah %f0 %f1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-11.ll b/test/CodeGen/SystemZ/asm-11.ll
index 9bd8d7c33f0..8aeb784134a 100644
--- a/test/CodeGen/SystemZ/asm-11.ll
+++ b/test/CodeGen/SystemZ/asm-11.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 0
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 0)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 255
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 255)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lhi [[REG:%r[0-5]]], 256
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-12.ll b/test/CodeGen/SystemZ/asm-12.ll
index dd920f11fde..feecbacf09e 100644
--- a/test/CodeGen/SystemZ/asm-12.ll
+++ b/test/CodeGen/SystemZ/asm-12.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 0
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 0)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 4095
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 4095)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lhi [[REG:%r[0-5]]], 4096
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-13.ll b/test/CodeGen/SystemZ/asm-13.ll
index af3fdb36153..b88170079ec 100644
--- a/test/CodeGen/SystemZ/asm-13.ll
+++ b/test/CodeGen/SystemZ/asm-13.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 4294934527
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 -32768
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 -32768)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 32767
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 32767)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llill [[REG:%r[0-5]]], 32768
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-14.ll b/test/CodeGen/SystemZ/asm-14.ll
index b6b28d6b32f..bcd8b1ebc3d 100644
--- a/test/CodeGen/SystemZ/asm-14.ll
+++ b/test/CodeGen/SystemZ/asm-14.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 4294443007
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 -524288
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 -524288)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 524287
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 524287)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llilh [[REG:%r[0-5]]], 8
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-15.ll b/test/CodeGen/SystemZ/asm-15.ll
index 4d0e2b4c3be..886ee0e897d 100644
--- a/test/CodeGen/SystemZ/asm-15.ll
+++ b/test/CodeGen/SystemZ/asm-15.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 2147483646
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 2147483647
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test 1 above the valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llilh [[REG:%r[0-5]]], 32768
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-16.ll b/test/CodeGen/SystemZ/asm-16.ll
index 4d0e2b4c3be..886ee0e897d 100644
--- a/test/CodeGen/SystemZ/asm-16.ll
+++ b/test/CodeGen/SystemZ/asm-16.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 2147483646
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 2147483647
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test 1 above the valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llilh [[REG:%r[0-5]]], 32768
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-17.ll b/test/CodeGen/SystemZ/asm-17.ll
index f2fbba6d4c5..33234fcae1c 100644
--- a/test/CodeGen/SystemZ/asm-17.ll
+++ b/test/CodeGen/SystemZ/asm-17.ll
@@ -4,7 +4,7 @@
 
 ; Test i32 GPRs.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r4, 1
 ; CHECK: blah %r4
 ; CHECK: lr %r2, %r4
@@ -15,7 +15,7 @@ define i32 @f1() {
 
 ; Test i64 GPRs.
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lghi %r4, 1
 ; CHECK: blah %r4
 ; CHECK: lgr %r2, %r4
@@ -26,7 +26,7 @@ define i64 @f2() {
 
 ; Test i32 FPRs.
 define float @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzer %f4
 ; CHECK: blah %f4
 ; CHECK: ler %f0, %f4
@@ -37,7 +37,7 @@ define float @f3() {
 
 ; Test i64 FPRs.
 define double @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lzdr %f4
 ; CHECK: blah %f4
 ; CHECK: ldr %f0, %f4
@@ -48,7 +48,7 @@ define double @f4() {
 
 ; Test i128 FPRs.
 define void @f5(fp128 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lzxr %f4
 ; CHECK: blah %f4
 ; CHECK-DAG: std %f4, 0(%r2)
@@ -61,7 +61,7 @@ define void @f5(fp128 *%dest) {
 
 ; Test clobbers of GPRs and CC.
 define i32 @f6(i32 %in) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lr [[REG:%r[01345]]], %r2
 ; CHECK: blah
 ; CHECK: lr %r2, [[REG]]
@@ -72,7 +72,7 @@ define i32 @f6(i32 %in) {
 
 ; Test clobbers of FPRs and CC.
 define float @f7(float %in) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ler [[REG:%f[1-7]]], %f0
 ; CHECK: blah
 ; CHECK: ler %f0, [[REG]]
diff --git a/test/CodeGen/SystemZ/atomic-load-01.ll b/test/CodeGen/SystemZ/atomic-load-01.ll
index 3e86bcf78ae..a5bc8833e78 100644
--- a/test/CodeGen/SystemZ/atomic-load-01.ll
+++ b/test/CodeGen/SystemZ/atomic-load-01.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; The CS-based sequence is probably far too conservative.
 define i8 @f1(i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   %val = load atomic i8 *%src seq_cst, align 1
diff --git a/test/CodeGen/SystemZ/atomic-load-02.ll b/test/CodeGen/SystemZ/atomic-load-02.ll
index d6168cedb8a..2c9bbdb488a 100644
--- a/test/CodeGen/SystemZ/atomic-load-02.ll
+++ b/test/CodeGen/SystemZ/atomic-load-02.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; The CS-based sequence is probably far too conservative.
 define i16 @f1(i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   %val = load atomic i16 *%src seq_cst, align 2
diff --git a/test/CodeGen/SystemZ/atomic-load-03.ll b/test/CodeGen/SystemZ/atomic-load-03.ll
index fcf0cf3d5a9..1fb41f5e39a 100644
--- a/test/CodeGen/SystemZ/atomic-load-03.ll
+++ b/test/CodeGen/SystemZ/atomic-load-03.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; Using CS is probably too conservative.
 define i32 @f1(i32 %dummy, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r2, 0
 ; CHECK: cs %r2, %r2, 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomic-load-04.ll b/test/CodeGen/SystemZ/atomic-load-04.ll
index 9593d35fef0..92cac406e20 100644
--- a/test/CodeGen/SystemZ/atomic-load-04.ll
+++ b/test/CodeGen/SystemZ/atomic-load-04.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; Using CSG is probably too conservative.
 define i64 @f1(i64 %dummy, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghi %r2, 0
 ; CHECK: csg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomic-store-01.ll b/test/CodeGen/SystemZ/atomic-store-01.ll
index b316e5cd630..53ed24f623c 100644
--- a/test/CodeGen/SystemZ/atomic-store-01.ll
+++ b/test/CodeGen/SystemZ/atomic-store-01.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; The CS-based sequence is probably far too conservative.
 define void @f1(i8 %val, i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   store atomic i8 %val, i8 *%src seq_cst, align 1
diff --git a/test/CodeGen/SystemZ/atomic-store-02.ll b/test/CodeGen/SystemZ/atomic-store-02.ll
index c7617143188..42d6695b51d 100644
--- a/test/CodeGen/SystemZ/atomic-store-02.ll
+++ b/test/CodeGen/SystemZ/atomic-store-02.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; The CS-based sequence is probably far too conservative.
 define void @f1(i16 %val, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   store atomic i16 %val, i16 *%src seq_cst, align 2
diff --git a/test/CodeGen/SystemZ/atomic-store-03.ll b/test/CodeGen/SystemZ/atomic-store-03.ll
index cbf1e511d2b..0954f6f4783 100644
--- a/test/CodeGen/SystemZ/atomic-store-03.ll
+++ b/test/CodeGen/SystemZ/atomic-store-03.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; Using CS is probably too conservative.
 define void @f1(i32 %val, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r0, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r0, %r2, 0(%r3)
diff --git a/test/CodeGen/SystemZ/atomic-store-04.ll b/test/CodeGen/SystemZ/atomic-store-04.ll
index a2d83c5e5c3..d4182783b7d 100644
--- a/test/CodeGen/SystemZ/atomic-store-04.ll
+++ b/test/CodeGen/SystemZ/atomic-store-04.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; Using CS is probably too conservative.
 define void @f1(i64 %val, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r0, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r0, %r2, 0(%r3)
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-01.ll b/test/CodeGen/SystemZ/atomicrmw-add-01.ll
index 3074c548f92..2e1947fcf76 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check addition of -1.  We add 0xff000000 to the rotated word.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], -16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 -1 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check addition of 1.  We add 0x01000000 to the rotated word.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], 16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We add 0x7f000000 to the rotated word.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], 2130706432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check addition of a large unsigned value.  We add 0xfe000000 to the
 ; rotated word, expressed as a negative AFI operand.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], -33554432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 254 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-02.ll b/test/CodeGen/SystemZ/atomicrmw-add-02.ll
index 24c336b79a7..76f7c2ed6b6 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check addition of -1.  We add 0xffff0000 to the rotated word.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], -65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 -1 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check addition of 1.  We add 0x00010000 to the rotated word.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], 65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We add 0x7fff0000 to the rotated word.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], 2147418112
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check addition of a large unsigned value.  We add 0xfffe0000 to the
 ; rotated word, expressed as a negative AFI operand.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], -131072
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 65534 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-03.ll b/test/CodeGen/SystemZ/atomicrmw-add-03.ll
index e3190574eed..04813f9d8bc 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-03.ll
@@ -4,7 +4,7 @@
 
 ; Check addition of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check addition of 1, which can use AHI.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the AHI range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ahi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 32767 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use AFI.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 32768 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the AFI range.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 2147483647 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which gets treated as a negative operand.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 2147483648 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check addition of -1, which can use AHI.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahi %r0, -1
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 -1 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the AHI range.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ahi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 -32768 seq_cst
@@ -86,7 +86,7 @@ define i32 @f8(i32 %dummy, i32 *%src) {
 
 ; Check the next value down, which must use AFI instead.
 define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 -32769 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-04.ll b/test/CodeGen/SystemZ/atomicrmw-add-04.ll
index b2cbaca852d..f3814f20abe 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-04.ll
@@ -4,7 +4,7 @@
 
 ; Check addition of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check addition of 1, which can use AGHI.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGHI range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 32767 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use AGFI.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 32768 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGFI range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 2147483647 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register addition.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agr
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 2147483648 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check addition of -1, which can use AGHI.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: aghi %r0, -1
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -1 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGHI range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -32768 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use AGFI instead.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -32769 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGFI range.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -2147483648 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use a register addition.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agr
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -2147483649 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-01.ll b/test/CodeGen/SystemZ/atomicrmw-and-01.ll
index cd4104da83f..243cf1573ed 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-01.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: oilf %r3, 16777215
 ; CHECK-SHIFT2: rll
@@ -48,7 +48,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -61,7 +61,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -69,7 +69,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -77,13 +77,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check ANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfeffffff.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65279
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 -2 seq_cst
   ret i8 %res
@@ -91,13 +91,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check ANDs of 1.  We AND the rotated word with 0x01ffffff.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 511
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -105,13 +105,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -120,13 +120,13 @@ define i8 @f5(i8 *%src) {
 ; Check ANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfdffffff.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65023
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-02.ll b/test/CodeGen/SystemZ/atomicrmw-and-02.ll
index a19d18705e3..31247a335d9 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-02.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: oill %r3, 65535
 ; CHECK-SHIFT2: rll
@@ -48,7 +48,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -61,7 +61,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -69,7 +69,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -77,13 +77,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check ANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfffeffff.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65534
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 -2 seq_cst
   ret i16 %res
@@ -91,13 +91,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check ANDs of 1.  We AND the rotated word with 0x0001ffff.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 1
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -105,13 +105,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -120,13 +120,13 @@ define i16 @f5(i16 *%src) {
 ; Check ANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfffdffff.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65533
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-03.ll b/test/CodeGen/SystemZ/atomicrmw-and-03.ll
index 8449a7cacf7..dd02828ad83 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-03.ll
@@ -4,7 +4,7 @@
 
 ; Check ANDs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check ANDs of 1.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check ANDs of the low end of the NILH range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 65535 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use NILF.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilf %r0, 65536
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 65536 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILL value.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nill %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -2 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the NILL range.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nill %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -65536 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILH value, which is one less than the above.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nilh %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -65537 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -65538 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-04.ll b/test/CodeGen/SystemZ/atomicrmw-and-04.ll
index ade7617d967..6a9f81ac39b 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-04.ll
@@ -4,7 +4,7 @@
 
 ; Check ANDs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check ANDs of 1, which must be done using a register.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 1 seq_cst
@@ -27,7 +27,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHF range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 4294967296 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHH range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nihh %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 281474976710655 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 281474976710656 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILL value.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nill %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -2 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILL range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nill %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -65536 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILH value, which is one less than the above.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: nilh %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -65537 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -65538 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILH range.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: nilh %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -4294901761 seq_cst
@@ -113,7 +113,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILF range.
 define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: nilf %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -4294967296 seq_cst
@@ -122,7 +122,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHL value, which is one less than the above.
 define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: nihl %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -4294967297 seq_cst
@@ -131,7 +131,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHL range.
 define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: nihl %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -281470681743361 seq_cst
@@ -140,7 +140,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHH value, which is 1<<32 less than the above.
 define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: nihh %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -281474976710657 seq_cst
@@ -149,7 +149,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHF value, which is 1<<32 less than the above.
 define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: nihf %r0, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -281479271677953 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
index 9e1e7ff71a4..1a9db879396 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -28,7 +28,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -36,7 +36,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
@@ -49,7 +49,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check signed maximum.
 define i8 @f2(i8 *%src, i8 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -64,7 +64,7 @@ define i8 @f2(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -72,7 +72,7 @@ define i8 @f2(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
@@ -85,7 +85,7 @@ define i8 @f2(i8 *%src, i8 %b) {
 
 ; Check unsigned minimum.
 define i8 @f3(i8 *%src, i8 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -101,7 +101,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -109,7 +109,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -122,7 +122,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 
 ; Check unsigned maximum.
 define i8 @f4(i8 *%src, i8 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -138,7 +138,7 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -146,7 +146,7 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -160,15 +160,15 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; Check the lowest useful signed minimum value.  We need to load 0x81000000
 ; into the source register.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw min i8 *%src, i8 -127 seq_cst
   ret i8 %res
@@ -177,15 +177,15 @@ define i8 @f5(i8 *%src) {
 ; Check the highest useful signed maximum value.  We need to load 0x7e000000
 ; into the source register.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw max i8 *%src, i8 126 seq_cst
   ret i8 %res
@@ -194,15 +194,15 @@ define i8 @f6(i8 *%src) {
 ; Check the lowest useful unsigned minimum value.  We need to load 0x01000000
 ; into the source register.
 define i8 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 256
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umin i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -211,15 +211,15 @@ define i8 @f7(i8 *%src) {
 ; Check the highest useful unsigned maximum value.  We need to load 0xfe000000
 ; into the source register.
 define i8 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umax i8 *%src, i8 254 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
index 78c95df11f4..2f6d3eddc07 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -28,7 +28,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -36,7 +36,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
@@ -49,7 +49,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check signed maximum.
 define i16 @f2(i16 *%src, i16 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -64,7 +64,7 @@ define i16 @f2(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -72,7 +72,7 @@ define i16 @f2(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
@@ -85,7 +85,7 @@ define i16 @f2(i16 *%src, i16 %b) {
 
 ; Check unsigned minimum.
 define i16 @f3(i16 *%src, i16 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -101,7 +101,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -109,7 +109,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -122,7 +122,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 
 ; Check unsigned maximum.
 define i16 @f4(i16 *%src, i16 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -138,7 +138,7 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -146,7 +146,7 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -160,15 +160,15 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; Check the lowest useful signed minimum value.  We need to load 0x80010000
 ; into the source register.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw min i16 *%src, i16 -32767 seq_cst
   ret i16 %res
@@ -177,15 +177,15 @@ define i16 @f5(i16 *%src) {
 ; Check the highest useful signed maximum value.  We need to load 0x7ffe0000
 ; into the source register.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw max i16 *%src, i16 32766 seq_cst
   ret i16 %res
@@ -194,15 +194,15 @@ define i16 @f6(i16 *%src) {
 ; Check the lowest useful unsigned maximum value.  We need to load 0x00010000
 ; into the source register.
 define i16 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 1
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umin i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -211,15 +211,15 @@ define i16 @f7(i16 *%src) {
 ; Check the highest useful unsigned maximum value.  We need to load 0xfffe0000
 ; into the source register.
 define i16 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umax i16 *%src, i16 65534 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
index 9dca13d15bb..13742b2e419 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
@@ -4,7 +4,7 @@
 
 ; Check signed minium.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
@@ -19,7 +19,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check signed maximum.
 define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
@@ -34,7 +34,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check unsigned minimum.
 define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clr %r2, %r4
@@ -50,7 +50,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check unsigned maximum.
 define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clr %r2, %r4
@@ -66,7 +66,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CS range.
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: l %r2, 4092(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which requires CSY.
 define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ly %r2, 4096(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CSY range.
 define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ly %r2, 524284(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which needs separate address logic.
 define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, 524288
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -111,7 +111,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ly %r2, -4(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the low end of the CSY range.
 define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ly %r2, -524288(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -133,7 +133,7 @@ define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word down, which needs separate address logic.
 define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r3, -524292
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -145,7 +145,7 @@ define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r3, %r4
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -158,7 +158,7 @@ define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
 
 ; Check that constants are handled.
 define i32 @f13(i32 %dummy, i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: lhi [[LIMIT:%r[0-9]+]], 42
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
index d6b5dcd482e..9efa16b38f7 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
@@ -4,7 +4,7 @@
 
 ; Check signed minium.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
@@ -19,7 +19,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check signed maximum.
 define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
@@ -34,7 +34,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check unsigned minimum.
 define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clgr %r2, %r4
@@ -50,7 +50,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check unsigned maximum.
 define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clgr %r2, %r4
@@ -66,7 +66,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the high end of the aligned CSG range.
 define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lg %r2, 524280(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword up, which requires separate address logic.
 define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -89,7 +89,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the low end of the CSG range.
 define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lg %r2, -524288(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword down, which requires separate address logic.
 define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524296
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -112,7 +112,7 @@ define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr %r3, %r4
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -125,7 +125,7 @@ define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
 
 ; Check that constants are handled.
 define i64 @f10(i64 %dummy, i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lghi [[LIMIT:%r[0-9]+]], 42
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
index 260286fe195..cdeeaba3c3a 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -35,7 +35,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: oilf %r3, 16777215
 ; CHECK-SHIFT2: rll
@@ -49,7 +49,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -63,7 +63,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -71,7 +71,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -79,14 +79,14 @@ define i8 @f2(i8 *%src) {
 
 ; Check NANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfeffffff.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65279
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 -2 seq_cst
   ret i8 %res
@@ -94,14 +94,14 @@ define i8 @f3(i8 *%src) {
 
 ; Check NANDs of 1.  We AND the rotated word with 0x01ffffff.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 511
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -109,14 +109,14 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -125,14 +125,14 @@ define i8 @f5(i8 *%src) {
 ; Check NANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfdffffff.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65023
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
index 383c2e513ea..60fdbc782dd 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -35,7 +35,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: oill %r3, 65535
 ; CHECK-SHIFT2: rll
@@ -49,7 +49,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -63,7 +63,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -71,7 +71,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -79,14 +79,14 @@ define i16 @f2(i16 *%src) {
 
 ; Check NANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfffeffff.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65534
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 -2 seq_cst
   ret i16 %res
@@ -94,14 +94,14 @@ define i16 @f3(i16 *%src) {
 
 ; Check ANDs of 1.  We AND the rotated word with 0x0001ffff.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 1
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -109,14 +109,14 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -125,14 +125,14 @@ define i16 @f5(i16 *%src) {
 ; Check NANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfffdffff.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65533
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-03.ll b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
index 56c241690d0..be306a29e36 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
@@ -4,7 +4,7 @@
 
 ; Check NANDs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -19,7 +19,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check NANDs of 1.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -34,7 +34,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check NANDs of the low end of the NILH range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh %r0, 0
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use NILF.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilf %r0, 65536
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILL value.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nill %r0, 65534
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the NILL range.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nill %r0, 0
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILH value, which is one less than the above.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nilh %r0, 65534
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-04.ll b/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
index dee661c9d4b..2fb919d3a34 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
@@ -4,7 +4,7 @@
 
 ; Check NANDs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -20,7 +20,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check NANDs of 1, which must be done using a register.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 1 seq_cst
@@ -29,7 +29,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHF range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -45,7 +45,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 4294967296 seq_cst
@@ -54,7 +54,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHH range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nihh %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 281474976710656 seq_cst
@@ -74,7 +74,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILL value.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nill %r0, 65534
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -85,7 +85,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILL range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nill %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -96,7 +96,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILH value, which is one less than the above.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: nilh %r0, 65534
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -107,7 +107,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -118,7 +118,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILH range.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: nilh %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -129,7 +129,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NILF range.
 define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: nilf %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -140,7 +140,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHL value, which is one less than the above.
 define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: nihl %r0, 65534
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -151,7 +151,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the NIHL range.
 define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: nihl %r0, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -162,7 +162,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHH value, which is 1<<32 less than the above.
 define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: nihh %r0, 65534
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
@@ -173,7 +173,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
 
 ; Check the highest useful NIHF value, which is 1<<32 less than the above.
 define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: nihf %r0, 4294901758
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-01.ll b/test/CodeGen/SystemZ/atomicrmw-or-01.ll
index c63087e87f3..fe1beedce74 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check ORs of -2 (-1 isn't useful).  We OR the rotated word with 0xfe000000.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh [[ROT]], 65024
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 -2 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check ORs of 1.  We OR the rotated word with 0x01000000.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh [[ROT]], 256
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We OR the rotated word with 0x7f000000.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh [[ROT]], 32512
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check ORs of a large unsigned value.  We OR the rotated word with
 ; 0xfd000000.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh [[ROT]], 64768
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-02.ll b/test/CodeGen/SystemZ/atomicrmw-or-02.ll
index 3b8efcb80c5..73bc2826444 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check ORs of -2 (-1 isn't useful).  We OR the rotated word with 0xfffe0000.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh [[ROT]], 65534
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 -2 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check ORs of 1.  We OR the rotated word with 0x00010000.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh [[ROT]], 1
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We OR the rotated word with 0x7fff0000.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh [[ROT]], 32767
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check ORs of a large unsigned value.  We OR the rotated word with
 ; 0xfffd0000.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh [[ROT]], 65533
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-03.ll b/test/CodeGen/SystemZ/atomicrmw-or-03.ll
index 1def200a899..6386847e53e 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-03.ll
@@ -4,7 +4,7 @@
 
 ; Check ORs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the lowest useful OILL value.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the OILL range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oill %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 65535 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the lowest useful OILH value, which is the next value up.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 65536 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the lowest useful OILF value, which is the next value up.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 65537 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the OILH range.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 -65536 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use OILF.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oilf %r0, 4294901761
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 -65535 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful OILF value.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oilf %r0, 4294967294
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 -2 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-04.ll b/test/CodeGen/SystemZ/atomicrmw-or-04.ll
index be0b23cbfe0..de798be1c13 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-04.ll
@@ -4,7 +4,7 @@
 
 ; Check ORs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the lowest useful OILL value.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OILL range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oill %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 65535 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OILH value, which is the next value up.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 65536 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OILF value, which is the next value up again.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 65537 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OILH range.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294901760 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use OILF.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oilf %r0, 4294901761
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294901761 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OILF range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oilf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294967295 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OIHL value, which is one greater than above.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: oihl %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294967296 seq_cst
@@ -96,7 +96,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 ; Check the next value up, which must use a register.  (We could use
 ; combinations of OIH* and OIL* instead, but that isn't implemented.)
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ogr
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294967297 seq_cst
@@ -105,7 +105,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OIHL range.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: oihl %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 281470681743360 seq_cst
@@ -114,7 +114,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OIHH value, which is 1<<32 greater than above.
 define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: oihh %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 281474976710656 seq_cst
@@ -123,7 +123,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OIHF value, which is 1<<32 greater again.
 define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: oihf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 281479271677952 seq_cst
@@ -132,7 +132,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OIHH range.
 define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: oihh %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 18446462598732840960 seq_cst
@@ -141,7 +141,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: ogr
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 18446462598732840961 seq_cst
@@ -150,7 +150,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OIHF range.
 define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: oihf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 -4294967296 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
index b17c36f713a..e1060e05517 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check subtraction of -1.  We add 0x01000000 to the rotated word.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], 16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 -1 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check subtraction of -1.  We add 0xff000000 to the rotated word.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], -16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We add 0x81000000 to the rotated word.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], -2130706432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check subtraction of a large unsigned value.  We add 0x02000000 to the
 ; rotated word.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], 33554432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 254 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
index dbacacdbd6f..499a606f0b6 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check subtraction of -1.  We add 0x00010000 to the rotated word.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], 65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 -1 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check subtraction of 1.  We add 0xffff0000 to the rotated word.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], -65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We add 0x80010000 to the rotated word.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], -2147418112
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check subtraction of a large unsigned value.  We add 0x00020000 to the
 ; rotated word.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], 131072
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 65534 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-03.ll b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
index c2821ad0ca8..b0c17699572 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
@@ -4,7 +4,7 @@
 
 ; Check subtraction of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check subtraction of 1, which can use AHI.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the AHI range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ahi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 32768 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value down, which must use AFI.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 32769 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the AFI range.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 2147483648 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which gets treated as a positive operand.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 2147483649 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check subtraction of -1, which can use AHI.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahi %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 -1 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the AHI range.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ahi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 -32767 seq_cst
@@ -86,7 +86,7 @@ define i32 @f8(i32 %dummy, i32 *%src) {
 
 ; Check the next value down, which must use AFI instead.
 define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 -32768 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-04.ll b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
index 6b3e1c9ae68..c0fd9f9938d 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
@@ -4,7 +4,7 @@
 
 ; Check subtraction of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check subtraction of 1, which can use AGHI.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGHI range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 32768 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use AGFI.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 32769 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGFI range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 2147483648 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register operation.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sgr
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 2147483649 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check subtraction of -1, which can use AGHI.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: aghi %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -1 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGHI range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -32767 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use AGFI instead.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -32768 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGFI range.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -2147483647 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use a register operation.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sgr
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -2147483648 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
index a44eadfc464..d83408f2588 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -24,7 +24,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT-NOT: %r3
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT-NOT: %r3
@@ -43,12 +43,12 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check exchange with a constant.  We should force the constant into
 ; a register and use the sequence above.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[VALUE:%r[0-9]+]], 88
 ; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 39, 24
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: br %r14
   %res = atomicrmw xchg i8 *%src, i8 88 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
index 1b6e84660d6..b00b341d4fc 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -24,7 +24,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT-NOT: %r3
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT-NOT: %r3
@@ -43,12 +43,12 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check exchange with a constant.  We should force the constant into
 ; a register and use the sequence above.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[VALUE:%r[0-9]+]], -25536
 ; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 47, 16
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: br %r14
   %res = atomicrmw xchg i16 *%src, i16 40000 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
index 4a4882667a4..e5ba4d5900c 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
@@ -4,7 +4,7 @@
 
 ; Check register exchange.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r2, %r4, 0(%r3)
@@ -16,7 +16,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CS range.
 define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 4092(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which requires CSY.
 define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ly %r2, 4096(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
 ; CHECK: br %r14
@@ -38,7 +38,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CSY range.
 define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ly %r2, 524284(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which needs separate address logic.
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -61,7 +61,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ly %r2, -4(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
 ; CHECK: br %r14
@@ -72,7 +72,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the low end of the CSY range.
 define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ly %r2, -524288(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word down, which needs separate address logic.
 define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524292
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -95,7 +95,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr %r3, %r4
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -109,7 +109,7 @@ define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
 ; Check exchange of a constant.  We should force it into a register and
 ; use the sequence above.
 define i32 @f10(i32 %dummy, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llill [[VALUE:%r[0-9+]]], 40000
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
index ac1f6cd1da1..c19b34d9fe0 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
@@ -4,7 +4,7 @@
 
 ; Check register exchange.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r2, %r4, 0(%r3)
@@ -16,7 +16,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the high end of the aligned CSG range.
 define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 524280(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword up, which requires separate address logic.
 define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r3, 524288
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -39,7 +39,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the low end of the CSG range.
 define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, -524288(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword down, which requires separate address logic.
 define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, -524296
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -62,7 +62,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agr %r3, %r4
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -76,7 +76,7 @@ define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
 ; Check exchange of a constant.  We should force it into a register and
 ; use the sequence above.
 define i64 @f7(i64 %dummy, i64 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilf [[VALUE:%r[0-9+]]], 3000000000
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
index 5f0957a090b..b457a608732 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check XORs of -1.  We XOR the rotated word with 0xff000000.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 -1 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check XORs of 1.  We XOR the rotated word with 0x01000000.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf [[ROT]], 16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We XOR the rotated word with 0x7f000000.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xilf [[ROT]], 2130706432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check XORs of a large unsigned value.  We XOR the rotated word with
 ; 0xfd000000.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xilf [[ROT]], 4244635648
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
index cdad3ef9ea3..fa38d7027f5 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -26,7 +26,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
 ; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -60,7 +60,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check XORs of -1.  We XOR the rotated word with 0xffff0000.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 -1 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check XORs of 1.  We XOR the rotated word with 0x00010000.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf [[ROT]], 65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We XOR the rotated word with 0x7fff0000.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xilf [[ROT]], 2147418112
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check XORs of a large unsigned value.  We XOR the rotated word with
 ; 0xfffd0000.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xilf [[ROT]], 4294770688
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-03.ll b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
index 0c1951534bb..292de3642bc 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
@@ -4,7 +4,7 @@
 
 ; Check XORs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -18,7 +18,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the lowest useful constant.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check an arbitrary constant.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf %r0, 3000000000
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 3000000000 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check bitwise negation.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 -1 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-04.ll b/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
index 6487b882f40..d767b20a574 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
@@ -4,7 +4,7 @@
 
 ; Check XORs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
@@ -18,7 +18,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the lowest useful XILF value.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the XILF range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 4294967295 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful XIHF value, which is one greater than above.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xihf %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 4294967296 seq_cst
@@ -51,7 +51,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 ; Check the next value up, which must use a register.  (We could use
 ; combinations of XIH* and XIL* instead, but that isn't implemented.)
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xgr
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 4294967297 seq_cst
@@ -60,7 +60,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the XIHF range.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xihf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 -4294967296 seq_cst
@@ -69,7 +69,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xgr
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 -4294967295 seq_cst
diff --git a/test/CodeGen/SystemZ/branch-01.ll b/test/CodeGen/SystemZ/branch-01.ll
index f201ddd2a9d..12ed2d32a80 100644
--- a/test/CodeGen/SystemZ/branch-01.ll
+++ b/test/CodeGen/SystemZ/branch-01.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: mvi 0(%r2), 1
 ; CHECK: j .L[[LABEL]]
diff --git a/test/CodeGen/SystemZ/branch-02.ll b/test/CodeGen/SystemZ/branch-02.ll
index 9f71c053c7b..38b5d27049d 100644
--- a/test/CodeGen/SystemZ/branch-02.ll
+++ b/test/CodeGen/SystemZ/branch-02.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -20,7 +20,7 @@ exit:
 }
 
 define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -35,7 +35,7 @@ exit:
 }
 
 define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -50,7 +50,7 @@ exit:
 }
 
 define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -65,7 +65,7 @@ exit:
 }
 
 define void @f5(i32 *%src, i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -80,7 +80,7 @@ exit:
 }
 
 define void @f6(i32 *%src, i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
diff --git a/test/CodeGen/SystemZ/branch-03.ll b/test/CodeGen/SystemZ/branch-03.ll
index 9d00f6e9af5..ef31a9c696e 100644
--- a/test/CodeGen/SystemZ/branch-03.ll
+++ b/test/CodeGen/SystemZ/branch-03.ll
@@ -3,7 +3,7 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
@@ -18,7 +18,7 @@ exit:
 }
 
 define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
@@ -33,7 +33,7 @@ exit:
 }
 
 define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
@@ -48,7 +48,7 @@ exit:
 }
 
 define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
diff --git a/test/CodeGen/SystemZ/branch-04.ll b/test/CodeGen/SystemZ/branch-04.ll
index d6826fb9cdd..fafb234616f 100644
--- a/test/CodeGen/SystemZ/branch-04.ll
+++ b/test/CodeGen/SystemZ/branch-04.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(float *%src, float %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -19,7 +19,7 @@ exit:
 }
 
 define void @f2(float *%src, float %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -34,7 +34,7 @@ exit:
 }
 
 define void @f3(float *%src, float %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -49,7 +49,7 @@ exit:
 }
 
 define void @f4(float *%src, float %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -64,7 +64,7 @@ exit:
 }
 
 define void @f5(float *%src, float %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -79,7 +79,7 @@ exit:
 }
 
 define void @f6(float *%src, float %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -94,7 +94,7 @@ exit:
 }
 
 define void @f7(float *%src, float %target) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -109,7 +109,7 @@ exit:
 }
 
 define void @f8(float *%src, float %target) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -124,7 +124,7 @@ exit:
 }
 
 define void @f9(float *%src, float %target) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -139,7 +139,7 @@ exit:
 }
 
 define void @f10(float *%src, float %target) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -154,7 +154,7 @@ exit:
 }
 
 define void @f11(float *%src, float %target) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -169,7 +169,7 @@ exit:
 }
 
 define void @f12(float *%src, float %target) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -186,7 +186,7 @@ exit:
 ; "jno" == "jump if no overflow", which corresponds to "jump if ordered"
 ; rather than "jump if not ordered" after a floating-point comparison.
 define void @f13(float *%src, float %target) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -203,7 +203,7 @@ exit:
 ; "jo" == "jump if overflow", which corresponds to "jump if not ordered"
 ; rather than "jump if ordered" after a floating-point comparison.
 define void @f14(float *%src, float %target) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
diff --git a/test/CodeGen/SystemZ/branch-05.ll b/test/CodeGen/SystemZ/branch-05.ll
index 268692a473a..d657c9b8960 100644
--- a/test/CodeGen/SystemZ/branch-05.ll
+++ b/test/CodeGen/SystemZ/branch-05.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i32 @f1(i32 %x, i32 %y, i32 %op) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ahi %r4, -1
 ; CHECK: clfi %r4, 5
 ; CHECK-NEXT: jh
diff --git a/test/CodeGen/SystemZ/branch-06.ll b/test/CodeGen/SystemZ/branch-06.ll
index 5d6610afebf..13e5a843f13 100644
--- a/test/CodeGen/SystemZ/branch-06.ll
+++ b/test/CodeGen/SystemZ/branch-06.ll
@@ -5,7 +5,7 @@
 declare i32 @foo()
 
 define void @f1(i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crje %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -19,7 +19,7 @@ exit:
 }
 
 define void @f2(i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -33,7 +33,7 @@ exit:
 }
 
 define void @f3(i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -47,7 +47,7 @@ exit:
 }
 
 define void @f4(i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -61,7 +61,7 @@ exit:
 }
 
 define void @f5(i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -75,7 +75,7 @@ exit:
 }
 
 define void @f6(i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
diff --git a/test/CodeGen/SystemZ/branch-07.ll b/test/CodeGen/SystemZ/branch-07.ll
index d009af2f1f0..b715a059bc7 100644
--- a/test/CodeGen/SystemZ/branch-07.ll
+++ b/test/CodeGen/SystemZ/branch-07.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Test EQ.
 define void @f1(i64 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrje %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -21,7 +21,7 @@ exit:
 
 ; Test NE.
 define void @f2(i64 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -36,7 +36,7 @@ exit:
 
 ; Test SLE.
 define void @f3(i64 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -51,7 +51,7 @@ exit:
 
 ; Test SLT.
 define void @f4(i64 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -66,7 +66,7 @@ exit:
 
 ; Test SGT.
 define void @f5(i64 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -81,7 +81,7 @@ exit:
 
 ; Test SGE.
 define void @f6(i64 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -96,7 +96,7 @@ exit:
 
 ; Test a vector of 0/-1 results for i32 EQ.
 define i64 @f7(i64 %a, i64 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: crje {{%r[0-5]}}
 ; CHECK: lhi [[REG]], 0
@@ -112,7 +112,7 @@ define i64 @f7(i64 %a, i64 %b) {
 
 ; Test a vector of 0/-1 results for i32 NE.
 define i64 @f8(i64 %a, i64 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: crjlh {{%r[0-5]}}
 ; CHECK: lhi [[REG]], 0
@@ -128,7 +128,7 @@ define i64 @f8(i64 %a, i64 %b) {
 
 ; Test a vector of 0/-1 results for i64 EQ.
 define void @f9(i64 %a, i64 %b, <2 x i64> *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lghi [[REG:%r[0-5]]], -1
 ; CHECK: crje {{%r[0-5]}}
 ; CHECK: lghi [[REG]], 0
@@ -144,7 +144,7 @@ define void @f9(i64 %a, i64 %b, <2 x i64> *%dest) {
 
 ; Test a vector of 0/-1 results for i64 NE.
 define void @f10(i64 %a, i64 %b, <2 x i64> *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lghi [[REG:%r[0-5]]], -1
 ; CHECK: crjlh {{%r[0-5]}}
 ; CHECK: lghi [[REG]], 0
diff --git a/test/CodeGen/SystemZ/bswap-01.ll b/test/CodeGen/SystemZ/bswap-01.ll
index 23bc35ca48b..7e6c83af3f8 100644
--- a/test/CodeGen/SystemZ/bswap-01.ll
+++ b/test/CodeGen/SystemZ/bswap-01.ll
@@ -7,7 +7,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check 32-bit register-to-register byteswaps.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lrvr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: br %r14
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
@@ -16,7 +16,7 @@ define i32 @f1(i32 %a) {
 
 ; Check 64-bit register-to-register byteswaps.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lrvgr %r2, %r2
 ; CHECK: br %r14
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
diff --git a/test/CodeGen/SystemZ/bswap-02.ll b/test/CodeGen/SystemZ/bswap-02.ll
index e2ae011f173..db69ea53dfe 100644
--- a/test/CodeGen/SystemZ/bswap-02.ll
+++ b/test/CodeGen/SystemZ/bswap-02.ll
@@ -6,7 +6,7 @@ declare i32 @llvm.bswap.i32(i32 %a)
 
 ; Check LRV with no displacement.
 define i32 @f1(i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
   %a = load i32 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 *%src) {
 
 ; Check the high end of the aligned LRV range.
 define i32 @f2(i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lrv %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -28,7 +28,7 @@ define i32 @f2(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define i32 @f3(i32 *%src) {
 
 ; Check the high end of the negative aligned LRV range.
 define i32 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lrv %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -51,7 +51,7 @@ define i32 @f4(i32 *%src) {
 
 ; Check the low end of the LRV range.
 define i32 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lrv %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -63,7 +63,7 @@ define i32 @f5(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524292
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define i32 @f6(i32 *%src) {
 
 ; Check that LRV allows an index.
 define i32 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lrv %r2, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define i32 @f7(i64 %src, i64 %index) {
 ; Check that volatile accesses do not use LRV, which might access the
 ; storage multple times.
 define i32 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: l [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: lrvr %r2, [[REG]]
 ; CHECK: br %r14
@@ -101,7 +101,7 @@ define i32 @f8(i32 *%src) {
 ; Test a case where we spill the source of at least one LRVR.  We want
 ; to use LRV if possible.
 define void @f9(i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lrv {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/bswap-03.ll b/test/CodeGen/SystemZ/bswap-03.ll
index e3ccc3841e7..d9e5ad1b52f 100644
--- a/test/CodeGen/SystemZ/bswap-03.ll
+++ b/test/CodeGen/SystemZ/bswap-03.ll
@@ -6,7 +6,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check LRVG with no displacement.
 define i64 @f1(i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
   %a = load i64 *%src
@@ -16,7 +16,7 @@ define i64 @f1(i64 *%src) {
 
 ; Check the high end of the aligned LRVG range.
 define i64 @f2(i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lrvg %r2, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -28,7 +28,7 @@ define i64 @f2(i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f3(i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define i64 @f3(i64 *%src) {
 
 ; Check the high end of the negative aligned LRVG range.
 define i64 @f4(i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lrvg %r2, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -51,7 +51,7 @@ define i64 @f4(i64 *%src) {
 
 ; Check the low end of the LRVG range.
 define i64 @f5(i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lrvg %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -63,7 +63,7 @@ define i64 @f5(i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define i64 @f6(i64 *%src) {
 
 ; Check that LRVG allows an index.
 define i64 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lrvg %r2, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define i64 @f7(i64 %src, i64 %index) {
 ; Check that volatile accesses do not use LRVG, which might access the
 ; storage multple times.
 define i64 @f8(i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: lrvgr %r2, [[REG]]
 ; CHECK: br %r14
@@ -101,7 +101,7 @@ define i64 @f8(i64 *%src) {
 ; Test a case where we spill the source of at least one LRVGR.  We want
 ; to use LRVG if possible.
 define void @f9(i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lrvg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/bswap-04.ll b/test/CodeGen/SystemZ/bswap-04.ll
index 63b202044e4..29d5a7b0721 100644
--- a/test/CodeGen/SystemZ/bswap-04.ll
+++ b/test/CodeGen/SystemZ/bswap-04.ll
@@ -6,7 +6,7 @@ declare i32 @llvm.bswap.i32(i32 %a)
 
 ; Check STRV with no displacement.
 define void @f1(i32 *%dst, i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
@@ -16,7 +16,7 @@ define void @f1(i32 *%dst, i32 %a) {
 
 ; Check the high end of the aligned STRV range.
 define void @f2(i32 *%dst, i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strv %r3, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 131071
@@ -28,7 +28,7 @@ define void @f2(i32 *%dst, i32 %a) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i32 *%dst, i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define void @f3(i32 *%dst, i32 %a) {
 
 ; Check the high end of the negative aligned STRV range.
 define void @f4(i32 *%dst, i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strv %r3, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -1
@@ -51,7 +51,7 @@ define void @f4(i32 *%dst, i32 %a) {
 
 ; Check the low end of the STRV range.
 define void @f5(i32 *%dst, i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strv %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -131072
@@ -63,7 +63,7 @@ define void @f5(i32 *%dst, i32 %a) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i32 *%dst, i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524292
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f6(i32 *%dst, i32 %a) {
 
 ; Check that STRV allows an index.
 define void @f7(i64 %src, i64 %index, i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: strv %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define void @f7(i64 %src, i64 %index, i32 %a) {
 ; Check that volatile stores do not use STRV, which might access the
 ; storage multple times.
 define void @f8(i32 *%dst, i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lrvr [[REG:%r[0-5]]], %r3
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/bswap-05.ll b/test/CodeGen/SystemZ/bswap-05.ll
index 6f25d3c10ab..5c8361e26ce 100644
--- a/test/CodeGen/SystemZ/bswap-05.ll
+++ b/test/CodeGen/SystemZ/bswap-05.ll
@@ -6,7 +6,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check STRVG with no displacement.
 define void @f1(i64 *%dst, i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
@@ -16,7 +16,7 @@ define void @f1(i64 *%dst, i64 %a) {
 
 ; Check the high end of the aligned STRVG range.
 define void @f2(i64 *%dst, i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strvg %r3, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 65535
@@ -28,7 +28,7 @@ define void @f2(i64 *%dst, i64 %a) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 *%dst, i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define void @f3(i64 *%dst, i64 %a) {
 
 ; Check the high end of the negative aligned STRVG range.
 define void @f4(i64 *%dst, i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strvg %r3, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -1
@@ -51,7 +51,7 @@ define void @f4(i64 *%dst, i64 %a) {
 
 ; Check the low end of the STRVG range.
 define void @f5(i64 *%dst, i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strvg %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -65536
@@ -63,7 +63,7 @@ define void @f5(i64 *%dst, i64 %a) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%dst, i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f6(i64 *%dst, i64 %a) {
 
 ; Check that STRVG allows an index.
 define void @f7(i64 %src, i64 %index, i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: strvg %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define void @f7(i64 %src, i64 %index, i64 %a) {
 ; Check that volatile stores do not use STRVG, which might access the
 ; storage multple times.
 define void @f8(i64 *%dst, i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lrvgr [[REG:%r[0-5]]], %r3
 ; CHECK: stg [[REG]], 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/call-01.ll b/test/CodeGen/SystemZ/call-01.ll
index 1b9172bdd81..42b6afdd98d 100644
--- a/test/CodeGen/SystemZ/call-01.ll
+++ b/test/CodeGen/SystemZ/call-01.ll
@@ -6,7 +6,7 @@ declare i64 @bar()
 
 ; We must allocate 160 bytes for the callee and save and restore %r14.
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: aghi %r15, -160
 ; CHECK: brasl %r14, bar@PLT
diff --git a/test/CodeGen/SystemZ/call-02.ll b/test/CodeGen/SystemZ/call-02.ll
index 07dd67bab1b..5f14d12249f 100644
--- a/test/CodeGen/SystemZ/call-02.ll
+++ b/test/CodeGen/SystemZ/call-02.ll
@@ -4,7 +4,7 @@
 
 ; We must allocate 160 bytes for the callee and save and restore %r14.
 define i64 @f1(i64() *%bar) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: aghi %r15, -160
 ; CHECK: basr %r14, %r2
diff --git a/test/CodeGen/SystemZ/cmpxchg-01.ll b/test/CodeGen/SystemZ/cmpxchg-01.ll
index bbb0aabb07e..c6f10380c2f 100644
--- a/test/CodeGen/SystemZ/cmpxchg-01.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-01.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
 ; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; CHECK-MAIN-NOT: %r2
 ; CHECK-MAIN: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT: rll
@@ -39,13 +39,13 @@ define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; Check compare and swap with constants.  We should force the constants into
 ; registers and use the sequence above.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[CMP:%r[0-9]+]], 42
 ; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 55, 0
 ; CHECK: risbg
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
 ; CHECK-SHIFT: risbg
 ; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 55, 0
diff --git a/test/CodeGen/SystemZ/cmpxchg-02.ll b/test/CodeGen/SystemZ/cmpxchg-02.ll
index 5f2dd3aa7d5..fa2d088295b 100644
--- a/test/CodeGen/SystemZ/cmpxchg-02.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-02.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
 ; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
@@ -27,7 +27,7 @@ define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; CHECK-MAIN-NOT: %r2
 ; CHECK-MAIN: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT: rll
@@ -39,13 +39,13 @@ define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; Check compare and swap with constants.  We should force the constants into
 ; registers and use the sequence above.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[CMP:%r[0-9]+]], 42
 ; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 47, 0
 ; CHECK: risbg
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
 ; CHECK-SHIFT: risbg
 ; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 47, 0
diff --git a/test/CodeGen/SystemZ/cmpxchg-03.ll b/test/CodeGen/SystemZ/cmpxchg-03.ll
index 45e224eda84..3917979ac24 100644
--- a/test/CodeGen/SystemZ/cmpxchg-03.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-03.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the CS range.
 define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
   %val = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst
@@ -13,7 +13,7 @@ define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the high end of the aligned CS range.
 define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cs %r2, %r3, 4092(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -23,7 +23,7 @@ define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the next word up, which should use CSY instead of CS.
 define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: csy %r2, %r3, 4096(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -33,7 +33,7 @@ define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the high end of the aligned CSY range.
 define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: csy %r2, %r3, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -44,7 +44,7 @@ define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r4, 524288
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: csy %r2, %r3, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the low end of the CSY range.
 define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: csy %r2, %r3, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +76,7 @@ define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, -524292
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check that CS does not allow an index.
 define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr %r4, %r5
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
 
 ; Check that CSY does not allow an index.
 define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r4, %r5
 ; CHECK: csy %r2, %r3, 4096(%r4)
 ; CHECK: br %r14
@@ -112,7 +112,7 @@ define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
 
 ; Check that a constant %cmp value is loaded into a register first.
 define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lhi %r2, 1001
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) {
 
 ; Check that a constant %swap value is loaded into a register first.
 define i32 @f12(i32 %cmp, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lhi [[SWAP:%r[0-9]+]], 1002
 ; CHECK: cs %r2, [[SWAP]], 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/cmpxchg-04.ll b/test/CodeGen/SystemZ/cmpxchg-04.ll
index f8969ee0844..f58868f04f2 100644
--- a/test/CodeGen/SystemZ/cmpxchg-04.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-04.ll
@@ -4,7 +4,7 @@
 
 ; Check CSG without a displacement.
 define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
   %val = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst
@@ -13,7 +13,7 @@ define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check the high end of the aligned CSG range.
 define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: csg %r2, %r3, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -24,7 +24,7 @@ define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r4, 524288
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check the high end of the negative aligned CSG range.
 define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: csg %r2, %r3, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -45,7 +45,7 @@ define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check the low end of the CSG range.
 define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: csg %r2, %r3, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -56,7 +56,7 @@ define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r4, -524296
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check that CSG does not allow an index.
 define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agr %r4, %r5
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -79,7 +79,7 @@ define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
 
 ; Check that a constant %cmp value is loaded into a register first.
 define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lghi %r2, 1001
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
 
 ; Check that a constant %swap value is loaded into a register first.
 define i64 @f9(i64 %cmp, i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lghi [[SWAP:%r[0-9]+]], 1002
 ; CHECK: csg %r2, [[SWAP]], 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/cond-store-01.ll b/test/CodeGen/SystemZ/cond-store-01.ll
index fadcae5e90a..a734eeeb410 100644
--- a/test/CodeGen/SystemZ/cond-store-01.ll
+++ b/test/CodeGen/SystemZ/cond-store-01.ll
@@ -6,7 +6,7 @@ declare void @foo(i8 *)
 
 ; Test the simple case, with the loaded value first.
 define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -39,7 +39,7 @@ define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 32 bits, with the
 ; loaded value first.
 define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -57,7 +57,7 @@ define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -76,7 +76,7 @@ define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
 ; loaded value first.
 define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -94,7 +94,7 @@ define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -113,7 +113,7 @@ define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
 ; loaded value first.
 define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -131,7 +131,7 @@ define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -150,7 +150,7 @@ define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 64 bits, with the
 ; loaded value first.
 define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -168,7 +168,7 @@ define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -186,7 +186,7 @@ define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
 
 ; Check the high end of the STC range.
 define void @f11(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -203,7 +203,7 @@ define void @f11(i8 *%base, i8 %alt, i32 %limit) {
 
 ; Check the next byte up, which should use STCY instead of STC.
 define void @f12(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -220,7 +220,7 @@ define void @f12(i8 *%base, i8 %alt, i32 %limit) {
 
 ; Check the high end of the STCY range.
 define void @f13(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -238,7 +238,7 @@ define void @f13(i8 *%base, i8 %alt, i32 %limit) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f14(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -256,7 +256,7 @@ define void @f14(i8 *%base, i8 %alt, i32 %limit) {
 
 ; Check the low end of the STCY range.
 define void @f15(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -274,7 +274,7 @@ define void @f15(i8 *%base, i8 %alt, i32 %limit) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f16(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -292,7 +292,7 @@ define void @f16(i8 *%base, i8 %alt, i32 %limit) {
 
 ; Check that STCY allows an index.
 define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -311,7 +311,7 @@ define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: lb {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -326,7 +326,7 @@ define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lb %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -345,7 +345,7 @@ define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
 ; to restrict the test to a stronger ordering.
 define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CS.
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: cs {{%r[0-9]+}},
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -361,7 +361,7 @@ define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
 ; ...likewise stores.
 define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CS.
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lb %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -376,7 +376,7 @@ define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f22(i8 %alt, i32 %limit) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-02.ll b/test/CodeGen/SystemZ/cond-store-02.ll
index 51f3ffc0f75..58550bf192a 100644
--- a/test/CodeGen/SystemZ/cond-store-02.ll
+++ b/test/CodeGen/SystemZ/cond-store-02.ll
@@ -6,7 +6,7 @@ declare void @foo(i16 *)
 
 ; Test the simple case, with the loaded value first.
 define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -39,7 +39,7 @@ define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 32 bits, with the
 ; loaded value first.
 define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -57,7 +57,7 @@ define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -76,7 +76,7 @@ define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
 ; loaded value first.
 define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -94,7 +94,7 @@ define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -113,7 +113,7 @@ define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
 ; loaded value first.
 define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -131,7 +131,7 @@ define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -150,7 +150,7 @@ define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 64 bits, with the
 ; loaded value first.
 define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -168,7 +168,7 @@ define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -186,7 +186,7 @@ define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
 
 ; Check the high end of the aligned STH range.
 define void @f11(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -203,7 +203,7 @@ define void @f11(i16 *%base, i16 %alt, i32 %limit) {
 
 ; Check the next halfword up, which should use STHY instead of STH.
 define void @f12(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -220,7 +220,7 @@ define void @f12(i16 *%base, i16 %alt, i32 %limit) {
 
 ; Check the high end of the aligned STHY range.
 define void @f13(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -238,7 +238,7 @@ define void @f13(i16 *%base, i16 %alt, i32 %limit) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f14(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -256,7 +256,7 @@ define void @f14(i16 *%base, i16 %alt, i32 %limit) {
 
 ; Check the low end of the STHY range.
 define void @f15(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -274,7 +274,7 @@ define void @f15(i16 *%base, i16 %alt, i32 %limit) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f16(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -292,7 +292,7 @@ define void @f16(i16 *%base, i16 %alt, i32 %limit) {
 
 ; Check that STHY allows an index.
 define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -311,7 +311,7 @@ define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: lh {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -326,7 +326,7 @@ define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lh %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -345,7 +345,7 @@ define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
 ; to restrict the test to a stronger ordering.
 define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CS.
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: cs {{%r[0-9]+}},
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -361,7 +361,7 @@ define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
 ; ...likewise stores.
 define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CS.
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lh %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -376,7 +376,7 @@ define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f22(i16 %alt, i32 %limit) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-03.ll b/test/CodeGen/SystemZ/cond-store-03.ll
index 6f19fbc3598..ba076b0acdb 100644
--- a/test/CodeGen/SystemZ/cond-store-03.ll
+++ b/test/CodeGen/SystemZ/cond-store-03.ll
@@ -6,7 +6,7 @@ declare void @foo(i32 *)
 
 ; Test the simple case, with the loaded value first.
 define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -39,7 +39,7 @@ define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
 ; loaded value first.
 define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -57,7 +57,7 @@ define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -76,7 +76,7 @@ define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
 ; loaded value first.
 define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -94,7 +94,7 @@ define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -112,7 +112,7 @@ define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
 
 ; Check the high end of the aligned ST range.
 define void @f7(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -129,7 +129,7 @@ define void @f7(i32 *%base, i32 %alt, i32 %limit) {
 
 ; Check the next word up, which should use STY instead of ST.
 define void @f8(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -146,7 +146,7 @@ define void @f8(i32 *%base, i32 %alt, i32 %limit) {
 
 ; Check the high end of the aligned STY range.
 define void @f9(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -164,7 +164,7 @@ define void @f9(i32 *%base, i32 %alt, i32 %limit) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -182,7 +182,7 @@ define void @f10(i32 *%base, i32 %alt, i32 %limit) {
 
 ; Check the low end of the STY range.
 define void @f11(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -200,7 +200,7 @@ define void @f11(i32 *%base, i32 %alt, i32 %limit) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f12(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -218,7 +218,7 @@ define void @f12(i32 *%base, i32 %alt, i32 %limit) {
 
 ; Check that STY allows an index.
 define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -237,7 +237,7 @@ define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -252,7 +252,7 @@ define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: l %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -271,7 +271,7 @@ define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
 ; to restrict the test to a stronger ordering.
 define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CS.
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cs {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -287,7 +287,7 @@ define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
 ; ...likewise stores.
 define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CS.
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: l %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -302,7 +302,7 @@ define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f18(i32 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-04.ll b/test/CodeGen/SystemZ/cond-store-04.ll
index 22f5fd42265..f00c94cb420 100644
--- a/test/CodeGen/SystemZ/cond-store-04.ll
+++ b/test/CodeGen/SystemZ/cond-store-04.ll
@@ -6,7 +6,7 @@ declare void @foo(i64 *)
 
 ; Test with the loaded value first.
 define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -38,7 +38,7 @@ define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; Check the high end of the aligned STG range.
 define void @f3(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -56,7 +56,7 @@ define void @f3(i64 *%base, i64 %alt, i32 %limit) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -74,7 +74,7 @@ define void @f4(i64 *%base, i64 %alt, i32 %limit) {
 
 ; Check the low end of the STG range.
 define void @f5(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -92,7 +92,7 @@ define void @f5(i64 *%base, i64 %alt, i32 %limit) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -110,7 +110,7 @@ define void @f6(i64 *%base, i64 %alt, i32 %limit) {
 
 ; Check that STG allows an index.
 define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -129,7 +129,7 @@ define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lg {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -144,7 +144,7 @@ define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %r3.
 define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -163,7 +163,7 @@ define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
 ; to restrict the test to a stronger ordering.
 define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
 ; FIXME: should use a normal load instead of CSG.
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: csg {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -179,7 +179,7 @@ define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
 ; ...likewise stores.
 define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
 ; FIXME: should use a normal store instead of CSG.
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: lg %r3, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -194,7 +194,7 @@ define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f12(i64 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-05.ll b/test/CodeGen/SystemZ/cond-store-05.ll
index 5bcfed0cd4a..131d1020cce 100644
--- a/test/CodeGen/SystemZ/cond-store-05.ll
+++ b/test/CodeGen/SystemZ/cond-store-05.ll
@@ -6,7 +6,7 @@ declare void @foo(float *)
 
 ; Test with the loaded value first.
 define void @f1(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(float *%ptr, float %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -38,7 +38,7 @@ define void @f2(float *%ptr, float %alt, i32 %limit) {
 
 ; Check the high end of the aligned STE range.
 define void @f3(float *%base, float %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -55,7 +55,7 @@ define void @f3(float *%base, float %alt, i32 %limit) {
 
 ; Check the next word up, which should use STEY instead of STE.
 define void @f4(float *%base, float %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -72,7 +72,7 @@ define void @f4(float *%base, float %alt, i32 %limit) {
 
 ; Check the high end of the aligned STEY range.
 define void @f5(float *%base, float %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -90,7 +90,7 @@ define void @f5(float *%base, float %alt, i32 %limit) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(float *%base, float %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -108,7 +108,7 @@ define void @f6(float *%base, float %alt, i32 %limit) {
 
 ; Check the low end of the STEY range.
 define void @f7(float *%base, float %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -126,7 +126,7 @@ define void @f7(float *%base, float %alt, i32 %limit) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(float *%base, float %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -144,7 +144,7 @@ define void @f8(float *%base, float %alt, i32 %limit) {
 
 ; Check that STEY allows an index.
 define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -163,7 +163,7 @@ define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f10(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: le {{%f[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -178,7 +178,7 @@ define void @f10(float *%ptr, float %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %f0.
 define void @f11(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -193,7 +193,7 @@ define void @f11(float *%ptr, float %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f12(float %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/cond-store-06.ll b/test/CodeGen/SystemZ/cond-store-06.ll
index 203a0b04fb9..1c2d716e5ff 100644
--- a/test/CodeGen/SystemZ/cond-store-06.ll
+++ b/test/CodeGen/SystemZ/cond-store-06.ll
@@ -6,7 +6,7 @@ declare void @foo(double *)
 
 ; Test with the loaded value first.
 define void @f1(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -22,7 +22,7 @@ define void @f1(double *%ptr, double %alt, i32 %limit) {
 
 ; ...and with the loaded value second
 define void @f2(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -38,7 +38,7 @@ define void @f2(double *%ptr, double %alt, i32 %limit) {
 
 ; Check the high end of the aligned STD range.
 define void @f3(double *%base, double %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -55,7 +55,7 @@ define void @f3(double *%base, double %alt, i32 %limit) {
 
 ; Check the next doubleword up, which should use STDY instead of STD.
 define void @f4(double *%base, double %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -72,7 +72,7 @@ define void @f4(double *%base, double %alt, i32 %limit) {
 
 ; Check the high end of the aligned STDY range.
 define void @f5(double *%base, double %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -90,7 +90,7 @@ define void @f5(double *%base, double %alt, i32 %limit) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(double *%base, double %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -108,7 +108,7 @@ define void @f6(double *%base, double %alt, i32 %limit) {
 
 ; Check the low end of the STDY range.
 define void @f7(double *%base, double %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -126,7 +126,7 @@ define void @f7(double *%base, double %alt, i32 %limit) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(double *%base, double %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -144,7 +144,7 @@ define void @f8(double *%base, double %alt, i32 %limit) {
 
 ; Check that STDY allows an index.
 define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
 ; CHECK: jl [[LABEL:[^ ]*]]
 ; CHECK-NOT: %r2
@@ -163,7 +163,7 @@ define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) {
 
 ; Check that volatile loads are not matched.
 define void @f10(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ld {{%f[0-5]}}, 0(%r2)
 ; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
 ; CHECK: [[LABEL]]:
@@ -178,7 +178,7 @@ define void @f10(double *%ptr, double %alt, i32 %limit) {
 
 ; ...likewise stores.  In this case we should have a conditional load into %f0.
 define void @f11(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: jnl [[LABEL:[^ ]*]]
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: [[LABEL]]:
@@ -193,7 +193,7 @@ define void @f11(double *%ptr, double %alt, i32 %limit) {
 
 ; Try a frame index base.
 define void @f12(double %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK-NOT: %r15
 ; CHECK: jl [[LABEL:[^ ]*]]
diff --git a/test/CodeGen/SystemZ/fp-abs-01.ll b/test/CodeGen/SystemZ/fp-abs-01.ll
index 81b3fb273d1..0b4067da3d1 100644
--- a/test/CodeGen/SystemZ/fp-abs-01.ll
+++ b/test/CodeGen/SystemZ/fp-abs-01.ll
@@ -5,7 +5,7 @@
 ; Test f32.
 declare float @llvm.fabs.f32(float %f)
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lpebr %f0, %f0
 ; CHECK: br %r14
   %res = call float @llvm.fabs.f32(float %f)
@@ -15,7 +15,7 @@ define float @f1(float %f) {
 ; Test f64.
 declare double @llvm.fabs.f64(double %f)
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lpdbr %f0, %f0
 ; CHECK: br %r14
   %res = call double @llvm.fabs.f64(double %f)
@@ -27,7 +27,7 @@ define double @f2(double %f) {
 ; processing so that using FPRs is unequivocally better.
 declare fp128 @llvm.fabs.f128(fp128 %f)
 define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lpxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-abs-02.ll b/test/CodeGen/SystemZ/fp-abs-02.ll
index 513d49c7acf..909c48a0637 100644
--- a/test/CodeGen/SystemZ/fp-abs-02.ll
+++ b/test/CodeGen/SystemZ/fp-abs-02.ll
@@ -5,7 +5,7 @@
 ; Test f32.
 declare float @llvm.fabs.f32(float %f)
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lnebr %f0, %f0
 ; CHECK: br %r14
   %abs = call float @llvm.fabs.f32(float %f)
@@ -16,7 +16,7 @@ define float @f1(float %f) {
 ; Test f64.
 declare double @llvm.fabs.f64(double %f)
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lndbr %f0, %f0
 ; CHECK: br %r14
   %abs = call double @llvm.fabs.f64(double %f)
@@ -29,7 +29,7 @@ define double @f2(double %f) {
 ; extra processing so that using FPRs is unequivocally better.
 declare fp128 @llvm.fabs.f128(fp128 %f)
 define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lnxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-add-01.ll b/test/CodeGen/SystemZ/fp-add-01.ll
index c25820a4d85..28a212801a6 100644
--- a/test/CodeGen/SystemZ/fp-add-01.ll
+++ b/test/CodeGen/SystemZ/fp-add-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register addition.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aebr %f0, %f2
 ; CHECK: br %r14
   %res = fadd float %f1, %f2
@@ -15,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the AEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned AEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that AEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: aeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define float @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that additions of spilled values can use AEB rather than AEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: aeb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-add-02.ll b/test/CodeGen/SystemZ/fp-add-02.ll
index 58afc1323a4..067c7474fb4 100644
--- a/test/CodeGen/SystemZ/fp-add-02.ll
+++ b/test/CodeGen/SystemZ/fp-add-02.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check register addition.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adbr %f0, %f2
 ; CHECK: br %r14
   %res = fadd double %f1, %f2
@@ -15,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the ADB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned ADB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: adb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that ADB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: adb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define double @f6(double %f1, double *%base, i64 %index) {
 
 ; Check that additions of spilled values can use ADB rather than ADBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: adb %f0, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-add-03.ll b/test/CodeGen/SystemZ/fp-add-03.ll
index 13ffb023b6f..cb4042eee47 100644
--- a/test/CodeGen/SystemZ/fp-add-03.ll
+++ b/test/CodeGen/SystemZ/fp-add-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit addition.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-cmp-01.ll b/test/CodeGen/SystemZ/fp-cmp-01.ll
index 5aef57f6400..d59640ec071 100644
--- a/test/CodeGen/SystemZ/fp-cmp-01.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check comparison with registers.
 define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cebr %f0, %f2
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -18,7 +18,7 @@ define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
 
 ; Check the low end of the CEB range.
 define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ceb %f0, 0(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -31,7 +31,7 @@ define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
 
 ; Check the high end of the aligned CEB range.
 define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ceb %f0, 4092(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -46,7 +46,7 @@ define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r4, 4096
 ; CHECK: ceb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -61,7 +61,7 @@ define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r4, -4
 ; CHECK: ceb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -76,7 +76,7 @@ define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
 
 ; Check that CEB allows indices.
 define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r5, 2
 ; CHECK: ceb %f0, 400(%r1,%r4)
 ; CHECK-NEXT: je
@@ -92,7 +92,7 @@ define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
 
 ; Check that comparisons of spilled values can use CEB rather than CEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ceb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-cmp-02.ll b/test/CodeGen/SystemZ/fp-cmp-02.ll
index c5bdd56037e..48374a722bb 100644
--- a/test/CodeGen/SystemZ/fp-cmp-02.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-02.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check comparison with registers.
 define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cdbr %f0, %f2
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -18,7 +18,7 @@ define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
 
 ; Check the low end of the CDB range.
 define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdb %f0, 0(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -31,7 +31,7 @@ define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
 
 ; Check the high end of the aligned CDB range.
 define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cdb %f0, 4088(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -46,7 +46,7 @@ define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r4, 4096
 ; CHECK: cdb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -61,7 +61,7 @@ define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r4, -8
 ; CHECK: cdb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -76,7 +76,7 @@ define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) {
 
 ; Check that CDB allows indices.
 define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r5, 3
 ; CHECK: cdb %f0, 800(%r1,%r4)
 ; CHECK-NEXT: je
@@ -92,7 +92,7 @@ define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
 
 ; Check that comparisons of spilled values can use CDB rather than CDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: cdb {{%f[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-cmp-03.ll b/test/CodeGen/SystemZ/fp-cmp-03.ll
index 1a5009e35f3..3badc46352c 100644
--- a/test/CodeGen/SystemZ/fp-cmp-03.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit comparison.
 define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r4)
 ; CHECK: ld %f3, 8(%r4)
diff --git a/test/CodeGen/SystemZ/fp-const-01.ll b/test/CodeGen/SystemZ/fp-const-01.ll
index 65209d661e9..3a4ddf08780 100644
--- a/test/CodeGen/SystemZ/fp-const-01.ll
+++ b/test/CodeGen/SystemZ/fp-const-01.ll
@@ -4,7 +4,7 @@
 
 ; Test f32.
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lzer %f0
 ; CHECK: br %r14
   ret float 0.0
@@ -12,7 +12,7 @@ define float @f1() {
 
 ; Test f64.
 define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lzdr %f0
 ; CHECK: br %r14
   ret double 0.0
@@ -20,7 +20,7 @@ define double @f2() {
 
 ; Test f128.
 define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzxr %f0
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-const-02.ll b/test/CodeGen/SystemZ/fp-const-02.ll
index 2dedf54e6f7..96f857895ec 100644
--- a/test/CodeGen/SystemZ/fp-const-02.ll
+++ b/test/CodeGen/SystemZ/fp-const-02.ll
@@ -4,7 +4,7 @@
 
 ; Test f32.
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lzer [[REGISTER:%f[0-5]+]]
 ; CHECK: lcebr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -13,7 +13,7 @@ define float @f1() {
 
 ; Test f64.
 define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lzdr [[REGISTER:%f[0-5]+]]
 ; CHECK: lcdbr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define double @f2() {
 
 ; Test f128.
 define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzxr [[REGISTER:%f[0-5]+]]
 ; CHECK: lcxbr %f0, [[REGISTER]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-03.ll b/test/CodeGen/SystemZ/fp-const-03.ll
index 4c287e4c08a..b2ae94db0b7 100644
--- a/test/CodeGen/SystemZ/fp-const-03.ll
+++ b/test/CodeGen/SystemZ/fp-const-03.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
 ; CHECK: le %f0, 0([[REGISTER]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-04.ll b/test/CodeGen/SystemZ/fp-const-04.ll
index 847c380e3b9..d5526884dc6 100644
--- a/test/CodeGen/SystemZ/fp-const-04.ll
+++ b/test/CodeGen/SystemZ/fp-const-04.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define double @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
 ; CHECK: ldeb %f0, 0([[REGISTER]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-05.ll b/test/CodeGen/SystemZ/fp-const-05.ll
index 48f84ce5bee..d81e3db91f4 100644
--- a/test/CodeGen/SystemZ/fp-const-05.ll
+++ b/test/CodeGen/SystemZ/fp-const-05.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: lxeb %f0, 0([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
diff --git a/test/CodeGen/SystemZ/fp-const-06.ll b/test/CodeGen/SystemZ/fp-const-06.ll
index 1da3d5eafaa..088810ba8e4 100644
--- a/test/CodeGen/SystemZ/fp-const-06.ll
+++ b/test/CodeGen/SystemZ/fp-const-06.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define double @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-07.ll b/test/CodeGen/SystemZ/fp-const-07.ll
index 5a108452a8e..87e8f68b372 100644
--- a/test/CodeGen/SystemZ/fp-const-07.ll
+++ b/test/CodeGen/SystemZ/fp-const-07.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: lxdb %f0, 0([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
diff --git a/test/CodeGen/SystemZ/fp-const-08.ll b/test/CodeGen/SystemZ/fp-const-08.ll
index 6a8a1ab3f9b..8845adbebc5 100644
--- a/test/CodeGen/SystemZ/fp-const-08.ll
+++ b/test/CodeGen/SystemZ/fp-const-08.ll
@@ -6,7 +6,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
diff --git a/test/CodeGen/SystemZ/fp-const-09.ll b/test/CodeGen/SystemZ/fp-const-09.ll
index 435dcbacc19..0c7d726e9d0 100644
--- a/test/CodeGen/SystemZ/fp-const-09.ll
+++ b/test/CodeGen/SystemZ/fp-const-09.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
diff --git a/test/CodeGen/SystemZ/fp-conv-01.ll b/test/CodeGen/SystemZ/fp-conv-01.ll
index 6c8ef489977..49ed43bce51 100644
--- a/test/CodeGen/SystemZ/fp-conv-01.ll
+++ b/test/CodeGen/SystemZ/fp-conv-01.ll
@@ -4,7 +4,7 @@
 
 ; Test f64->f32.
 define float @f1(double %d1, double %d2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ledbr %f0, %f2
 ; CHECK: br %r14
   %res = fptrunc double %d2 to float
@@ -13,7 +13,7 @@ define float @f1(double %d1, double %d2) {
 
 ; Test f128->f32.
 define float @f2(fp128 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lexbr %f0, %f0
 ; CHECK: br %r14
   %val = load fp128 *%ptr
@@ -24,7 +24,7 @@ define float @f2(fp128 *%ptr) {
 ; Make sure that we don't use %f0 as the destination of LEXBR when %f2
 ; is still live.
 define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lexbr %f1, %f1
 ; CHECK: aebr %f1, %f2
 ; CHECK: ste %f1, 0(%r2)
@@ -38,7 +38,7 @@ define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) {
 
 ; Test f128->f64.
 define double @f4(fp128 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldxbr %f0, %f0
 ; CHECK: br %r14
   %val = load fp128 *%ptr
@@ -48,7 +48,7 @@ define double @f4(fp128 *%ptr) {
 
 ; Like f3, but for f128->f64.
 define void @f5(double *%dst, fp128 *%ptr, double %d1, double %d2) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldxbr %f1, %f1
 ; CHECK: adbr %f1, %f2
 ; CHECK: std %f1, 0(%r2)
diff --git a/test/CodeGen/SystemZ/fp-conv-02.ll b/test/CodeGen/SystemZ/fp-conv-02.ll
index eb405da2dae..93fb7c8d4d9 100644
--- a/test/CodeGen/SystemZ/fp-conv-02.ll
+++ b/test/CodeGen/SystemZ/fp-conv-02.ll
@@ -4,7 +4,7 @@
 
 ; Check register extension.
 define double @f1(float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldebr %f0, %f0
 ; CHECK: br %r14
   %res = fpext float %val to double
@@ -13,7 +13,7 @@ define double @f1(float %val) {
 
 ; Check the low end of the LDEB range.
 define double @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load float *%ptr
@@ -23,7 +23,7 @@ define double @f2(float *%ptr) {
 
 ; Check the high end of the aligned LDEB range.
 define double @f3(float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -35,7 +35,7 @@ define double @f3(float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +47,7 @@ define double @f4(float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +59,7 @@ define double @f5(float *%base) {
 
 ; Check that LDEB allows indices.
 define double @f6(float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: ldeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -73,7 +73,7 @@ define double @f6(float *%base, i64 %index) {
 ; Test a case where we spill the source of at least one LDEBR.  We want
 ; to use LDEB if possible.
 define void @f7(double *%ptr1, float *%ptr2) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile float *%ptr2
diff --git a/test/CodeGen/SystemZ/fp-conv-03.ll b/test/CodeGen/SystemZ/fp-conv-03.ll
index 963653c8abf..d42ce6650aa 100644
--- a/test/CodeGen/SystemZ/fp-conv-03.ll
+++ b/test/CodeGen/SystemZ/fp-conv-03.ll
@@ -4,7 +4,7 @@
 
 ; Check register extension.
 define void @f1(fp128 *%dst, float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -16,7 +16,7 @@ define void @f1(fp128 *%dst, float %val) {
 
 ; Check the low end of the LXEB range.
 define void @f2(fp128 *%dst, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lxeb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -29,7 +29,7 @@ define void @f2(fp128 *%dst, float *%ptr) {
 
 ; Check the high end of the aligned LXEB range.
 define void @f3(fp128 *%dst, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lxeb %f0, 4092(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -44,7 +44,7 @@ define void @f3(fp128 *%dst, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(fp128 *%dst, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r3, 4096
 ; CHECK: lxeb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -59,7 +59,7 @@ define void @f4(fp128 *%dst, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f5(fp128 *%dst, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r3, -4
 ; CHECK: lxeb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -74,7 +74,7 @@ define void @f5(fp128 *%dst, float *%base) {
 
 ; Check that LXEB allows indices.
 define void @f6(fp128 *%dst, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r4, 2
 ; CHECK: lxeb %f0, 400(%r1,%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -91,7 +91,7 @@ define void @f6(fp128 *%dst, float *%base, i64 %index) {
 ; Test a case where we spill the source of at least one LXEBR.  We want
 ; to use LXEB if possible.
 define void @f7(fp128 *%ptr1, float *%ptr2) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lxeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile float *%ptr2
diff --git a/test/CodeGen/SystemZ/fp-conv-04.ll b/test/CodeGen/SystemZ/fp-conv-04.ll
index f8a66f8f13a..518d6c28d86 100644
--- a/test/CodeGen/SystemZ/fp-conv-04.ll
+++ b/test/CodeGen/SystemZ/fp-conv-04.ll
@@ -4,7 +4,7 @@
 
 ; Check register extension.
 define void @f1(fp128 *%dst, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxdbr %f0, %f0
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -16,7 +16,7 @@ define void @f1(fp128 *%dst, double %val) {
 
 ; Check the low end of the LXDB range.
 define void @f2(fp128 *%dst, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lxdb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -29,7 +29,7 @@ define void @f2(fp128 *%dst, double *%ptr) {
 
 ; Check the high end of the aligned LXDB range.
 define void @f3(fp128 *%dst, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lxdb %f0, 4088(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -44,7 +44,7 @@ define void @f3(fp128 *%dst, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(fp128 *%dst, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r3, 4096
 ; CHECK: lxdb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -59,7 +59,7 @@ define void @f4(fp128 *%dst, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f5(fp128 *%dst, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r3, -8
 ; CHECK: lxdb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -74,7 +74,7 @@ define void @f5(fp128 *%dst, double *%base) {
 
 ; Check that LXDB allows indices.
 define void @f6(fp128 *%dst, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r4, 3
 ; CHECK: lxdb %f0, 800(%r1,%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -91,7 +91,7 @@ define void @f6(fp128 *%dst, double *%base, i64 %index) {
 ; Test a case where we spill the source of at least one LXDBR.  We want
 ; to use LXDB if possible.
 define void @f7(fp128 *%ptr1, double *%ptr2) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lxdb {{%f[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
   %val0 = load volatile double *%ptr2
diff --git a/test/CodeGen/SystemZ/fp-conv-05.ll b/test/CodeGen/SystemZ/fp-conv-05.ll
index 2d887324c3e..deeffbf30c0 100644
--- a/test/CodeGen/SystemZ/fp-conv-05.ll
+++ b/test/CodeGen/SystemZ/fp-conv-05.ll
@@ -4,7 +4,7 @@
 
 ; Check i32->f32.
 define float @f1(i32 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cefbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i32 %i to float
@@ -13,7 +13,7 @@ define float @f1(i32 %i) {
 
 ; Check i32->f64.
 define double @f2(i32 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdfbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i32 %i to double
@@ -22,7 +22,7 @@ define double @f2(i32 %i) {
 
 ; Check i32->f128.
 define void @f3(i32 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxfbr %f0, %r2
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
diff --git a/test/CodeGen/SystemZ/fp-conv-06.ll b/test/CodeGen/SystemZ/fp-conv-06.ll
index 1b39b67d49b..466c1456a0c 100644
--- a/test/CodeGen/SystemZ/fp-conv-06.ll
+++ b/test/CodeGen/SystemZ/fp-conv-06.ll
@@ -5,7 +5,7 @@
 ; Check i32->f32.  There is no native instruction, so we must promote
 ; to i64 first.
 define float @f1(i32 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: cegbr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define float @f1(i32 %i) {
 
 ; Check i32->f64.
 define double @f2(i32 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: cdgbr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -25,7 +25,7 @@ define double @f2(i32 %i) {
 
 ; Check i32->f128.
 define void @f3(i32 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: cxgbr %f0, [[REGISTER]]
 ; CHECK: std %f0, 0(%r3)
diff --git a/test/CodeGen/SystemZ/fp-conv-07.ll b/test/CodeGen/SystemZ/fp-conv-07.ll
index 0ebbd37d512..aba5c4c0195 100644
--- a/test/CodeGen/SystemZ/fp-conv-07.ll
+++ b/test/CodeGen/SystemZ/fp-conv-07.ll
@@ -4,7 +4,7 @@
 
 ; Test i64->f32.
 define float @f1(i64 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cegbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i64 %i to float
@@ -13,7 +13,7 @@ define float @f1(i64 %i) {
 
 ; Test i64->f64.
 define double @f2(i64 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdgbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i64 %i to double
@@ -22,7 +22,7 @@ define double @f2(i64 %i) {
 
 ; Test i64->f128.
 define void @f3(i64 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxgbr %f0, %r2
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
diff --git a/test/CodeGen/SystemZ/fp-conv-08.ll b/test/CodeGen/SystemZ/fp-conv-08.ll
index 2cb97460a3e..69b2d13e29f 100644
--- a/test/CodeGen/SystemZ/fp-conv-08.ll
+++ b/test/CodeGen/SystemZ/fp-conv-08.ll
@@ -5,7 +5,7 @@
 ; Test i64->f32.  There's no native support for unsigned i64-to-fp conversions,
 ; but we should be able to implement them using signed i64-to-fp conversions.
 define float @f1(i64 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cegbr
 ; CHECK: aebr
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define float @f1(i64 %i) {
 
 ; Test i64->f64.
 define double @f2(i64 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldgr
 ; CHECK: adbr
 ; CHECK: br %r14
@@ -25,7 +25,7 @@ define double @f2(i64 %i) {
 
 ; Test i64->f128.
 define void @f3(i64 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxgbr
 ; CHECK: axbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-conv-09.ll b/test/CodeGen/SystemZ/fp-conv-09.ll
index e3c0352cf84..6aee73644a1 100644
--- a/test/CodeGen/SystemZ/fp-conv-09.ll
+++ b/test/CodeGen/SystemZ/fp-conv-09.ll
@@ -4,7 +4,7 @@
 
 ; Test f32->i32.
 define i32 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cfebr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi float %f to i32
@@ -13,7 +13,7 @@ define i32 @f1(float %f) {
 
 ; Test f64->i32.
 define i32 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cfdbr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi double %f to i32
@@ -22,7 +22,7 @@ define i32 @f2(double %f) {
 
 ; Test f128->i32.
 define i32 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: cfxbr %r2, 5, %f0
diff --git a/test/CodeGen/SystemZ/fp-conv-10.ll b/test/CodeGen/SystemZ/fp-conv-10.ll
index bb8878bacee..723d19d2a1d 100644
--- a/test/CodeGen/SystemZ/fp-conv-10.ll
+++ b/test/CodeGen/SystemZ/fp-conv-10.ll
@@ -9,7 +9,7 @@
 
 ; Test f32->i32.
 define i32 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cebr
 ; CHECK: sebr
 ; CHECK: cfebr
@@ -21,7 +21,7 @@ define i32 @f1(float %f) {
 
 ; Test f64->i32.
 define i32 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdbr
 ; CHECK: sdbr
 ; CHECK: cfdbr
@@ -33,7 +33,7 @@ define i32 @f2(double %f) {
 
 ; Test f128->i32.
 define i32 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxbr
 ; CHECK: sxbr
 ; CHECK: cfxbr
diff --git a/test/CodeGen/SystemZ/fp-conv-11.ll b/test/CodeGen/SystemZ/fp-conv-11.ll
index 2a36cb955cb..46f4cb3a6d8 100644
--- a/test/CodeGen/SystemZ/fp-conv-11.ll
+++ b/test/CodeGen/SystemZ/fp-conv-11.ll
@@ -4,7 +4,7 @@
 
 ; Test f32->i64.
 define i64 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgebr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi float %f to i64
@@ -13,7 +13,7 @@ define i64 @f1(float %f) {
 
 ; Test f64->i64.
 define i64 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgdbr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi double %f to i64
@@ -22,7 +22,7 @@ define i64 @f2(double %f) {
 
 ; Test f128->i64.
 define i64 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: cgxbr %r2, 5, %f0
diff --git a/test/CodeGen/SystemZ/fp-conv-12.ll b/test/CodeGen/SystemZ/fp-conv-12.ll
index 4445b14ee8e..6cc343abdaf 100644
--- a/test/CodeGen/SystemZ/fp-conv-12.ll
+++ b/test/CodeGen/SystemZ/fp-conv-12.ll
@@ -8,7 +8,7 @@
 
 ; Test f32->i64.
 define i64 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cebr
 ; CHECK: sebr
 ; CHECK: cgebr
@@ -20,7 +20,7 @@ define i64 @f1(float %f) {
 
 ; Test f64->i64.
 define i64 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdbr
 ; CHECK: sdbr
 ; CHECK: cgdbr
@@ -32,7 +32,7 @@ define i64 @f2(double %f) {
 
 ; Test f128->i64.
 define i64 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxbr
 ; CHECK: sxbr
 ; CHECK: cgxbr
diff --git a/test/CodeGen/SystemZ/fp-copysign-01.ll b/test/CodeGen/SystemZ/fp-copysign-01.ll
index 458d475bdf3..50177e5f41b 100644
--- a/test/CodeGen/SystemZ/fp-copysign-01.ll
+++ b/test/CodeGen/SystemZ/fp-copysign-01.ll
@@ -9,7 +9,7 @@ declare fp128 @copysignl(fp128, fp128) readnone
 
 ; Test f32 copies in which the sign comes from an f32.
 define float @f1(float %a, float %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define float @f1(float %a, float %b) {
 
 ; Test f32 copies in which the sign comes from an f64.
 define float @f2(float %a, double %bd) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define float @f2(float %a, double %bd) {
 
 ; Test f32 copies in which the sign comes from an f128.
 define float @f3(float %a, fp128 *%bptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2)
 ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
 ; CHECK: cpsdr %f0, %f0, [[BHIGH]]
@@ -43,7 +43,7 @@ define float @f3(float %a, fp128 *%bptr) {
 
 ; Test f64 copies in which the sign comes from an f32.
 define double @f4(double %a, float %bf) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define double @f4(double %a, float %bf) {
 
 ; Test f64 copies in which the sign comes from an f64.
 define double @f5(double %a, double %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ define double @f5(double %a, double %b) {
 
 ; Test f64 copies in which the sign comes from an f128.
 define double @f6(double %a, fp128 *%bptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2)
 ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
 ; CHECK: cpsdr %f0, %f0, [[BHIGH]]
@@ -79,7 +79,7 @@ define double @f6(double %a, fp128 *%bptr) {
 ; need any register shuffling here; %a should be tied to %c, with CPSDR
 ; just changing the high register.
 define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
 ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
 ; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0
@@ -95,7 +95,7 @@ define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
 
 ; As above, but the sign comes from an f64.
 define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
 ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
 ; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0
@@ -112,7 +112,7 @@ define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
 ; As above, but the sign comes from an f128.  Don't require the low part
 ; of %b to be loaded, since it isn't used.
 define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
 ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
 ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r4)
diff --git a/test/CodeGen/SystemZ/fp-div-01.ll b/test/CodeGen/SystemZ/fp-div-01.ll
index 3e581235395..1b99463327b 100644
--- a/test/CodeGen/SystemZ/fp-div-01.ll
+++ b/test/CodeGen/SystemZ/fp-div-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register division.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: debr %f0, %f2
 ; CHECK: br %r14
   %res = fdiv float %f1, %f2
@@ -15,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the DEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned DEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: deb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that DEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: deb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define float @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that divisions of spilled values can use DEB rather than DEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: deb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-div-02.ll b/test/CodeGen/SystemZ/fp-div-02.ll
index 31b1988b4c5..513664bd949 100644
--- a/test/CodeGen/SystemZ/fp-div-02.ll
+++ b/test/CodeGen/SystemZ/fp-div-02.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check register division.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ddbr %f0, %f2
 ; CHECK: br %r14
   %res = fdiv double %f1, %f2
@@ -15,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the DDB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned DDB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ddb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that DDB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: ddb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define double @f6(double %f1, double *%base, i64 %index) {
 
 ; Check that divisions of spilled values can use DDB rather than DDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ddb %f0, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-div-03.ll b/test/CodeGen/SystemZ/fp-div-03.ll
index 18f2d7449a8..079b349b408 100644
--- a/test/CodeGen/SystemZ/fp-div-03.ll
+++ b/test/CodeGen/SystemZ/fp-div-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit division.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-move-01.ll b/test/CodeGen/SystemZ/fp-move-01.ll
index 73cd978c597..d16502f2f7c 100644
--- a/test/CodeGen/SystemZ/fp-move-01.ll
+++ b/test/CodeGen/SystemZ/fp-move-01.ll
@@ -4,14 +4,14 @@
 
 ; Test f32 moves.
 define float @f1(float %a, float %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ler %f0, %f2
   ret float %b
 }
 
 ; Test f64 moves.
 define double @f2(double %a, double %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldr %f0, %f2
   ret double %b
 }
@@ -19,7 +19,7 @@ define double @f2(double %a, double %b) {
 ; Test f128 moves.  Since f128s are passed by reference, we need to force
 ; a copy by other means.
 define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lxr
 ; CHECK: axbr
   %val = load volatile fp128 *%x
diff --git a/test/CodeGen/SystemZ/fp-move-02.ll b/test/CodeGen/SystemZ/fp-move-02.ll
index 165d025e3bf..b6fc0d58337 100644
--- a/test/CodeGen/SystemZ/fp-move-02.ll
+++ b/test/CodeGen/SystemZ/fp-move-02.ll
@@ -10,7 +10,7 @@ declare double @bar()
 ; Test 32-bit moves from GPRs to FPRs.  The GPR must be moved into the high
 ; 32 bits of the FPR.
 define float @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 32
 ; CHECK: ldgr %f0, [[REGISTER]]
   %res = bitcast i32 %a to float
@@ -20,7 +20,7 @@ define float @f1(i32 %a) {
 ; Like f1, but create a situation where the shift can be folded with
 ; surrounding code.
 define float @f2(i64 %big) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 31
 ; CHECK: ldgr %f0, [[REGISTER]]
   %shift = lshr i64 %big, 1
@@ -31,7 +31,7 @@ define float @f2(i64 %big) {
 
 ; Another example of the same thing.
 define float @f3(i64 %big) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 2
 ; CHECK: ldgr %f0, [[REGISTER]]
   %shift = ashr i64 %big, 30
@@ -42,7 +42,7 @@ define float @f3(i64 %big) {
 
 ; Like f1, but the value to transfer is already in the high 32 bits.
 define float @f4(i64 %big) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: risbg [[REG:%r[0-5]]], %r2, 0, 159, 0
 ; CHECK-NOT: [[REG]]
@@ -55,7 +55,7 @@ define float @f4(i64 %big) {
 
 ; Test 64-bit moves from GPRs to FPRs.
 define double @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldgr %f0, %r2
   %res = bitcast i64 %a to double
   ret double %res
@@ -65,7 +65,7 @@ define double @f5(i64 %a) {
 ; so this goes through memory.
 ; FIXME: it would be better to use one MVC here.
 define void @f6(fp128 *%a, i128 *%b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lg
 ; CHECK: mvc
 ; CHECK: stg
@@ -79,7 +79,7 @@ define void @f6(fp128 *%a, i128 *%b) {
 ; Test 32-bit moves from FPRs to GPRs.  The high 32 bits of the FPR should
 ; be moved into the low 32 bits of the GPR.
 define i32 @f7(float %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgdr [[REGISTER:%r[0-5]]], %f0
 ; CHECK: srlg %r2, [[REGISTER]], 32
   %res = bitcast float %a to i32
@@ -88,7 +88,7 @@ define i32 @f7(float %a) {
 
 ; Test 64-bit moves from FPRs to GPRs.
 define i64 @f8(double %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lgdr %r2, %f0
   %res = bitcast double %a to i64
   ret i64 %res
@@ -96,7 +96,7 @@ define i64 @f8(double %a) {
 
 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
 define void @f9(fp128 *%a, i128 *%b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ld
 ; CHECK: ld
 ; CHECK: std
@@ -110,7 +110,7 @@ define void @f9(fp128 *%a, i128 *%b) {
 ; Test cases where the destination of an LGDR needs to be spilled.
 ; We shouldn't have any integer stack stores or floating-point loads.
 define void @f10(double %extra) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dptr
 ; CHECK-NOT: stg {{.*}}(%r15)
 ; CHECK: %loop
@@ -172,7 +172,7 @@ exit:
 
 ; ...likewise LDGR, with the requirements the other way around.
 define void @f11(i64 %mask) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: iptr
 ; CHECK-NOT: std {{.*}}(%r15)
 ; CHECK: %loop
@@ -235,7 +235,7 @@ exit:
 ; Test cases where the source of an LDGR needs to be spilled.
 ; We shouldn't have any integer stack stores or floating-point loads.
 define void @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: %loop
 ; CHECK-NOT: std {{.*}}(%r15)
 ; CHECK: %exit
@@ -314,7 +314,7 @@ exit:
 
 ; ...likewise LGDR, with the requirements the other way around.
 define void @f13() {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: %loop
 ; CHECK-NOT: stg {{.*}}(%r15)
 ; CHECK: %exit
diff --git a/test/CodeGen/SystemZ/fp-move-03.ll b/test/CodeGen/SystemZ/fp-move-03.ll
index 37dbdfad7b8..1273358f65a 100644
--- a/test/CodeGen/SystemZ/fp-move-03.ll
+++ b/test/CodeGen/SystemZ/fp-move-03.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the LE range.
 define float @f1(float *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load float *%src
@@ -13,7 +13,7 @@ define float @f1(float *%src) {
 
 ; Test the high end of the LE range.
 define float @f2(float *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: le %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1023
@@ -23,7 +23,7 @@ define float @f2(float *%src) {
 
 ; Check the next word up, which should use LEY instead of LE.
 define float @f3(float *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ley %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1024
@@ -33,7 +33,7 @@ define float @f3(float *%src) {
 
 ; Check the high end of the aligned LEY range.
 define float @f4(float *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ley %f0, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 131071
@@ -44,7 +44,7 @@ define float @f4(float *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f5(float *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define float @f5(float *%src) {
 
 ; Check the high end of the negative aligned LEY range.
 define float @f6(float *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ley %f0, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -1
@@ -65,7 +65,7 @@ define float @f6(float *%src) {
 
 ; Check the low end of the LEY range.
 define float @f7(float *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ley %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -131072
@@ -76,7 +76,7 @@ define float @f7(float *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f8(float *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define float @f8(float *%src) {
 
 ; Check that LE allows an index.
 define float @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: le %f0, 4092({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define float @f9(i64 %src, i64 %index) {
 
 ; Check that LEY allows an index.
 define float @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ley %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-04.ll b/test/CodeGen/SystemZ/fp-move-04.ll
index 72e90d1fffd..1b0278fdee0 100644
--- a/test/CodeGen/SystemZ/fp-move-04.ll
+++ b/test/CodeGen/SystemZ/fp-move-04.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the LD range.
 define double @f1(double *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load double *%src
@@ -13,7 +13,7 @@ define double @f1(double *%src) {
 
 ; Test the high end of the LD range.
 define double @f2(double *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ld %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 511
@@ -23,7 +23,7 @@ define double @f2(double *%src) {
 
 ; Check the next doubleword up, which should use LDY instead of LD.
 define double @f3(double *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldy %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 512
@@ -33,7 +33,7 @@ define double @f3(double *%src) {
 
 ; Check the high end of the aligned LDY range.
 define double @f4(double *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldy %f0, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 65535
@@ -44,7 +44,7 @@ define double @f4(double *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f5(double *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define double @f5(double *%src) {
 
 ; Check the high end of the negative aligned LDY range.
 define double @f6(double *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldy %f0, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -1
@@ -65,7 +65,7 @@ define double @f6(double *%src) {
 
 ; Check the low end of the LDY range.
 define double @f7(double *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldy %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -65536
@@ -76,7 +76,7 @@ define double @f7(double *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f8(double *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524296
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define double @f8(double *%src) {
 
 ; Check that LD allows an index.
 define double @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ld %f0, 4095({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define double @f9(i64 %src, i64 %index) {
 
 ; Check that LDY allows an index.
 define double @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ldy %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-05.ll b/test/CodeGen/SystemZ/fp-move-05.ll
index 66ad048fbed..d302a0f9c63 100644
--- a/test/CodeGen/SystemZ/fp-move-05.ll
+++ b/test/CodeGen/SystemZ/fp-move-05.ll
@@ -4,7 +4,7 @@
 
 ; Check loads with no offset.
 define double @f1(i64 %src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define double @f1(i64 %src) {
 
 ; Check the highest aligned offset that allows LD for both halves.
 define double @f2(i64 %src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ld %f0, 4080(%r2)
 ; CHECK: ld %f2, 4088(%r2)
 ; CHECK: br %r14
@@ -29,7 +29,7 @@ define double @f2(i64 %src) {
 
 ; Check the next doubleword up, which requires a mixture of LD and LDY.
 define double @f3(i64 %src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld %f0, 4088(%r2)
 ; CHECK: ldy %f2, 4096(%r2)
 ; CHECK: br %r14
@@ -42,7 +42,7 @@ define double @f3(i64 %src) {
 
 ; Check the next doubleword after that, which requires LDY for both halves.
 define double @f4(i64 %src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldy %f0, 4096(%r2)
 ; CHECK: ldy %f2, 4104(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define double @f4(i64 %src) {
 
 ; Check the highest aligned offset that allows LDY for both halves.
 define double @f5(i64 %src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldy %f0, 524272(%r2)
 ; CHECK: ldy %f2, 524280(%r2)
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(i64 %src) {
 ; Check the next doubleword up, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(i64 %src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lay %r1, 524280(%r2)
 ; CHECK: ld %f0, 0(%r1)
 ; CHECK: ld %f2, 8(%r1)
@@ -84,7 +84,7 @@ define double @f6(i64 %src) {
 ; Check the highest aligned negative offset, which needs a combination of
 ; LDY and LD.
 define double @f7(i64 %src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldy %f0, -8(%r2)
 ; CHECK: ld %f2, 0(%r2)
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define double @f7(i64 %src) {
 
 ; Check the next doubleword down, which requires LDY for both halves.
 define double @f8(i64 %src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ldy %f0, -16(%r2)
 ; CHECK: ldy %f2, -8(%r2)
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define double @f8(i64 %src) {
 
 ; Check the lowest offset that allows LDY for both halves.
 define double @f9(i64 %src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ldy %f0, -524288(%r2)
 ; CHECK: ldy %f2, -524280(%r2)
 ; CHECK: br %r14
@@ -124,7 +124,7 @@ define double @f9(i64 %src) {
 ; Check the next doubleword down, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f10(i64 %src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524296
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
@@ -138,7 +138,7 @@ define double @f10(i64 %src) {
 
 ; Check that indices are allowed.
 define double @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: ld %f0, 4088({{%r2,%r3|%r3,%r2}})
 ; CHECK: ldy %f2, 4096({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-move-06.ll b/test/CodeGen/SystemZ/fp-move-06.ll
index b660c2ac223..da67691729e 100644
--- a/test/CodeGen/SystemZ/fp-move-06.ll
+++ b/test/CodeGen/SystemZ/fp-move-06.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the STE range.
 define void @f1(float *%ptr, float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
   store float %val, float *%ptr
@@ -13,7 +13,7 @@ define void @f1(float *%ptr, float %val) {
 
 ; Test the high end of the STE range.
 define void @f2(float *%src, float %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ste %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1023
@@ -23,7 +23,7 @@ define void @f2(float *%src, float %val) {
 
 ; Check the next word up, which should use STEY instead of STE.
 define void @f3(float *%src, float %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stey %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1024
@@ -33,7 +33,7 @@ define void @f3(float *%src, float %val) {
 
 ; Check the high end of the aligned STEY range.
 define void @f4(float *%src, float %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stey %f0, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 131071
@@ -44,7 +44,7 @@ define void @f4(float *%src, float %val) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f5(float *%src, float %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f5(float *%src, float %val) {
 
 ; Check the high end of the negative aligned STEY range.
 define void @f6(float *%src, float %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stey %f0, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -1
@@ -65,7 +65,7 @@ define void @f6(float *%src, float %val) {
 
 ; Check the low end of the STEY range.
 define void @f7(float *%src, float %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stey %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -131072
@@ -76,7 +76,7 @@ define void @f7(float *%src, float %val) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(float *%src, float %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define void @f8(float *%src, float %val) {
 
 ; Check that STE allows an index.
 define void @f9(i64 %src, i64 %index, float %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ste %f0, 4092({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define void @f9(i64 %src, i64 %index, float %val) {
 
 ; Check that STEY allows an index.
 define void @f10(i64 %src, i64 %index, float %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: stey %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-07.ll b/test/CodeGen/SystemZ/fp-move-07.ll
index 0cb0474157d..a4f1820d120 100644
--- a/test/CodeGen/SystemZ/fp-move-07.ll
+++ b/test/CodeGen/SystemZ/fp-move-07.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the STD range.
 define void @f1(double *%src, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
   store double %val, double *%src
@@ -13,7 +13,7 @@ define void @f1(double *%src, double %val) {
 
 ; Test the high end of the STD range.
 define void @f2(double *%src, double %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: std %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 511
@@ -23,7 +23,7 @@ define void @f2(double *%src, double %val) {
 
 ; Check the next doubleword up, which should use STDY instead of STD.
 define void @f3(double *%src, double %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stdy %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 512
@@ -33,7 +33,7 @@ define void @f3(double *%src, double %val) {
 
 ; Check the high end of the aligned STDY range.
 define void @f4(double *%src, double %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stdy %f0, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 65535
@@ -44,7 +44,7 @@ define void @f4(double *%src, double %val) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f5(double *%src, double %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f5(double *%src, double %val) {
 
 ; Check the high end of the negative aligned STDY range.
 define void @f6(double *%src, double %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stdy %f0, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -1
@@ -65,7 +65,7 @@ define void @f6(double *%src, double %val) {
 
 ; Check the low end of the STDY range.
 define void @f7(double *%src, double %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stdy %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -65536
@@ -76,7 +76,7 @@ define void @f7(double *%src, double %val) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(double *%src, double %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524296
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define void @f8(double *%src, double %val) {
 
 ; Check that STD allows an index.
 define void @f9(i64 %src, i64 %index, double %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: std %f0, 4095({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define void @f9(i64 %src, i64 %index, double %val) {
 
 ; Check that STDY allows an index.
 define void @f10(i64 %src, i64 %index, double %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: stdy %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-08.ll b/test/CodeGen/SystemZ/fp-move-08.ll
index 448d2ace176..88038abc0da 100644
--- a/test/CodeGen/SystemZ/fp-move-08.ll
+++ b/test/CodeGen/SystemZ/fp-move-08.ll
@@ -4,7 +4,7 @@
 
 ; Check stores with no offset.
 define void @f1(i64 %src, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define void @f1(i64 %src, double %val) {
 
 ; Check the highest aligned offset that allows STD for both halves.
 define void @f2(i64 %src, double %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: std %f0, 4080(%r2)
 ; CHECK: std %f2, 4088(%r2)
 ; CHECK: br %r14
@@ -29,7 +29,7 @@ define void @f2(i64 %src, double %val) {
 
 ; Check the next doubleword up, which requires a mixture of STD and STDY.
 define void @f3(i64 %src, double %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: std %f0, 4088(%r2)
 ; CHECK: stdy %f2, 4096(%r2)
 ; CHECK: br %r14
@@ -42,7 +42,7 @@ define void @f3(i64 %src, double %val) {
 
 ; Check the next doubleword after that, which requires STDY for both halves.
 define void @f4(i64 %src, double %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stdy %f0, 4096(%r2)
 ; CHECK: stdy %f2, 4104(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f4(i64 %src, double %val) {
 
 ; Check the highest aligned offset that allows STDY for both halves.
 define void @f5(i64 %src, double %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stdy %f0, 524272(%r2)
 ; CHECK: stdy %f2, 524280(%r2)
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define void @f5(i64 %src, double %val) {
 ; Check the next doubleword up, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 %src, double %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lay %r1, 524280(%r2)
 ; CHECK: std %f0, 0(%r1)
 ; CHECK: std %f2, 8(%r1)
@@ -84,7 +84,7 @@ define void @f6(i64 %src, double %val) {
 ; Check the highest aligned negative offset, which needs a combination of
 ; STDY and STD.
 define void @f7(i64 %src, double %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stdy %f0, -8(%r2)
 ; CHECK: std %f2, 0(%r2)
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define void @f7(i64 %src, double %val) {
 
 ; Check the next doubleword down, which requires STDY for both halves.
 define void @f8(i64 %src, double %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: stdy %f0, -16(%r2)
 ; CHECK: stdy %f2, -8(%r2)
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define void @f8(i64 %src, double %val) {
 
 ; Check the lowest offset that allows STDY for both halves.
 define void @f9(i64 %src, double %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: stdy %f0, -524288(%r2)
 ; CHECK: stdy %f2, -524280(%r2)
 ; CHECK: br %r14
@@ -124,7 +124,7 @@ define void @f9(i64 %src, double %val) {
 ; Check the next doubleword down, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i64 %src, double %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524296
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -138,7 +138,7 @@ define void @f10(i64 %src, double %val) {
 
 ; Check that indices are allowed.
 define void @f11(i64 %src, i64 %index, double %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: std %f0, 4088({{%r2,%r3|%r3,%r2}})
 ; CHECK: stdy %f2, 4096({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-01.ll b/test/CodeGen/SystemZ/fp-mul-01.ll
index 3e6428a0a97..7562d6bf071 100644
--- a/test/CodeGen/SystemZ/fp-mul-01.ll
+++ b/test/CodeGen/SystemZ/fp-mul-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register multiplication.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: meebr %f0, %f2
 ; CHECK: br %r14
   %res = fmul float %f1, %f2
@@ -15,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the MEEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned MEEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: meeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that MEEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: meeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define float @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that multiplications of spilled values can use MEEB rather than MEEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: meeb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-02.ll b/test/CodeGen/SystemZ/fp-mul-02.ll
index 632638958e3..cf4448fd7dd 100644
--- a/test/CodeGen/SystemZ/fp-mul-02.ll
+++ b/test/CodeGen/SystemZ/fp-mul-02.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register multiplication.
 define double @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mdebr %f0, %f2
 ; CHECK: br %r14
   %f1x = fpext float %f1 to double
@@ -17,7 +17,7 @@ define double @f1(float %f1, float %f2) {
 
 ; Check the low end of the MDEB range.
 define double @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -29,7 +29,7 @@ define double @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned MDEB range.
 define double @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mdeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -43,7 +43,7 @@ define double @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -57,7 +57,7 @@ define double @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define double @f5(float %f1, float *%base) {
 
 ; Check that MDEB allows indices.
 define double @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mdeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -86,7 +86,7 @@ define double @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that multiplications of spilled values can use MDEB rather than MDEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mdeb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-03.ll b/test/CodeGen/SystemZ/fp-mul-03.ll
index 5c5d230eb40..6d296f07d1f 100644
--- a/test/CodeGen/SystemZ/fp-mul-03.ll
+++ b/test/CodeGen/SystemZ/fp-mul-03.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check register multiplication.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mdbr %f0, %f2
 ; CHECK: br %r14
   %res = fmul double %f1, %f2
@@ -15,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the MDB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned MDB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mdb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that MDB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: mdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define double @f6(double %f1, double *%base, i64 %index) {
 
 ; Check that multiplications of spilled values can use MDB rather than MDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mdb %f0, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-04.ll b/test/CodeGen/SystemZ/fp-mul-04.ll
index c7f734ff818..3c4325e6cbb 100644
--- a/test/CodeGen/SystemZ/fp-mul-04.ll
+++ b/test/CodeGen/SystemZ/fp-mul-04.ll
@@ -8,7 +8,7 @@ declare double @foo()
 ; point of view, because %f2 is the low register of the FP128 %f0.  Pass the
 ; multiplier in %f4 instead.
 define void @f1(double %f1, double %dummy, double %f2, fp128 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mxdbr %f0, %f4
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -22,7 +22,7 @@ define void @f1(double %f1, double %dummy, double %f2, fp128 *%dst) {
 
 ; Check the low end of the MXDB range.
 define void @f2(double %f1, double *%ptr, fp128 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mxdb %f0, 0(%r2)
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
@@ -37,7 +37,7 @@ define void @f2(double %f1, double *%ptr, fp128 *%dst) {
 
 ; Check the high end of the aligned MXDB range.
 define void @f3(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mxdb %f0, 4088(%r2)
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
@@ -54,7 +54,7 @@ define void @f3(double %f1, double *%base, fp128 *%dst) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mxdb %f0, 0(%r2)
 ; CHECK: std %f0, 0(%r3)
@@ -71,7 +71,7 @@ define void @f4(double %f1, double *%base, fp128 *%dst) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f5(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: mxdb %f0, 0(%r2)
 ; CHECK: std %f0, 0(%r3)
@@ -88,7 +88,7 @@ define void @f5(double %f1, double *%base, fp128 *%dst) {
 
 ; Check that MXDB allows indices.
 define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: mxdb %f0, 800(%r1,%r2)
 ; CHECK: std %f0, 0(%r4)
@@ -106,7 +106,7 @@ define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) {
 
 ; Check that multiplications of spilled values can use MXDB rather than MXDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mxdb %f0, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-05.ll b/test/CodeGen/SystemZ/fp-mul-05.ll
index df5bc4e7075..0be1fe8b41a 100644
--- a/test/CodeGen/SystemZ/fp-mul-05.ll
+++ b/test/CodeGen/SystemZ/fp-mul-05.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit multiplication.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-mul-06.ll b/test/CodeGen/SystemZ/fp-mul-06.ll
index 8124c680371..3f631a68b57 100644
--- a/test/CodeGen/SystemZ/fp-mul-06.ll
+++ b/test/CodeGen/SystemZ/fp-mul-06.ll
@@ -3,7 +3,7 @@
 declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
 
 define float @f1(float %f1, float %f2, float %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: maebr %f4, %f0, %f2
 ; CHECK: ler %f0, %f4
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define float @f1(float %f1, float %f2, float %acc) {
 }
 
 define float @f2(float %f1, float *%ptr, float %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define float @f2(float %f1, float *%ptr, float %acc) {
 }
 
 define float @f3(float %f1, float *%base, float %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: maeb %f2, %f0, 4092(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -36,7 +36,7 @@ define float @f4(float %f1, float *%base, float %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -51,7 +51,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -63,7 +63,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 }
 
 define float @f6(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: maeb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ler %f0, %f2
@@ -75,7 +75,7 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f7(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: maeb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}})
 ; CHECK: ler %f0, %f2
@@ -88,7 +88,7 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f8(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: maeb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-mul-07.ll b/test/CodeGen/SystemZ/fp-mul-07.ll
index b8e44830f33..e4f59044721 100644
--- a/test/CodeGen/SystemZ/fp-mul-07.ll
+++ b/test/CodeGen/SystemZ/fp-mul-07.ll
@@ -3,7 +3,7 @@
 declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
 
 define double @f1(double %f1, double %f2, double %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: madbr %f4, %f0, %f2
 ; CHECK: ldr %f0, %f4
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define double @f1(double %f1, double %f2, double %acc) {
 }
 
 define double @f2(double %f1, double *%ptr, double %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define double @f2(double %f1, double *%ptr, double %acc) {
 }
 
 define double @f3(double %f1, double *%base, double %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: madb %f2, %f0, 4088(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -36,7 +36,7 @@ define double @f4(double %f1, double *%base, double %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -51,7 +51,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -63,7 +63,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 }
 
 define double @f6(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: madb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ldr %f0, %f2
@@ -75,7 +75,7 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f7(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: madb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}})
 ; CHECK: ldr %f0, %f2
@@ -88,7 +88,7 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f8(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: madb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-mul-08.ll b/test/CodeGen/SystemZ/fp-mul-08.ll
index 5c1474063a1..ab5fcb2cbef 100644
--- a/test/CodeGen/SystemZ/fp-mul-08.ll
+++ b/test/CodeGen/SystemZ/fp-mul-08.ll
@@ -3,7 +3,7 @@
 declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
 
 define float @f1(float %f1, float %f2, float %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msebr %f4, %f0, %f2
 ; CHECK: ler %f0, %f4
 ; CHECK: br %r14
@@ -13,7 +13,7 @@ define float @f1(float %f1, float %f2, float %acc) {
 }
 
 define float @f2(float %f1, float *%ptr, float %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -24,7 +24,7 @@ define float @f2(float %f1, float *%ptr, float %acc) {
 }
 
 define float @f3(float %f1, float *%base, float %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mseb %f2, %f0, 4092(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define float @f4(float %f1, float *%base, float %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -55,7 +55,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -68,7 +68,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 }
 
 define float @f6(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mseb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ler %f0, %f2
@@ -81,7 +81,7 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f7(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mseb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}})
 ; CHECK: ler %f0, %f2
@@ -95,7 +95,7 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f8(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: mseb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-mul-09.ll b/test/CodeGen/SystemZ/fp-mul-09.ll
index bcae1e35e6e..7e740968a8c 100644
--- a/test/CodeGen/SystemZ/fp-mul-09.ll
+++ b/test/CodeGen/SystemZ/fp-mul-09.ll
@@ -3,7 +3,7 @@
 declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
 
 define double @f1(double %f1, double %f2, double %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msdbr %f4, %f0, %f2
 ; CHECK: ldr %f0, %f4
 ; CHECK: br %r14
@@ -13,7 +13,7 @@ define double @f1(double %f1, double %f2, double %acc) {
 }
 
 define double @f2(double %f1, double *%ptr, double %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -24,7 +24,7 @@ define double @f2(double %f1, double *%ptr, double %acc) {
 }
 
 define double @f3(double %f1, double *%base, double %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msdb %f2, %f0, 4088(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define double @f4(double %f1, double *%base, double %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -55,7 +55,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -68,7 +68,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 }
 
 define double @f6(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: msdb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ldr %f0, %f2
@@ -81,7 +81,7 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f7(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: msdb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}})
 ; CHECK: ldr %f0, %f2
@@ -95,7 +95,7 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f8(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: msdb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-neg-01.ll b/test/CodeGen/SystemZ/fp-neg-01.ll
index 09a4a53e41d..1cc6d816fee 100644
--- a/test/CodeGen/SystemZ/fp-neg-01.ll
+++ b/test/CodeGen/SystemZ/fp-neg-01.ll
@@ -4,7 +4,7 @@
 
 ; Test f32.
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lcebr %f0, %f0
 ; CHECK: br %r14
   %res = fsub float -0.0, %f
@@ -13,7 +13,7 @@ define float @f1(float %f) {
 
 ; Test f64.
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lcdbr %f0, %f0
 ; CHECK: br %r14
   %res = fsub double -0.0, %f
@@ -24,7 +24,7 @@ define double @f2(double %f) {
 ; be better implemented using an XI on the upper byte.  Do some extra
 ; processing so that using FPRs is unequivocally better.
 define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lcxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-round-01.ll b/test/CodeGen/SystemZ/fp-round-01.ll
index 20325c33664..f2530dc60d5 100644
--- a/test/CodeGen/SystemZ/fp-round-01.ll
+++ b/test/CodeGen/SystemZ/fp-round-01.ll
@@ -6,7 +6,7 @@
 ; Test f32.
 declare float @llvm.rint.f32(float %f)
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: fiebr %f0, 0, %f0
 ; CHECK: br %r14
   %res = call float @llvm.rint.f32(float %f)
@@ -16,7 +16,7 @@ define float @f1(float %f) {
 ; Test f64.
 declare double @llvm.rint.f64(double %f)
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: fidbr %f0, 0, %f0
 ; CHECK: br %r14
   %res = call double @llvm.rint.f64(double %f)
@@ -26,7 +26,7 @@ define double @f2(double %f) {
 ; Test f128.
 declare fp128 @llvm.rint.f128(fp128 %f)
 define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: fixbr %f0, 0, %f0
 ; CHECK: br %r14
   %src = load fp128 *%ptr
diff --git a/test/CodeGen/SystemZ/fp-sqrt-01.ll b/test/CodeGen/SystemZ/fp-sqrt-01.ll
index faba390ea59..b6568d6f01c 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-01.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-01.ll
@@ -6,7 +6,7 @@ declare float @llvm.sqrt.f32(float %f)
 
 ; Check register square root.
 define float @f1(float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sqebr %f0, %f0
 ; CHECK: br %r14
   %res = call float @llvm.sqrt.f32(float %val)
@@ -15,7 +15,7 @@ define float @f1(float %val) {
 
 ; Check the low end of the SQEB range.
 define float @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float *%ptr) {
 
 ; Check the high end of the aligned SQEB range.
 define float @f3(float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sqeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float *%base) {
 
 ; Check that SQEB allows indices.
 define float @f6(float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: sqeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define float @f6(float *%base, i64 %index) {
 ; Test a case where we spill the source of at least one SQEBR.  We want
 ; to use SQEB if possible.
 define void @f7(float *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sqeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile float *%ptr
diff --git a/test/CodeGen/SystemZ/fp-sqrt-02.ll b/test/CodeGen/SystemZ/fp-sqrt-02.ll
index e90f7a369e9..b07a2c66fb4 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-02.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-02.ll
@@ -6,7 +6,7 @@ declare double @llvm.sqrt.f64(double %f)
 
 ; Check register square root.
 define double @f1(double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sqdbr %f0, %f0
 ; CHECK: br %r14
   %res = call double @llvm.sqrt.f64(double %val)
@@ -15,7 +15,7 @@ define double @f1(double %val) {
 
 ; Check the low end of the SQDB range.
 define double @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double *%ptr) {
 
 ; Check the high end of the aligned SQDB range.
 define double @f3(double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sqdb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double *%base) {
 
 ; Check that SQDB allows indices.
 define double @f6(double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: sqdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define double @f6(double *%base, i64 %index) {
 ; Test a case where we spill the source of at least one SQDBR.  We want
 ; to use SQDB if possible.
 define void @f7(double *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sqdb {{%f[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
   %val0 = load volatile double *%ptr
diff --git a/test/CodeGen/SystemZ/fp-sqrt-03.ll b/test/CodeGen/SystemZ/fp-sqrt-03.ll
index 1b49af41254..71426440aca 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-03.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-03.ll
@@ -6,7 +6,7 @@ declare fp128 @llvm.sqrt.f128(fp128 %f)
 
 ; There's no memory form of SQXBR.
 define void @f1(fp128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: sqxbr %f0, %f0
diff --git a/test/CodeGen/SystemZ/fp-sub-01.ll b/test/CodeGen/SystemZ/fp-sub-01.ll
index 88ce7fb440e..76f46f62670 100644
--- a/test/CodeGen/SystemZ/fp-sub-01.ll
+++ b/test/CodeGen/SystemZ/fp-sub-01.ll
@@ -6,7 +6,7 @@ declare float @foo()
 
 ; Check register subtraction.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sebr %f0, %f2
 ; CHECK: br %r14
   %res = fsub float %f1, %f2
@@ -15,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the SEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned SEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: seb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that SEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: seb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define float @f6(float %f1, float *%base, i64 %index) {
 
 ; Check that subtractions of spilled values can use SEB rather than SEBR.
 define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: seb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-sub-02.ll b/test/CodeGen/SystemZ/fp-sub-02.ll
index b6409fcd6ee..99cafed8d08 100644
--- a/test/CodeGen/SystemZ/fp-sub-02.ll
+++ b/test/CodeGen/SystemZ/fp-sub-02.ll
@@ -6,7 +6,7 @@ declare double @foo()
 
 ; Check register subtraction.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sdbr %f0, %f2
 ; CHECK: br %r14
   %res = fsub double %f1, %f2
@@ -15,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the SDB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned SDB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sdb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that SDB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: sdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define double @f6(double %f1, double *%base, i64 %index) {
 
 ; Check that subtractions of spilled values can use SDB rather than SDBR.
 define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: sdb %f0, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-sub-03.ll b/test/CodeGen/SystemZ/fp-sub-03.ll
index 82bb94dd28b..a1404c4ff0e 100644
--- a/test/CodeGen/SystemZ/fp-sub-03.ll
+++ b/test/CodeGen/SystemZ/fp-sub-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit subtraction.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/frame-01.ll b/test/CodeGen/SystemZ/frame-01.ll
index ad1ee533724..f61836ca855 100644
--- a/test/CodeGen/SystemZ/frame-01.ll
+++ b/test/CodeGen/SystemZ/frame-01.ll
@@ -7,7 +7,7 @@ declare void @foo(i32 *)
 
 ; The CFA offset is 160 (the caller-allocated part of the frame) + 168.
 define void @f1(i64 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -168
 ; CHECK: .cfi_def_cfa_offset 328
 ; CHECK: stg %r2, 160(%r15)
@@ -24,7 +24,7 @@ define void @f1(i64 %x) {
 ; 12-bit offsets that end up being out of range.  Fill the remaining
 ; 32760 - 176 bytes by allocating (32760 - 176) / 8 = 4073 doublewords.
 define void @f2(i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -32760
 ; CHECK: .cfi_def_cfa_offset 32920
 ; CHECK: stg %r2, 176(%r15)
@@ -39,7 +39,7 @@ define void @f2(i64 %x) {
 ; Allocate one more doubleword.  This is the one frame size that we can
 ; allocate using AGHI but must free using AGFI.
 define void @f3(i64 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -32768
 ; CHECK: .cfi_def_cfa_offset 32928
 ; CHECK: stg %r2, 176(%r15)
@@ -54,7 +54,7 @@ define void @f3(i64 %x) {
 ; Allocate another doubleword on top of that.  The allocation and free
 ; must both use AGFI.
 define void @f4(i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r15, -32776
 ; CHECK: .cfi_def_cfa_offset 32936
 ; CHECK: stg %r2, 176(%r15)
@@ -69,7 +69,7 @@ define void @f4(i64 %x) {
 ; The largest size that can be both allocated and freed using AGFI.
 ; At this point the frame is too big to represent properly in the CFI.
 define void @f5(i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r15, -2147483640
 ; CHECK: stg %r2, 176(%r15)
 ; CHECK: agfi %r15, 2147483640
@@ -83,7 +83,7 @@ define void @f5(i64 %x) {
 ; The only frame size that can be allocated using a single AGFI but which
 ; must be freed using two instructions.
 define void @f6(i64 %x) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r15, -2147483648
 ; CHECK: stg %r2, 176(%r15)
 ; CHECK: agfi %r15, 2147483640
@@ -98,7 +98,7 @@ define void @f6(i64 %x) {
 ; The smallest frame size that needs two instructions to both allocate
 ; and free the frame.
 define void @f7(i64 %x) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r15, -2147483648
 ; CHECK: aghi %r15, -8
 ; CHECK: stg %r2, 176(%r15)
@@ -113,7 +113,7 @@ define void @f7(i64 %x) {
 
 ; Make sure that LA can be rematerialized.
 define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: la %r2, 164(%r15)
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: la %r2, 164(%r15)
diff --git a/test/CodeGen/SystemZ/frame-02.ll b/test/CodeGen/SystemZ/frame-02.ll
index 589703ec0e7..9a7f8eac9eb 100644
--- a/test/CodeGen/SystemZ/frame-02.ll
+++ b/test/CodeGen/SystemZ/frame-02.ll
@@ -7,7 +7,7 @@
 ; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
 ; (the caller-allocated part of the frame) + 224.
 define void @f1(float *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -224
 ; CHECK: .cfi_def_cfa_offset 384
 ; CHECK: std %f8, 216(%r15)
@@ -91,7 +91,7 @@ define void @f1(float *%ptr) {
 ; Like f1, but requires one fewer FPR.  We allocate in numerical order,
 ; so %f15 is the one that gets dropped.
 define void @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -216
 ; CHECK: .cfi_def_cfa_offset 376
 ; CHECK: std %f8, 208(%r15)
@@ -169,7 +169,7 @@ define void @f2(float *%ptr) {
 
 ; Like f1, but should require only one call-saved FPR.
 define void @f3(float *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -168
 ; CHECK: .cfi_def_cfa_offset 328
 ; CHECK: std %f8, 160(%r15)
@@ -218,7 +218,7 @@ define void @f3(float *%ptr) {
 ; This function should use all call-clobbered FPRs but no call-saved ones.
 ; It shouldn't need to create a frame.
 define void @f4(float *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %f8
 ; CHECK-NOT: %f9
diff --git a/test/CodeGen/SystemZ/frame-03.ll b/test/CodeGen/SystemZ/frame-03.ll
index 3c4a49977a1..db146c7c985 100644
--- a/test/CodeGen/SystemZ/frame-03.ll
+++ b/test/CodeGen/SystemZ/frame-03.ll
@@ -9,7 +9,7 @@
 ; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
 ; (the caller-allocated part of the frame) + 224.
 define void @f1(double *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -224
 ; CHECK: .cfi_def_cfa_offset 384
 ; CHECK: std %f8, 216(%r15)
@@ -93,7 +93,7 @@ define void @f1(double *%ptr) {
 ; Like f1, but requires one fewer FPR.  We allocate in numerical order,
 ; so %f15 is the one that gets dropped.
 define void @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -216
 ; CHECK: .cfi_def_cfa_offset 376
 ; CHECK: std %f8, 208(%r15)
@@ -171,7 +171,7 @@ define void @f2(double *%ptr) {
 
 ; Like f1, but should require only one call-saved FPR.
 define void @f3(double *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -168
 ; CHECK: .cfi_def_cfa_offset 328
 ; CHECK: std %f8, 160(%r15)
@@ -220,7 +220,7 @@ define void @f3(double *%ptr) {
 ; This function should use all call-clobbered FPRs but no call-saved ones.
 ; It shouldn't need to create a frame.
 define void @f4(double *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %f8
 ; CHECK-NOT: %f9
diff --git a/test/CodeGen/SystemZ/frame-04.ll b/test/CodeGen/SystemZ/frame-04.ll
index 360f85cde32..93c59a3bc15 100644
--- a/test/CodeGen/SystemZ/frame-04.ll
+++ b/test/CodeGen/SystemZ/frame-04.ll
@@ -8,7 +8,7 @@
 ; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
 ; (the caller-allocated part of the frame) + 224.
 define void @f1(fp128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -224
 ; CHECK: .cfi_def_cfa_offset 384
 ; CHECK: std %f8, 216(%r15)
@@ -68,7 +68,7 @@ define void @f1(fp128 *%ptr) {
 ; Like f1, but requires one fewer FPR pair.  We allocate in numerical order,
 ; so %f13+%f15 is the pair that gets dropped.
 define void @f2(fp128 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -208
 ; CHECK: .cfi_def_cfa_offset 368
 ; CHECK: std %f8, 200(%r15)
@@ -121,7 +121,7 @@ define void @f2(fp128 *%ptr) {
 ; Like f1, but requires only one call-saved FPR pair.  We allocate in
 ; numerical order so the pair should be %f8+%f10.
 define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -176
 ; CHECK: .cfi_def_cfa_offset 336
 ; CHECK: std %f8, 168(%r15)
@@ -160,7 +160,7 @@ define void @f3(fp128 *%ptr) {
 ; This function should use all call-clobbered FPRs but no call-saved ones.
 ; It shouldn't need to create a frame.
 define void @f4(fp128 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %f8
 ; CHECK-NOT: %f9
diff --git a/test/CodeGen/SystemZ/frame-05.ll b/test/CodeGen/SystemZ/frame-05.ll
index 3a159fcd594..f95284deeb7 100644
--- a/test/CodeGen/SystemZ/frame-05.ll
+++ b/test/CodeGen/SystemZ/frame-05.ll
@@ -14,7 +14,7 @@
 ; Use a different address for the final store, so that we can check that
 ; %r15 isn't referenced again until after that.
 define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r6, -112
@@ -82,7 +82,7 @@ define void @f1(i32 *%ptr) {
 ; from %r14 down, so that the STMG/LMG sequences aren't any longer than
 ; they need to be.
 define void @f2(i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r7, %r15, 56(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r7, -104
@@ -145,7 +145,7 @@ define void @f2(i32 *%ptr) {
 
 ; Like f1, but only needs one call-saved GPR, which ought to be %r14.
 define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r14, -48
@@ -188,7 +188,7 @@ define void @f3(i32 *%ptr) {
 ; This function should use all call-clobbered GPRs but no call-saved ones.
 ; It shouldn't need to touch the stack at all.
 define void @f4(i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %r6
 ; CHECK-NOT: %r7
diff --git a/test/CodeGen/SystemZ/frame-06.ll b/test/CodeGen/SystemZ/frame-06.ll
index 4c361f1e9fc..ad22f10903a 100644
--- a/test/CodeGen/SystemZ/frame-06.ll
+++ b/test/CodeGen/SystemZ/frame-06.ll
@@ -11,7 +11,7 @@
 ; Use a different address for the final store, so that we can check that
 ; %r15 isn't referenced again until after that.
 define void @f1(i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r6, -112
@@ -79,7 +79,7 @@ define void @f1(i64 *%ptr) {
 ; from %r14 down, so that the STMG/LMG sequences aren't any longer than
 ; they need to be.
 define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r7, %r15, 56(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r7, -104
@@ -142,7 +142,7 @@ define void @f2(i64 *%ptr) {
 
 ; Like f1, but only needs one call-saved GPR, which ought to be %r14.
 define void @f3(i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r14, -48
@@ -185,7 +185,7 @@ define void @f3(i64 *%ptr) {
 ; This function should use all call-clobbered GPRs but no call-saved ones.
 ; It shouldn't need to touch the stack at all.
 define void @f4(i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %r6
 ; CHECK-NOT: %r7
diff --git a/test/CodeGen/SystemZ/frame-07.ll b/test/CodeGen/SystemZ/frame-07.ll
index b5999ae5e3b..eab313744b9 100644
--- a/test/CodeGen/SystemZ/frame-07.ll
+++ b/test/CodeGen/SystemZ/frame-07.ll
@@ -9,7 +9,7 @@
 ; as well as the 8 FPR save slots.  Get a frame of size 4128 by allocating
 ; (4128 - 176 - 8 * 8) / 8 = 486 extra doublewords.
 define void @f1(double *%ptr, i64 %x) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: aghi %r15, -4128
 ; CHECK-NOFP: .cfi_def_cfa_offset 4288
 ; CHECK-NOFP: stdy %f8, 4120(%r15)
@@ -40,7 +40,7 @@ define void @f1(double *%ptr, i64 %x) {
 ; CHECK-NOFP: aghi %r15, 4128
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: stmg %r11, %r15, 88(%r15)
 ; CHECK-FP: aghi %r15, -4128
 ; CHECK-FP: .cfi_def_cfa_offset 4288
@@ -129,7 +129,7 @@ define void @f1(double *%ptr, i64 %x) {
 ; As above, get a frame of size 524320 by allocating
 ; (524320 - 176 - 8 * 8) / 8 = 65510 extra doublewords.
 define void @f2(double *%ptr, i64 %x) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: agfi %r15, -524320
 ; CHECK-NOFP: .cfi_def_cfa_offset 524480
 ; CHECK-NOFP: llilh [[INDEX:%r[1-5]]], 8
@@ -161,7 +161,7 @@ define void @f2(double *%ptr, i64 %x) {
 ; CHECK-NOFP: agfi %r15, 524320
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: stmg %r11, %r15, 88(%r15)
 ; CHECK-FP: agfi %r15, -524320
 ; CHECK-FP: .cfi_def_cfa_offset 524480
diff --git a/test/CodeGen/SystemZ/frame-08.ll b/test/CodeGen/SystemZ/frame-08.ll
index 8db4dd33e1b..da2a6142fb4 100644
--- a/test/CodeGen/SystemZ/frame-08.ll
+++ b/test/CodeGen/SystemZ/frame-08.ll
@@ -7,7 +7,7 @@
 ; so get a frame of size 524232 by allocating (524232 - 176) / 8 = 65507
 ; extra doublewords.
 define void @f1(i32 *%ptr, i64 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: .cfi_offset %r6, -112
 ; CHECK: .cfi_offset %r7, -104
@@ -75,7 +75,7 @@ define void @f1(i32 *%ptr, i64 %x) {
 ; so get a frame of size 524168 by allocating (524168 - 176) / 8 = 65499
 ; extra doublewords.
 define void @f2(i32 *%ptr, i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -110,7 +110,7 @@ define void @f2(i32 *%ptr, i64 %x) {
 ; frame size that needs two instructions to perform the final LMG for
 ; %r6 and above.
 define void @f3(i32 *%ptr, i64 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: .cfi_offset %r6, -112
 ; CHECK: .cfi_offset %r7, -104
@@ -177,7 +177,7 @@ define void @f3(i32 *%ptr, i64 %x) {
 ; frame size that needs two instructions to perform the final LMG for
 ; %r14 and %r15.
 define void @f4(i32 *%ptr, i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -211,7 +211,7 @@ define void @f4(i32 *%ptr, i64 %x) {
 ; This is the largest frame size for which the prepatory increment for
 ; "lmg %r14, %r15, ..." can be done using AGHI.
 define void @f5(i32 *%ptr, i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -245,7 +245,7 @@ define void @f5(i32 *%ptr, i64 %x) {
 ; This is the smallest frame size for which the prepatory increment for
 ; "lmg %r14, %r15, ..." needs to be done using AGFI.
 define void @f6(i32 *%ptr, i64 %x) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
diff --git a/test/CodeGen/SystemZ/frame-09.ll b/test/CodeGen/SystemZ/frame-09.ll
index 6b6341a7d11..8a4f99c343a 100644
--- a/test/CodeGen/SystemZ/frame-09.ll
+++ b/test/CodeGen/SystemZ/frame-09.ll
@@ -6,7 +6,7 @@
 ; We don't need to allocate any more than the caller-provided 160-byte
 ; area though.
 define i32 @f1(i32 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -22,7 +22,7 @@ define i32 @f1(i32 %x) {
 ; Make sure that frame accesses after the initial allocation are relative
 ; to %r11 rather than %r15.
 define void @f2(i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -41,7 +41,7 @@ define void @f2(i64 %x) {
 ; This function should require all GPRs but no other spill slots.
 ; It shouldn't need to allocate its own frame.
 define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %r11
@@ -111,7 +111,7 @@ define void @f3(i32 *%ptr) {
 ; emergency spill slots at 160(%r11), so create a frame of size 524192
 ; by allocating (524192 - 176) / 8 = 65502 doublewords.
 define void @f4(i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -131,7 +131,7 @@ define void @f4(i64 %x) {
 
 ; The next frame size larger than f4.
 define void @f5(i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
diff --git a/test/CodeGen/SystemZ/frame-10.ll b/test/CodeGen/SystemZ/frame-10.ll
index 399a4125933..b96973a9cb9 100644
--- a/test/CodeGen/SystemZ/frame-10.ll
+++ b/test/CodeGen/SystemZ/frame-10.ll
@@ -5,7 +5,7 @@
 declare i8 *@llvm.stacksave()
 
 define void @f1(i8 **%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stg %r15, 0(%r2)
 ; CHECK: br %r14
   %addr = call i8 *@llvm.stacksave()
diff --git a/test/CodeGen/SystemZ/frame-11.ll b/test/CodeGen/SystemZ/frame-11.ll
index 84222056e6d..5145b4d1c86 100644
--- a/test/CodeGen/SystemZ/frame-11.ll
+++ b/test/CodeGen/SystemZ/frame-11.ll
@@ -7,7 +7,7 @@ declare void @llvm.stackrestore(i8 *)
 ; we should use a frame pointer and tear down the frame based on %r11
 ; rather than %r15.
 define void @f1(i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: lgr %r11, %r15
 ; CHECK: lgr %r15, %r2
diff --git a/test/CodeGen/SystemZ/frame-13.ll b/test/CodeGen/SystemZ/frame-13.ll
index 75793a032be..1d383542694 100644
--- a/test/CodeGen/SystemZ/frame-13.ll
+++ b/test/CodeGen/SystemZ/frame-13.ll
@@ -22,11 +22,11 @@
 ; in order to put another object at offset 4088 is (4088 - 176) / 4 = 978
 ; words.
 define void @f1() {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: mvhi 4092(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: mvhi 4092(%r11), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x i32], align 8
@@ -40,12 +40,12 @@ define void @f1() {
 
 ; Test the first out-of-range offset.  We cannot use an index register here.
 define void @f2() {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: mvhi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: mvhi 0(%r1), 42
 ; CHECK-FP: br %r14
@@ -60,12 +60,12 @@ define void @f2() {
 
 ; Test the next offset after that.
 define void @f3() {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: mvhi 4(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: mvhi 4(%r1), 42
 ; CHECK-FP: br %r14
@@ -80,12 +80,12 @@ define void @f3() {
 
 ; Add 4096 bytes (1024 words) to the size of each object and repeat.
 define void @f4() {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: mvhi 4092(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: mvhi 4092(%r1), 42
 ; CHECK-FP: br %r14
@@ -100,12 +100,12 @@ define void @f4() {
 
 ; ...as above.
 define void @f5() {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: lay %r1, 8192(%r15)
 ; CHECK-NOFP: mvhi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: lay %r1, 8192(%r11)
 ; CHECK-FP: mvhi 0(%r1), 42
 ; CHECK-FP: br %r14
@@ -120,12 +120,12 @@ define void @f5() {
 
 ; ...as above.
 define void @f6() {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: lay %r1, 8192(%r15)
 ; CHECK-NOFP: mvhi 4(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: lay %r1, 8192(%r11)
 ; CHECK-FP: mvhi 4(%r1), 42
 ; CHECK-FP: br %r14
@@ -142,12 +142,12 @@ define void @f6() {
 ; being at offset 8192.  This time we need objects of (8192 - 176) / 4 = 2004
 ; words.
 define void @f7() {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: lay %r1, 8192(%r15)
 ; CHECK-NOFP: mvhi 4092(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: lay %r1, 8192(%r11)
 ; CHECK-FP: mvhi 4092(%r1), 42
 ; CHECK-FP: br %r14
@@ -163,12 +163,12 @@ define void @f7() {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8() {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: lay %r1, 12288(%r15)
 ; CHECK-NOFP: mvhi 4(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: lay %r1, 12288(%r11)
 ; CHECK-FP: mvhi 4(%r1), 42
 ; CHECK-FP: br %r14
@@ -185,12 +185,12 @@ define void @f8() {
 ; should force an LAY from the outset.  We don't yet do any kind of anchor
 ; optimization, so there should be no offset on the MVHI itself.
 define void @f9() {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: lay %r1, 12296(%r15)
 ; CHECK-NOFP: mvhi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: lay %r1, 12296(%r11)
 ; CHECK-FP: mvhi 0(%r1), 42
 ; CHECK-FP: br %r14
@@ -207,14 +207,14 @@ define void @f9() {
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
 ; CHECK-NOFP: mvhi 0([[REGISTER]]), 42
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: lay [[REGISTER]], 4096(%r11)
 ; CHECK-FP: mvhi 0([[REGISTER]]), 42
@@ -244,7 +244,7 @@ define void @f10(i32 *%vptr) {
 ; However, the FP case uses %r11 as the frame pointer and must therefore
 ; spill a second register.  This leads to an extra displacement of 8.
 define void @f11(i32 *%vptr) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
@@ -253,7 +253,7 @@ define void @f11(i32 *%vptr) {
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: stmg %r6, %r15,
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: lay [[REGISTER]], 4096(%r11)
diff --git a/test/CodeGen/SystemZ/frame-14.ll b/test/CodeGen/SystemZ/frame-14.ll
index 29fab98604e..22a45eecf30 100644
--- a/test/CodeGen/SystemZ/frame-14.ll
+++ b/test/CodeGen/SystemZ/frame-14.ll
@@ -20,11 +20,11 @@
 ; emergency spill slots at 160(%r15), the amount that we need to allocate
 ; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.
 define void @f1() {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: mvi 4095(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: mvi 4095(%r11), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
@@ -38,11 +38,11 @@ define void @f1() {
 
 ; Test the first offset that is out-of-range of the 12-bit form.
 define void @f2() {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: mviy 4096(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: mviy 4096(%r11), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
@@ -59,11 +59,11 @@ define void @f2() {
 ; The last in-range doubleword offset is 524280, so by the same reasoning
 ; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.
 define void @f3() {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: mviy 524287(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: mviy 524287(%r11), 42
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
@@ -79,13 +79,13 @@ define void @f3() {
 ; and the offset is also out of LAY's range, so expect a constant load
 ; followed by an addition.
 define void @f4() {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mvi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mvi 0(%r1), 42
@@ -102,13 +102,13 @@ define void @f4() {
 ; Add 4095 to the previous offset, to test the other end of the MVI range.
 ; The instruction will actually be STCY before frame lowering.
 define void @f5() {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mvi 4095(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mvi 4095(%r1), 42
@@ -124,13 +124,13 @@ define void @f5() {
 
 ; Test the next offset after that, which uses MVIY instead of MVI.
 define void @f6() {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mviy 4096(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mviy 4096(%r1), 42
@@ -149,13 +149,13 @@ define void @f6() {
 ; anchors 0x10000 bytes apart, so that the high part can be loaded using
 ; LLILH while still using MVI in more cases than 0x40000 anchors would.
 define void @f7() {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: llilh %r1, 23
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mviy 65535(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: llilh %r1, 23
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mviy 65535(%r1), 42
@@ -172,13 +172,13 @@ define void @f7() {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8() {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: llilh %r1, 24
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mvi 7(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: llilh %r1, 24
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mvi 7(%r1), 42
@@ -200,14 +200,14 @@ define void @f8() {
 ; The LA then gets lowered into the LLILH/LA form.  The exact sequence
 ; isn't that important though.
 define void @f9() {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
 ; CHECK-NOFP: agfi [[R2]], 524288
 ; CHECK-NOFP: mvi 0([[R2]]), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
 ; CHECK-FP: agfi [[R2]], 524288
@@ -226,7 +226,7 @@ define void @f9() {
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
 ; CHECK-NOFP: agr [[REGISTER]], %r15
@@ -234,7 +234,7 @@ define void @f10(i32 *%vptr) {
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
 ; CHECK-FP: agr [[REGISTER]], %r11
@@ -265,7 +265,7 @@ define void @f10(i32 *%vptr) {
 ; However, the FP case uses %r11 as the frame pointer and must therefore
 ; spill a second register.  This leads to an extra displacement of 8.
 define void @f11(i32 *%vptr) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
@@ -275,7 +275,7 @@ define void @f11(i32 *%vptr) {
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: stmg %r6, %r15,
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
diff --git a/test/CodeGen/SystemZ/frame-15.ll b/test/CodeGen/SystemZ/frame-15.ll
index af804da82c0..d8b291d0178 100644
--- a/test/CodeGen/SystemZ/frame-15.ll
+++ b/test/CodeGen/SystemZ/frame-15.ll
@@ -24,11 +24,11 @@ declare void @foo(float *%ptr1, float *%ptr2)
 ; in order to put another object at offset 4088 is (4088 - 176) / 4 = 978
 ; words.
 define void @f1(double *%dst) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r11)
 ; CHECK-FP: br %r14
   %region1 = alloca [978 x float], align 8
@@ -49,12 +49,12 @@ define void @f1(double *%dst) {
 
 ; Test the first out-of-range offset.
 define void @f2(double *%dst) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: lghi %r1, 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: lghi %r1, 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -76,12 +76,12 @@ define void @f2(double *%dst) {
 
 ; Test the next offset after that.
 define void @f3(double *%dst) {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: lghi %r1, 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: lghi %r1, 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -103,12 +103,12 @@ define void @f3(double *%dst) {
 
 ; Add 4096 bytes (1024 words) to the size of each object and repeat.
 define void @f4(double *%dst) {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: lghi %r1, 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: lghi %r1, 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -130,12 +130,12 @@ define void @f4(double *%dst) {
 
 ; ...as above.
 define void @f5(double *%dst) {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: lghi %r1, 8192
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: lghi %r1, 8192
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -157,12 +157,12 @@ define void @f5(double *%dst) {
 
 ; ...as above.
 define void @f6(double *%dst) {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: lghi %r1, 8192
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: lghi %r1, 8192
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -186,12 +186,12 @@ define void @f6(double *%dst) {
 ; being at offset 8192.  This time we need objects of (8192 - 168) / 4 = 2004
 ; words.
 define void @f7(double *%dst) {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: lghi %r1, 8192
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: lghi %r1, 8192
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -214,12 +214,12 @@ define void @f7(double *%dst) {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8(double *%dst) {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: lghi %r1, 12288
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: lghi %r1, 12288
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -243,12 +243,12 @@ define void @f8(double *%dst) {
 ; should force an LAY from the outset.  We don't yet do any kind of anchor
 ; optimization, so there should be no offset on the LDEB itself.
 define void @f9(double *%dst) {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: lay %r1, 12296(%r15)
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: lay %r1, 12296(%r11)
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1)
 ; CHECK-FP: br %r14
@@ -273,14 +273,14 @@ define void @f9(double *%dst) {
 ; %vptr and %dst are copied to call-saved registers, freeing up %r2 and
 ; %r3 during the main test.
 define void @f10(i32 *%vptr, double *%dst) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: lghi [[REGISTER]], 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r15)
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: lghi [[REGISTER]], 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r11)
@@ -318,13 +318,13 @@ define void @f10(i32 *%vptr, double *%dst) {
 
 ; Repeat f2 in a case where the index register is already occupied.
 define void @f11(double *%dst, i64 %index) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1)
diff --git a/test/CodeGen/SystemZ/frame-16.ll b/test/CodeGen/SystemZ/frame-16.ll
index dc67da93f21..9f43b4947f0 100644
--- a/test/CodeGen/SystemZ/frame-16.ll
+++ b/test/CodeGen/SystemZ/frame-16.ll
@@ -20,11 +20,11 @@
 ; emergency spill slots at 160(%r15), the amount that we need to allocate
 ; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.
 define void @f1(i8 %byte) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: stc %r2, 4095(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: stc %r2, 4095(%r11)
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
@@ -38,11 +38,11 @@ define void @f1(i8 %byte) {
 
 ; Test the first offset that is out-of-range of the 12-bit form.
 define void @f2(i8 %byte) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: stcy %r2, 4096(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: stcy %r2, 4096(%r11)
 ; CHECK-FP: br %r14
   %region1 = alloca [3912 x i8], align 8
@@ -59,11 +59,11 @@ define void @f2(i8 %byte) {
 ; The last in-range doubleword offset is 524280, so by the same reasoning
 ; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.
 define void @f3(i8 %byte) {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: stcy %r2, 524287(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: stcy %r2, 524287(%r11)
 ; CHECK-FP: br %r14
   %region1 = alloca [524104 x i8], align 8
@@ -79,12 +79,12 @@ define void @f3(i8 %byte) {
 ; and the offset is also out of LAY's range, so expect a constant load
 ; followed by an addition.
 define void @f4(i8 %byte) {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: stc %r2, 0(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: stc %r2, 0(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -100,12 +100,12 @@ define void @f4(i8 %byte) {
 ; Add 4095 to the previous offset, to test the other end of the STC range.
 ; The instruction will actually be STCY before frame lowering.
 define void @f5(i8 %byte) {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: stc %r2, 4095(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: stc %r2, 4095(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -120,12 +120,12 @@ define void @f5(i8 %byte) {
 
 ; Test the next offset after that, which uses STCY instead of STC.
 define void @f6(i8 %byte) {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: stcy %r2, 4096(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: stcy %r2, 4096(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -143,12 +143,12 @@ define void @f6(i8 %byte) {
 ; anchors 0x10000 bytes apart, so that the high part can be loaded using
 ; LLILH while still using STC in more cases than 0x40000 anchors would.
 define void @f7(i8 %byte) {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: llilh %r1, 23
 ; CHECK-NOFP: stcy %r2, 65535(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: llilh %r1, 23
 ; CHECK-FP: stcy %r2, 65535(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -164,12 +164,12 @@ define void @f7(i8 %byte) {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8(i8 %byte) {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: llilh %r1, 24
 ; CHECK-NOFP: stc %r2, 7(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: llilh %r1, 24
 ; CHECK-FP: stc %r2, 7(%r1,%r11)
 ; CHECK-FP: br %r14
@@ -190,14 +190,14 @@ define void @f8(i8 %byte) {
 ; The LA then gets lowered into the LLILH/LA form.  The exact sequence
 ; isn't that important though.
 define void @f9(i8 %byte) {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
 ; CHECK-NOFP: agfi [[R2]], 524288
 ; CHECK-NOFP: stc %r2, 0([[R2]])
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
 ; CHECK-FP: agfi [[R2]], 524288
@@ -216,14 +216,14 @@ define void @f9(i8 %byte) {
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr, i8 %byte) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
 ; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
 ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
 ; CHECK-FP: stc %r3, 0([[REGISTER]],%r11)
@@ -251,7 +251,7 @@ define void @f10(i32 *%vptr, i8 %byte) {
 ; However, the FP case uses %r11 as the frame pointer and must therefore
 ; spill a second register.  This leads to an extra displacement of 8.
 define void @f11(i32 *%vptr, i8 %byte) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
 ; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
@@ -260,7 +260,7 @@ define void @f11(i32 *%vptr, i8 %byte) {
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: stmg %r6, %r15,
 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
@@ -305,13 +305,13 @@ define void @f11(i32 *%vptr, i8 %byte) {
 
 ; Repeat f4 in a case where the index register is already occupied.
 define void @f12(i8 %byte, i64 %index) {
-; CHECK-NOFP: f12:
+; CHECK-NOFP-LABEL: f12:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: stc %r2, 0(%r3,%r1)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f12:
+; CHECK-FP-LABEL: f12:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: stc %r2, 0(%r3,%r1)
diff --git a/test/CodeGen/SystemZ/frame-17.ll b/test/CodeGen/SystemZ/frame-17.ll
index 613d9f87955..97cf83dfd78 100644
--- a/test/CodeGen/SystemZ/frame-17.ll
+++ b/test/CodeGen/SystemZ/frame-17.ll
@@ -6,7 +6,7 @@
 ; 4-byte spill slot, rounded to 8 bytes.  The frame size should be exactly
 ; 160 + 8 * 8 = 232.
 define void @f1(float *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -232
 ; CHECK: std %f8, 224(%r15)
 ; CHECK: std %f9, 216(%r15)
@@ -70,7 +70,7 @@ define void @f1(float *%ptr) {
 
 ; Same for doubles, except that the full spill slot is used.
 define void @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -232
 ; CHECK: std %f8, 224(%r15)
 ; CHECK: std %f9, 216(%r15)
@@ -131,7 +131,7 @@ define void @f2(double *%ptr) {
 
 ; The long double case needs a 16-byte spill slot.
 define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -240
 ; CHECK: std %f8, 232(%r15)
 ; CHECK: std %f9, 224(%r15)
diff --git a/test/CodeGen/SystemZ/frame-18.ll b/test/CodeGen/SystemZ/frame-18.ll
index a9977ed04b4..57d6f7d4db2 100644
--- a/test/CodeGen/SystemZ/frame-18.ll
+++ b/test/CodeGen/SystemZ/frame-18.ll
@@ -5,7 +5,7 @@
 ; We need to allocate a 4-byte spill slot, rounded to 8 bytes.  The frame
 ; size should be exactly 160 + 8 = 168.
 define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: aghi %r15, -168
 ; CHECK-NOT: 160(%r15)
@@ -50,7 +50,7 @@ define void @f1(i32 *%ptr) {
 
 ; Same for i64, except that the full spill slot is used.
 define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: aghi %r15, -168
 ; CHECK: stg [[REGISTER:%r[0-9]+]], 160(%r15)
diff --git a/test/CodeGen/SystemZ/insert-01.ll b/test/CodeGen/SystemZ/insert-01.ll
index 2ff9ff4bee2..5f14b2919e1 100644
--- a/test/CodeGen/SystemZ/insert-01.ll
+++ b/test/CodeGen/SystemZ/insert-01.ll
@@ -5,7 +5,7 @@
 ; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
 ; The whole sequence can be performed by IC.
 define i32 @f1(i32 %orig, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define i32 @f1(i32 %orig, i8 *%ptr) {
 
 ; Like f1, but with the operands reversed.
 define i32 @f2(i32 %orig, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -32,7 +32,7 @@ define i32 @f2(i32 %orig, i8 *%ptr) {
 ; Check a case where more bits than lower 8 are masked out of the
 ; register value.  We can use IC but must keep the original mask.
 define i32 @f3(i32 %orig, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg %r2, %r2, 32, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -45,7 +45,7 @@ define i32 @f3(i32 %orig, i8 *%ptr) {
 
 ; Like f3, but with the operands reversed.
 define i32 @f4(i32 %orig, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 32, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i32 @f4(i32 %orig, i8 *%ptr) {
 
 ; Check a case where the low 8 bits are cleared by a shift left.
 define i32 @f5(i32 %orig, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sll %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f5(i32 %orig, i8 *%ptr) {
 
 ; Like f5, but with the operands reversed.
 define i32 @f6(i32 %orig, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sll %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i32 @f6(i32 %orig, i8 *%ptr) {
 
 ; Check insertions into a constant.
 define i32 @f7(i32 %orig, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lhi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -96,7 +96,7 @@ define i32 @f7(i32 %orig, i8 *%ptr) {
 
 ; Like f7, but with the operands reversed.
 define i32 @f8(i32 %orig, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lhi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define i32 @f8(i32 %orig, i8 *%ptr) {
 
 ; Check the high end of the IC range.
 define i32 @f9(i32 %orig, i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ic %r2, 4095(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -121,7 +121,7 @@ define i32 @f9(i32 %orig, i8 *%src) {
 
 ; Check the next byte up, which should use ICY instead of IC.
 define i32 @f10(i32 %orig, i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: icy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -134,7 +134,7 @@ define i32 @f10(i32 %orig, i8 *%src) {
 
 ; Check the high end of the ICY range.
 define i32 @f11(i32 %orig, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: icy %r2, 524287(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -148,7 +148,7 @@ define i32 @f11(i32 %orig, i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f12(i32 %orig, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define i32 @f12(i32 %orig, i8 *%src) {
 
 ; Check the high end of the negative ICY range.
 define i32 @f13(i32 %orig, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: icy %r2, -1(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -175,7 +175,7 @@ define i32 @f13(i32 %orig, i8 *%src) {
 
 ; Check the low end of the ICY range.
 define i32 @f14(i32 %orig, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: icy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -189,7 +189,7 @@ define i32 @f14(i32 %orig, i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f15(i32 %orig, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: agfi %r3, -524289
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -203,7 +203,7 @@ define i32 @f15(i32 %orig, i8 *%src) {
 
 ; Check that IC allows an index.
 define i32 @f16(i32 %orig, i8 *%src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
@@ -217,7 +217,7 @@ define i32 @f16(i32 %orig, i8 *%src, i64 %index) {
 
 ; Check that ICY allows an index.
 define i32 @f17(i32 %orig, i8 *%src, i64 %index) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
diff --git a/test/CodeGen/SystemZ/insert-02.ll b/test/CodeGen/SystemZ/insert-02.ll
index e9980144e9e..05958a65dc2 100644
--- a/test/CodeGen/SystemZ/insert-02.ll
+++ b/test/CodeGen/SystemZ/insert-02.ll
@@ -5,7 +5,7 @@
 ; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
 ; The whole sequence can be performed by IC.
 define i64 @f1(i64 %orig, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define i64 @f1(i64 %orig, i8 *%ptr) {
 
 ; Like f1, but with the operands reversed.
 define i64 @f2(i64 %orig, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -32,7 +32,7 @@ define i64 @f2(i64 %orig, i8 *%ptr) {
 ; Check a case where more bits than lower 8 are masked out of the
 ; register value.  We can use IC but must keep the original mask.
 define i64 @f3(i64 %orig, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg %r2, %r2, 0, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -45,7 +45,7 @@ define i64 @f3(i64 %orig, i8 *%ptr) {
 
 ; Like f3, but with the operands reversed.
 define i64 @f4(i64 %orig, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 0, 182, 0
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i64 @f4(i64 %orig, i8 *%ptr) {
 
 ; Check a case where the low 8 bits are cleared by a shift left.
 define i64 @f5(i64 %orig, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sllg %r2, %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i64 @f5(i64 %orig, i8 *%ptr) {
 
 ; Like f5, but with the operands reversed.
 define i64 @f6(i64 %orig, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r2, %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f6(i64 %orig, i8 *%ptr) {
 
 ; Check insertions into a constant.
 define i64 @f7(i64 %orig, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lghi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -96,7 +96,7 @@ define i64 @f7(i64 %orig, i8 *%ptr) {
 
 ; Like f7, but with the operands reversed.
 define i64 @f8(i64 %orig, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lghi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define i64 @f8(i64 %orig, i8 *%ptr) {
 
 ; Check the high end of the IC range.
 define i64 @f9(i64 %orig, i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ic %r2, 4095(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -121,7 +121,7 @@ define i64 @f9(i64 %orig, i8 *%src) {
 
 ; Check the next byte up, which should use ICY instead of IC.
 define i64 @f10(i64 %orig, i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: icy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -134,7 +134,7 @@ define i64 @f10(i64 %orig, i8 *%src) {
 
 ; Check the high end of the ICY range.
 define i64 @f11(i64 %orig, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: icy %r2, 524287(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -148,7 +148,7 @@ define i64 @f11(i64 %orig, i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f12(i64 %orig, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define i64 @f12(i64 %orig, i8 *%src) {
 
 ; Check the high end of the negative ICY range.
 define i64 @f13(i64 %orig, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: icy %r2, -1(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -175,7 +175,7 @@ define i64 @f13(i64 %orig, i8 *%src) {
 
 ; Check the low end of the ICY range.
 define i64 @f14(i64 %orig, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: icy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -189,7 +189,7 @@ define i64 @f14(i64 %orig, i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f15(i64 %orig, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: agfi %r3, -524289
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -203,7 +203,7 @@ define i64 @f15(i64 %orig, i8 *%src) {
 
 ; Check that IC allows an index.
 define i64 @f16(i64 %orig, i8 *%src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
@@ -217,7 +217,7 @@ define i64 @f16(i64 %orig, i8 *%src, i64 %index) {
 
 ; Check that ICY allows an index.
 define i64 @f17(i64 %orig, i8 *%src, i64 %index) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
diff --git a/test/CodeGen/SystemZ/insert-03.ll b/test/CodeGen/SystemZ/insert-03.ll
index 261eabd1be7..c3c1ae316c9 100644
--- a/test/CodeGen/SystemZ/insert-03.ll
+++ b/test/CodeGen/SystemZ/insert-03.ll
@@ -5,7 +5,7 @@
 ; Check the lowest useful IILL value.  (We use NILL rather than IILL
 ; to clear 16 bits.)
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 1
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define i32 @f1(i32 %a) {
 
 ; Check a middle value.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 32769
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define i32 @f2(i32 %a) {
 ; Check the highest useful IILL value.  (We use OILL rather than IILL
 ; to set 16 bits.)
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 65534
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the lowest useful IILH value.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 1
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define i32 @f4(i32 %a) {
 
 ; Check a middle value.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 32767
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the highest useful IILH value.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 65534
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/insert-04.ll b/test/CodeGen/SystemZ/insert-04.ll
index 07f88b9859e..5ce99dfcb7b 100644
--- a/test/CodeGen/SystemZ/insert-04.ll
+++ b/test/CodeGen/SystemZ/insert-04.ll
@@ -5,7 +5,7 @@
 ; Check the lowest useful IILL value.  (We use NILL rather than IILL
 ; to clear 16 bits.)
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 1
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a) {
 
 ; Check a middle value.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 32769
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define i64 @f2(i64 %a) {
 ; Check the highest useful IILL value.  (We use OILL rather than IILL
 ; to set 16 bits.)
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 65534
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the lowest useful IILH value.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 1
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define i64 @f4(i64 %a) {
 
 ; Check a middle value.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 32767
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the highest useful IILH value.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 65534
 ; CHECK: br %r14
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the lowest useful IIHL value.
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: ni
 ; CHECK: iihl %r2, 1
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define i64 @f7(i64 %a) {
 
 ; Check a middle value.
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: ni
 ; CHECK: iihl %r2, 32767
 ; CHECK: br %r14
@@ -94,7 +94,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the highest useful IIHL value.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: ni
 ; CHECK: iihl %r2, 65534
 ; CHECK: br %r14
@@ -105,7 +105,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the lowest useful IIHH value.
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: ni
 ; CHECK: iihh %r2, 1
 ; CHECK: br %r14
@@ -116,7 +116,7 @@ define i64 @f10(i64 %a) {
 
 ; Check a middle value.
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: ni
 ; CHECK: iihh %r2, 32767
 ; CHECK: br %r14
@@ -127,7 +127,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the highest useful IIHH value.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: ni
 ; CHECK: iihh %r2, 65534
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/insert-05.ll b/test/CodeGen/SystemZ/insert-05.ll
index da51676b99c..b76859a568f 100644
--- a/test/CodeGen/SystemZ/insert-05.ll
+++ b/test/CodeGen/SystemZ/insert-05.ll
@@ -4,7 +4,7 @@
 
 ; Prefer LHI over IILF for signed 16-bit constants.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, 1
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the LHI range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, 32767
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the next value up, which should use IILF instead.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: ni
 ; CHECK: iilf %r2, 32768
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a) {
 
 ; Check a value in which the lower 16 bits are clear.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: ni
 ; CHECK: iilf %r2, 65536
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the highest useful IILF value (-0x8001).
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: ni
 ; CHECK: iilf %r2, 4294934527
 ; CHECK: br %r14
@@ -59,7 +59,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the next value up, which should use LHI instead.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, -32768
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i64 @f6(i64 %a) {
 ; Check the highest useful LHI value.  (We use OILF for -1 instead, although
 ; LHI might be better there too.)
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, -2
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define i64 @f7(i64 %a) {
 ; Check that SRLG is still used if some of the high bits are known to be 0
 ; (and so might be removed from the mask).
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f8(i64 %a) {
 
 ; Repeat f8 with addition, which is known to be equivalent to OR in this case.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define i64 @f9(i64 %a) {
 
 ; Repeat f8 with already-zero bits removed from the mask.
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define i64 @f10(i64 %a) {
 
 ; Repeat f10 with addition, which is known to be equivalent to OR in this case.
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the lowest useful IIHF value.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: ni
 ; CHECK: iihf %r2, 1
 ; CHECK: br %r14
@@ -142,7 +142,7 @@ define i64 @f12(i64 %a) {
 
 ; Check a value in which the lower 16 bits are clear.
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-NOT: ni
 ; CHECK: iihf %r2, 2147483648
 ; CHECK: br %r14
@@ -153,7 +153,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the highest useful IIHF value (0xfffffffe).
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: ni
 ; CHECK: iihf %r2, 4294967294
 ; CHECK: br %r14
@@ -165,7 +165,7 @@ define i64 @f14(i64 %a) {
 ; Check a case in which some of the low 32 bits are known to be clear,
 ; and so could be removed from the AND mask.
 define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -177,7 +177,7 @@ define i64 @f15(i64 %a) {
 
 ; Repeat f15 with the zero bits explicitly removed from the mask.
 define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -189,7 +189,7 @@ define i64 @f16(i64 %a) {
 
 ; Check concatenation of two i32s.
 define i64 @f17(i32 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: msr %r2, %r2
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -201,7 +201,7 @@ define i64 @f17(i32 %a) {
 
 ; Repeat f17 with the operands reversed.
 define i64 @f18(i32 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: msr %r2, %r2
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -213,7 +213,7 @@ define i64 @f18(i32 %a) {
 
 ; The truncation here isn't free; we need an explicit zero extension.
 define i64 @f19(i32 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: oihl %r2, 1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/insert-06.ll b/test/CodeGen/SystemZ/insert-06.ll
index 4a13ef47c88..8366b2c7979 100644
--- a/test/CodeGen/SystemZ/insert-06.ll
+++ b/test/CodeGen/SystemZ/insert-06.ll
@@ -4,7 +4,7 @@
 
 ; Insertion of an i32 can be done using LR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; ... and again with the operands reversed.
 define i64 @f2(i64 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define i64 @f2(i64 %a, i32 %b) {
 
 ; Like f1, but with "in register" zero extension.
 define i64 @f3(i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i64 %b) {
 
 ; ... and again with the operands reversed.
 define i64 @f4(i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -52,7 +52,7 @@ define i64 @f4(i64 %a, i64 %b) {
 
 ; Unary operations can be done directly into the low half.
 define i64 @f5(i64 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lcr %r2, %r3
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 %b) {
 
 ; ...likewise three-operand binary operations like RLL.
 define i64 @f6(i64 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: rll %r2, %r3, 1
 ; CHECK: br %r14
@@ -81,7 +81,7 @@ define i64 @f6(i64 %a, i32 %b) {
 ; Loads can be done directly into the low half.  The range of L is checked
 ; in the move tests.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: br %r14
@@ -94,7 +94,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; ...likewise extending loads.
 define i64 @f8(i64 %a, i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lb %r2, 0(%r3)
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define i64 @f8(i64 %a, i8 *%src) {
 ; that the upper half of one OR operand and the lower half of the other are
 ; both clear.
 define i64 @f9(i64 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: sllg %r2, %r2, 32
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define i64 @f9(i64 %a, i32 %b) {
 
 ; ...and again with the operands reversed.
 define i64 @f10(i64 %a, i32 %b) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sllg %r2, %r2, 32
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -134,7 +134,7 @@ define i64 @f10(i64 %a, i32 %b) {
 
 ; Like f9, but with "in register" zero extension.
 define i64 @f11(i64 %a, i64 %b) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   %shift = shl i64 %a, 32
@@ -145,7 +145,7 @@ define i64 @f11(i64 %a, i64 %b) {
 
 ; ...and again with the operands reversed.
 define i64 @f12(i64 %a, i64 %b) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   %shift = shl i64 %a, 32
@@ -156,7 +156,7 @@ define i64 @f12(i64 %a, i64 %b) {
 
 ; Like f9, but for larger shifts than 32.
 define i64 @f13(i64 %a, i32 %b) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: sllg %r2, %r2, 60
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-01.ll b/test/CodeGen/SystemZ/int-add-01.ll
index d12ac229774..4114686e41e 100644
--- a/test/CodeGen/SystemZ/int-add-01.ll
+++ b/test/CodeGen/SystemZ/int-add-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the AH range.
 define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned AH range.
 define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ah %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -28,7 +28,7 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 
 ; Check the next halfword up, which should use AHY instead of AH.
 define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ahy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -40,7 +40,7 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned AHY range.
 define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ahy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -53,7 +53,7 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the negative aligned AHY range.
 define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ahy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 
 ; Check the low end of the AHY range.
 define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -91,7 +91,7 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 
 ; Check that AH allows an index.
 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ah %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -118,7 +118,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
 
 ; Check that AHY allows an index.
 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ahy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-add-02.ll b/test/CodeGen/SystemZ/int-add-02.ll
index bc434a634a4..0d4c8ce7a02 100644
--- a/test/CodeGen/SystemZ/int-add-02.ll
+++ b/test/CodeGen/SystemZ/int-add-02.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check AR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ar %r2, %r3
 ; CHECK: br %r14
   %add = add i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the A range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned A range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: a %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use AY instead of A.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ay %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned AY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ay %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned AY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ay %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the AY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ay %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that A allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: a %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that AY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: ay %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that additions of spilled values can use A rather than AR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: a %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-03.ll b/test/CodeGen/SystemZ/int-add-03.ll
index bfd163db54f..56000a80cd9 100644
--- a/test/CodeGen/SystemZ/int-add-03.ll
+++ b/test/CodeGen/SystemZ/int-add-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check AGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: agfr %r2, %r3
 ; CHECK: br %r14
   %bext = sext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check AGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned AGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned AGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the AGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that AGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that additions of spilled values can use AGF rather than AGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: agf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-04.ll b/test/CodeGen/SystemZ/int-add-04.ll
index 6c8e5cf2268..675e36babfa 100644
--- a/test/CodeGen/SystemZ/int-add-04.ll
+++ b/test/CodeGen/SystemZ/int-add-04.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check ALGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algfr %r2, %r3
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check ALGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned ALGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: algf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned ALGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: algf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the ALGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: algf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that ALGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: algf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that additions of spilled values can use ALGF rather than ALGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: algf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-05.ll b/test/CodeGen/SystemZ/int-add-05.ll
index ee840ac6478..4f39a2d4dec 100644
--- a/test/CodeGen/SystemZ/int-add-05.ll
+++ b/test/CodeGen/SystemZ/int-add-05.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check AGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: agr %r2, %r3
 ; CHECK: br %r14
   %add = add i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check AG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned AG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ag %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned AG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ag %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the AG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ag %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that AG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ag %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that additions of spilled values can use AG rather than AGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ag %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-06.ll b/test/CodeGen/SystemZ/int-add-06.ll
index 3a9c698dd24..142c7559802 100644
--- a/test/CodeGen/SystemZ/int-add-06.ll
+++ b/test/CodeGen/SystemZ/int-add-06.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ahi %r2, 1
 ; CHECK: br %r14
   %add = add i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the AHI range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ahi %r2, 32767
 ; CHECK: br %r14
   %add = add i32 %a, 32767
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; Check the next value up, which must use AFI instead.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi %r2, 32768
 ; CHECK: br %r14
   %add = add i32 %a, 32768
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the high end of the signed 32-bit range.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi %r2, 2147483647
 ; CHECK: br %r14
   %add = add i32 %a, 2147483647
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a) {
 
 ; Check the next value up, which is treated as a negative value.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi %r2, -2147483648
 ; CHECK: br %r14
   %add = add i32 %a, 2147483648
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the high end of the negative AHI range.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ahi %r2, -1
 ; CHECK: br %r14
   %add = add i32 %a, -1
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a) {
 
 ; Check the low end of the AHI range.
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahi %r2, -32768
 ; CHECK: br %r14
   %add = add i32 %a, -32768
@@ -67,7 +67,7 @@ define i32 @f7(i32 %a) {
 
 ; Check the next value down, which must use AFI instead.
 define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: afi %r2, -32769
 ; CHECK: br %r14
   %add = add i32 %a, -32769
@@ -76,7 +76,7 @@ define i32 @f8(i32 %a) {
 
 ; Check the low end of the signed 32-bit range.
 define i32 @f9(i32 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r2, -2147483648
 ; CHECK: br %r14
   %add = add i32 %a, -2147483648
@@ -85,7 +85,7 @@ define i32 @f9(i32 %a) {
 
 ; Check the next value down, which is treated as a positive value.
 define i32 @f10(i32 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: afi %r2, 2147483647
 ; CHECK: br %r14
   %add = add i32 %a, -2147483649
diff --git a/test/CodeGen/SystemZ/int-add-07.ll b/test/CodeGen/SystemZ/int-add-07.ll
index a065bb2ee13..e9e0212e4df 100644
--- a/test/CodeGen/SystemZ/int-add-07.ll
+++ b/test/CodeGen/SystemZ/int-add-07.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: {{aghi %r2, 1|la %r[0-5], 1\(%r2\)}}
 ; CHECK: br %r14
   %add = add i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the AGHI range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r2, 32767
 ; CHECK: br %r14
   %add = add i64 %a, 32767
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the next value up, which must use AGFI instead.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: {{agfi %r2, 32768|lay %r[0-5], 32768\(%r2\)}}
 ; CHECK: br %r14
   %add = add i64 %a, 32768
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the high end of the AGFI range.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r2, 2147483647
 ; CHECK: br %r14
   %add = add i64 %a, 2147483647
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the next value up, which must use ALGFI instead.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: algfi %r2, 2147483648
 ; CHECK: br %r14
   %add = add i64 %a, 2147483648
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the high end of the ALGFI range.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: algfi %r2, 4294967295
 ; CHECK: br %r14
   %add = add i64 %a, 4294967295
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the next value up, which must be loaded into a register first.
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llihl %r0, 1
 ; CHECK: agr
 ; CHECK: br %r14
@@ -68,7 +68,7 @@ define i64 @f7(i64 %a) {
 
 ; Check the high end of the negative AGHI range.
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, -1
 ; CHECK: br %r14
   %add = add i64 %a, -1
@@ -77,7 +77,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the low end of the AGHI range.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -32768
 ; CHECK: br %r14
   %add = add i64 %a, -32768
@@ -86,7 +86,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the next value down, which must use AGFI instead.
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: {{agfi %r2, -32769|lay %r[0-5]+, -32769\(%r2\)}}
 ; CHECK: br %r14
   %add = add i64 %a, -32769
@@ -95,7 +95,7 @@ define i64 @f10(i64 %a) {
 
 ; Check the low end of the AGFI range.
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -2147483648
 ; CHECK: br %r14
   %add = add i64 %a, -2147483648
@@ -104,7 +104,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the next value down, which must use SLGFI instead.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: slgfi %r2, 2147483649
 ; CHECK: br %r14
   %add = add i64 %a, -2147483649
@@ -113,7 +113,7 @@ define i64 @f12(i64 %a) {
 
 ; Check the low end of the SLGFI range.
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: slgfi %r2, 4294967295
 ; CHECK: br %r14
   %add = add i64 %a, -4294967295
@@ -122,7 +122,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the next value down, which must use register addition instead.
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: llihf %r0, 4294967295
 ; CHECK: agr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-08.ll b/test/CodeGen/SystemZ/int-add-08.ll
index 0b8c01eac96..d645137e5f6 100644
--- a/test/CodeGen/SystemZ/int-add-08.ll
+++ b/test/CodeGen/SystemZ/int-add-08.ll
@@ -6,7 +6,7 @@ declare i128 *@foo()
 
 ; Test register addition.
 define void @f1(i128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define void @f1(i128 *%ptr) {
 ; Test memory addition with no offset.  Making the load of %a volatile
 ; should force the memory operand to be %b.
 define void @f2(i128 *%aptr, i64 %addr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: alg {{%r[0-5]}}, 8(%r3)
 ; CHECK: alcg {{%r[0-5]}}, 0(%r3)
 ; CHECK: br %r14
@@ -33,7 +33,7 @@ define void @f2(i128 *%aptr, i64 %addr) {
 
 ; Test the highest aligned offset that is in range of both ALG and ALCG.
 define void @f3(i128 *%aptr, i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: alg {{%r[0-5]}}, 524280(%r3)
 ; CHECK: alcg {{%r[0-5]}}, 524272(%r3)
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define void @f3(i128 *%aptr, i64 %base) {
 
 ; Test the next doubleword up, which requires separate address logic for ALG.
 define void @f4(i128 *%aptr, i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgr [[BASE:%r[1-5]]], %r3
 ; CHECK: agfi [[BASE]], 524288
 ; CHECK: alg {{%r[0-5]}}, 0([[BASE]])
@@ -67,7 +67,7 @@ define void @f4(i128 *%aptr, i64 %base) {
 ; both instructions.  It would be better to create an anchor at 524288
 ; that both instructions can use, but that isn't implemented yet.
 define void @f5(i128 *%aptr, i64 %base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: alg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -82,7 +82,7 @@ define void @f5(i128 *%aptr, i64 %base) {
 
 ; Test the lowest displacement that is in range of both ALG and ALCG.
 define void @f6(i128 *%aptr, i64 %base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: alg {{%r[0-5]}}, -524280(%r3)
 ; CHECK: alcg {{%r[0-5]}}, -524288(%r3)
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define void @f6(i128 *%aptr, i64 %base) {
 
 ; Test the next doubleword down, which is out of range of the ALCG.
 define void @f7(i128 *%aptr, i64 %base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: alg {{%r[0-5]}}, -524288(%r3)
 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -113,7 +113,7 @@ define void @f7(i128 *%aptr, i64 %base) {
 ; Check that additions of spilled values can use ALG and ALCG rather than
 ; ALGR and ALCGR.
 define void @f8(i128 *%ptr0) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
diff --git a/test/CodeGen/SystemZ/int-add-09.ll b/test/CodeGen/SystemZ/int-add-09.ll
index bfe63389f18..43136bde332 100644
--- a/test/CodeGen/SystemZ/int-add-09.ll
+++ b/test/CodeGen/SystemZ/int-add-09.ll
@@ -5,7 +5,7 @@
 ; Check additions of 1.  The XOR ensures that we don't instead load the
 ; constant into a register and use memory addition.
 define void @f1(i128 *%aptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algfi {{%r[0-5]}}, 1
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define void @f1(i128 *%aptr) {
 
 ; Check the high end of the ALGFI range.
 define void @f2(i128 *%aptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: algfi {{%r[0-5]}}, 4294967295
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define void @f2(i128 *%aptr) {
 
 ; Check the next value up, which must use register addition.
 define void @f3(i128 *%aptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ define void @f3(i128 *%aptr) {
 
 ; Check addition of -1, which must also use register addition.
 define void @f4(i128 *%aptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-10.ll b/test/CodeGen/SystemZ/int-add-10.ll
index 17cfdbe3377..66a275bc6c7 100644
--- a/test/CodeGen/SystemZ/int-add-10.ll
+++ b/test/CodeGen/SystemZ/int-add-10.ll
@@ -5,7 +5,7 @@
 ; Check register additions.  The XOR ensures that we don't instead zero-extend
 ; %b into a register and use memory addition.
 define void @f1(i128 *%aptr, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define void @f1(i128 *%aptr, i32 %b) {
 
 ; Like f1, but using an "in-register" extension.
 define void @f2(i128 *%aptr, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f2(i128 *%aptr, i64 %b) {
 ; Test register addition in cases where the second operand is zero extended
 ; from i64 rather than i32, but is later masked to i32 range.
 define void @f3(i128 *%aptr, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f3(i128 *%aptr, i64 %b) {
 
 ; Test ALGF with no offset.
 define void @f4(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define void @f4(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the ALGF range.
 define void @f5(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: algf {{%r[0-5]}}, 524284(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -82,7 +82,7 @@ define void @f5(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcgr
@@ -99,7 +99,7 @@ define void @f6(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the negative aligned ALGF range.
 define void @f7(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: algf {{%r[0-5]}}, -4(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -115,7 +115,7 @@ define void @f7(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the low end of the ALGF range.
 define void @f8(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: algf {{%r[0-5]}}, -524288(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define void @f8(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcgr
@@ -149,7 +149,7 @@ define void @f9(i128 *%aptr, i32 *%bsrc) {
 
 ; Check that ALGF allows an index.
 define void @f10(i128 *%aptr, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: algf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %a = load i128 *%aptr
diff --git a/test/CodeGen/SystemZ/int-add-11.ll b/test/CodeGen/SystemZ/int-add-11.ll
index 47a776ecf6e..6c617ba19c5 100644
--- a/test/CodeGen/SystemZ/int-add-11.ll
+++ b/test/CodeGen/SystemZ/int-add-11.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i32 *%ptr) {
 
 ; Check the high end of the constant range.
 define void @f2(i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: asi 0(%r2), 127
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -27,7 +27,7 @@ define void @f2(i32 *%ptr) {
 ; Check the next constant up, which must use an addition and a store.
 ; Both L/AHI and LHI/A would be OK.
 define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: asi
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define void @f3(i32 *%ptr) {
 
 ; Check the low end of the constant range.
 define void @f4(i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: asi 0(%r2), -128
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -50,7 +50,7 @@ define void @f4(i32 *%ptr) {
 
 ; Check the next value down, with the same comment as f3.
 define void @f5(i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: asi
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f5(i32 *%ptr) {
 
 ; Check the high end of the aligned ASI range.
 define void @f6(i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: asi 524284(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 131071
@@ -75,7 +75,7 @@ define void @f6(i32 *%base) {
 ; Check the next word up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define void @f7(i32 *%base) {
 
 ; Check the low end of the ASI range.
 define void @f8(i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: asi -524288(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 -131072
@@ -101,7 +101,7 @@ define void @f8(i32 *%base) {
 ; Check the next word down, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524292
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
@@ -114,7 +114,7 @@ define void @f9(i32 *%base) {
 
 ; Check that ASI does not allow indices.
 define void @f10(i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: asi 4(%r2), 1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-12.ll b/test/CodeGen/SystemZ/int-add-12.ll
index ae1c1f735fa..ef4dc3933ec 100644
--- a/test/CodeGen/SystemZ/int-add-12.ll
+++ b/test/CodeGen/SystemZ/int-add-12.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define void @f1(i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i64 *%ptr) {
 
 ; Check the high end of the constant range.
 define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: agsi 0(%r2), 127
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -27,7 +27,7 @@ define void @f2(i64 *%ptr) {
 ; Check the next constant up, which must use an addition and a store.
 ; Both LG/AGHI and LGHI/AG would be OK.
 define void @f3(i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: agsi
 ; CHECK: stg %r0, 0(%r2)
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define void @f3(i64 *%ptr) {
 
 ; Check the low end of the constant range.
 define void @f4(i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agsi 0(%r2), -128
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -50,7 +50,7 @@ define void @f4(i64 *%ptr) {
 
 ; Check the next value down, with the same comment as f3.
 define void @f5(i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: agsi
 ; CHECK: stg %r0, 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f5(i64 *%ptr) {
 
 ; Check the high end of the aligned AGSI range.
 define void @f6(i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agsi 524280(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 65535
@@ -75,7 +75,7 @@ define void @f6(i64 *%base) {
 ; Check the next doubleword up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define void @f7(i64 *%base) {
 
 ; Check the low end of the AGSI range.
 define void @f8(i64 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agsi -524288(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 -65536
@@ -101,7 +101,7 @@ define void @f8(i64 *%base) {
 ; Check the next doubleword down, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i64 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524296
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
@@ -114,7 +114,7 @@ define void @f9(i64 *%base) {
 
 ; Check that AGSI does not allow indices.
 define void @f10(i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: agsi 8(%r2), 1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-01.ll b/test/CodeGen/SystemZ/int-cmp-01.ll
index aa432f0b04f..dbfe0dfd645 100644
--- a/test/CodeGen/SystemZ/int-cmp-01.ll
+++ b/test/CodeGen/SystemZ/int-cmp-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the CH range.
 define void @f1(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -18,7 +18,7 @@ define void @f1(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the high end of the aligned CH range.
 define void @f2(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ch %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -32,7 +32,7 @@ define void @f2(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the next halfword up, which should use CHY instead of CH.
 define void @f3(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -46,7 +46,7 @@ define void @f3(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the high end of the aligned CHY range.
 define void @f4(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -61,7 +61,7 @@ define void @f4(i32 %lhs, i16 *%src, i32 *%dst) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f5(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define void @f5(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the high end of the negative aligned CHY range.
 define void @f6(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: chy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -90,7 +90,7 @@ define void @f6(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the low end of the CHY range.
 define void @f7(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: chy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -105,7 +105,7 @@ define void @f7(i32 %lhs, i16 *%src, i32 *%dst) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define void @f8(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check that CH allows an index.
 define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ch %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
@@ -136,7 +136,7 @@ define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
 
 ; Check that CHY allows an index.
 define void @f10(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: chy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
diff --git a/test/CodeGen/SystemZ/int-cmp-02.ll b/test/CodeGen/SystemZ/int-cmp-02.ll
index b98661ed4dd..455350b974c 100644
--- a/test/CodeGen/SystemZ/int-cmp-02.ll
+++ b/test/CodeGen/SystemZ/int-cmp-02.ll
@@ -4,7 +4,7 @@
 
 ; Check register comparison.
 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: crjl %r2, %r3
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
 
 ; Check the low end of the C range.
 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: c %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -28,7 +28,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned C range.
 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: c %r2, 4092(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -42,7 +42,7 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which should use CY instead of C.
 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cy %r2, 4096(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the aligned CY range.
 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cy %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -71,7 +71,7 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: c %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -86,7 +86,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CY range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cy %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -100,7 +100,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the low end of the CY range.
 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cy %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -115,7 +115,7 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: c %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -130,7 +130,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check that C allows an index.
 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: c %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -146,7 +146,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 
 ; Check that CY allows an index.
 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-03.ll b/test/CodeGen/SystemZ/int-cmp-03.ll
index bd802bcedcd..2d679cf592e 100644
--- a/test/CodeGen/SystemZ/int-cmp-03.ll
+++ b/test/CodeGen/SystemZ/int-cmp-03.ll
@@ -4,7 +4,7 @@
 
 ; Check register comparison.
 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -16,7 +16,7 @@ define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
 
 ; Check the low end of the CL range.
 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cl %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -29,7 +29,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned CL range.
 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cl %r2, 4092(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which should use CLY instead of CL.
 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cly %r2, 4096(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -57,7 +57,7 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the aligned CLY range.
 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cly %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -72,7 +72,7 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cl %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -87,7 +87,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CLY range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cly %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -101,7 +101,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the low end of the CLY range.
 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cly %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -116,7 +116,7 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: cl %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -131,7 +131,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check that CL allows an index.
 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cl %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -147,7 +147,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 
 ; Check that CLY allows an index.
 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cly %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-04.ll b/test/CodeGen/SystemZ/int-cmp-04.ll
index d0625fbddba..54c4b5baad3 100644
--- a/test/CodeGen/SystemZ/int-cmp-04.ll
+++ b/test/CodeGen/SystemZ/int-cmp-04.ll
@@ -5,7 +5,7 @@
 
 ; Check CGH with no displacement.
 define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -18,7 +18,7 @@ define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the high end of the aligned CGH range.
 define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgh %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -33,7 +33,7 @@ define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the high end of the negative aligned CGH range.
 define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgh %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -62,7 +62,7 @@ define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the low end of the CGH range.
 define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgh %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -77,7 +77,7 @@ define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, -524290
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -92,7 +92,7 @@ define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check that CGH allows an index.
 define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
diff --git a/test/CodeGen/SystemZ/int-cmp-05.ll b/test/CodeGen/SystemZ/int-cmp-05.ll
index d953ebfc679..36d12a5b663 100644
--- a/test/CodeGen/SystemZ/int-cmp-05.ll
+++ b/test/CodeGen/SystemZ/int-cmp-05.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check signed register comparison.
 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgfr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check unsigned register comparison, which can't use CGFR.
 define double @f2(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: cgfr
 ; CHECK: br %r14
   %i2 = sext i32 %unext to i64
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check register equality.
 define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cgfr %r2, %r3
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check register inequality.
 define double @f4(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgfr %r2, %r3
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check signed comparisonn with memory.
 define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -70,7 +70,7 @@ define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check unsigned comparison with memory.
 define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cgf
 ; CHECK: br %r14
   %unext = load i32 *%ptr
@@ -82,7 +82,7 @@ define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory equality.
 define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -96,7 +96,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory inequality.
 define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -110,7 +110,7 @@ define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned CGF range.
 define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgf %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -126,7 +126,7 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f10(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -142,7 +142,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CGF range.
 define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cgf %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the low end of the CGF range.
 define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cgf %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -173,7 +173,7 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agfi %r3, -524292
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -189,7 +189,7 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check that CGF allows an index.
 define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -206,7 +206,7 @@ define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
 
 ; Check that comparisons of spilled values can use CGF rather than CGFR.
 define i64 @f15(i32 *%ptr0) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: cgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-06.ll b/test/CodeGen/SystemZ/int-cmp-06.ll
index f8666316d06..cdd61141d8d 100644
--- a/test/CodeGen/SystemZ/int-cmp-06.ll
+++ b/test/CodeGen/SystemZ/int-cmp-06.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check unsigned register comparison.
 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -19,7 +19,7 @@ define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation.
 define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -32,7 +32,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check signed register comparison, which can't use CLGFR.
 define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clgfr
 ; CHECK: br %r14
   %i2 = zext i32 %unext to i64
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation
 define double @f4(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clgfr
 ; CHECK: br %r14
   %i2 = and i64 %unext, 4294967295
@@ -54,7 +54,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check register equality.
 define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -67,7 +67,7 @@ define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation
 define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check register inequality.
 define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -93,7 +93,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation
 define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -106,7 +106,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check unsigned comparisonn with memory.
 define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -120,7 +120,7 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check signed comparison with memory.
 define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clgf
 ; CHECK: br %r14
   %unext = load i32 *%ptr
@@ -132,7 +132,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory equality.
 define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -146,7 +146,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory inequality.
 define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -160,7 +160,7 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned CLGF range.
 define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: clgf %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -176,7 +176,7 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: agfi %r3, 524288
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -192,7 +192,7 @@ define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CLGF range.
 define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: clgf %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -207,7 +207,7 @@ define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the low end of the CLGF range.
 define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: clgf %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -223,7 +223,7 @@ define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: agfi %r3, -524292
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -239,7 +239,7 @@ define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check that CLGF allows an index.
 define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: clgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -256,7 +256,7 @@ define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
 
 ; Check that comparisons of spilled values can use CLGF rather than CLGFR.
 define i64 @f19(i32 *%ptr0) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: clgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-07.ll b/test/CodeGen/SystemZ/int-cmp-07.ll
index 48ccf5cb30b..3308cb0fb90 100644
--- a/test/CodeGen/SystemZ/int-cmp-07.ll
+++ b/test/CodeGen/SystemZ/int-cmp-07.ll
@@ -4,7 +4,7 @@
 
 ; Check CGR.
 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgrjl %r2, %r3
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
 
 ; Check CG with no displacement.
 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cg %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -28,7 +28,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 
 ; Check the high end of the aligned CG range.
 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cg %r2, 524280(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the high end of the negative aligned CG range.
 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cg %r2, -8(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -72,7 +72,7 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the low end of the CG range.
 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cg %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -87,7 +87,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: cg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -102,7 +102,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check that CG allows an index.
 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-08.ll b/test/CodeGen/SystemZ/int-cmp-08.ll
index b091ba67e1e..e68a0fefa04 100644
--- a/test/CodeGen/SystemZ/int-cmp-08.ll
+++ b/test/CodeGen/SystemZ/int-cmp-08.ll
@@ -4,7 +4,7 @@
 
 ; Check CLGR.
 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -16,7 +16,7 @@ define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
 
 ; Check CLG with no displacement.
 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clg %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -29,7 +29,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 
 ; Check the high end of the aligned CLG range.
 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clg %r2, 524280(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: clg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -59,7 +59,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the high end of the negative aligned CLG range.
 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clg %r2, -8(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -73,7 +73,7 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the low end of the CLG range.
 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clg %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -88,7 +88,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: clg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -103,7 +103,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check that CLG allows an index.
 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-09.ll b/test/CodeGen/SystemZ/int-cmp-09.ll
index 8fb0e7c41a4..66c9d8df308 100644
--- a/test/CodeGen/SystemZ/int-cmp-09.ll
+++ b/test/CodeGen/SystemZ/int-cmp-09.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i32 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cijl %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i32 %i1) {
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i32 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cijl %r2, 1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the CIJ range.
 define double @f3(double %a, double %b, i32 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cijl %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define double @f3(double %a, double %b, i32 %i1) {
 
 ; Check the next value up, which must use CHI instead.
 define double @f4(double %a, double %b, i32 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chi %r2, 128
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -49,7 +49,7 @@ define double @f4(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the CHI range.
 define double @f5(double %a, double %b, i32 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: chi %r2, 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i32 %i1) {
 
 ; Check the next value up, which must use CFI.
 define double @f6(double %a, double %b, i32 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cfi %r2, 32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the signed 32-bit range.
 define double @f7(double %a, double %b, i32 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -85,7 +85,7 @@ define double @f7(double %a, double %b, i32 %i1) {
 
 ; Check the next value up, which should be treated as a negative value.
 define double @f8(double %a, double %b, i32 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -97,7 +97,7 @@ define double @f8(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the negative CIJ range.
 define double @f9(double %a, double %b, i32 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cijl %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f9(double %a, double %b, i32 %i1) {
 
 ; Check the low end of the CIJ range.
 define double @f10(double %a, double %b, i32 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cijl %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define double @f10(double %a, double %b, i32 %i1) {
 
 ; Check the next value down, which must use CHI instead.
 define double @f11(double %a, double %b, i32 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: chi %r2, -129
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -131,7 +131,7 @@ define double @f11(double %a, double %b, i32 %i1) {
 
 ; Check the low end of the CHI range.
 define double @f12(double %a, double %b, i32 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: chi %r2, -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -143,7 +143,7 @@ define double @f12(double %a, double %b, i32 %i1) {
 
 ; Check the next value down, which must use CFI instead.
 define double @f13(double %a, double %b, i32 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cfi %r2, -32769
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -155,7 +155,7 @@ define double @f13(double %a, double %b, i32 %i1) {
 
 ; Check the low end of the signed 32-bit range.
 define double @f14(double %a, double %b, i32 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f14(double %a, double %b, i32 %i1) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f15(double %a, double %b, i32 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-10.ll b/test/CodeGen/SystemZ/int-cmp-10.ll
index 937b1bccffa..e30e014319d 100644
--- a/test/CodeGen/SystemZ/int-cmp-10.ll
+++ b/test/CodeGen/SystemZ/int-cmp-10.ll
@@ -5,7 +5,7 @@
 ; Check a value near the low end of the range.  We use CFI for comparisons
 ; with zero, or things that are equivalent to them.
 define double @f1(double %a, double %b, i32 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clfi %r2, 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i32 %i1) {
 
 ; Check a value near the high end of the range.
 define double @f2(double %a, double %b, i32 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clfi %r2, 4294967280
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-11.ll b/test/CodeGen/SystemZ/int-cmp-11.ll
index a0f598e9d0f..8dd2ebcfbf1 100644
--- a/test/CodeGen/SystemZ/int-cmp-11.ll
+++ b/test/CodeGen/SystemZ/int-cmp-11.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgijl %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgijl %r2, 1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGIJ range.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cgijl %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define double @f3(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGHI instead.
 define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -49,7 +49,7 @@ define double @f4(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGHI range.
 define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGFI.
 define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGFI range.
 define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -85,7 +85,7 @@ define double @f7(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use register comparison.
 define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cgrjl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -96,7 +96,7 @@ define double @f8(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the negative CGIJ range.
 define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgijl %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define double @f9(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cgijl %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -118,7 +118,7 @@ define double @f10(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGHI instead.
 define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -130,7 +130,7 @@ define double @f11(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGHI range.
 define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -142,7 +142,7 @@ define double @f12(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGFI instead.
 define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -154,7 +154,7 @@ define double @f13(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGFI range.
 define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -166,7 +166,7 @@ define double @f14(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use register comparison.
 define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cgrjl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-12.ll b/test/CodeGen/SystemZ/int-cmp-12.ll
index 74d16cc251f..f57f6eca879 100644
--- a/test/CodeGen/SystemZ/int-cmp-12.ll
+++ b/test/CodeGen/SystemZ/int-cmp-12.ll
@@ -5,7 +5,7 @@
 ; Check a value near the low end of the range.  We use CGFI for comparisons
 ; with zero, or things that are equivalent to them.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgfi %r2, 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CLGFI range.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -29,7 +29,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use a register comparison.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clgr %r2,
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-13.ll b/test/CodeGen/SystemZ/int-cmp-13.ll
index 19bceecb626..53af0c868a2 100644
--- a/test/CodeGen/SystemZ/int-cmp-13.ll
+++ b/test/CodeGen/SystemZ/int-cmp-13.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgije %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGIJ range.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgije %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGHI instead.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGHI range.
 define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -50,7 +50,7 @@ define double @f4(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGFI.
 define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -62,7 +62,7 @@ define double @f5(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGFI range.
 define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -74,7 +74,7 @@ define double @f6(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which should use CLGFI instead.
 define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clgfi %r2, 2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CLGFI range.
 define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -98,7 +98,7 @@ define double @f8(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use a register comparison.
 define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgrje %r2,
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the negative CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cgije %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define double @f10(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGIJ range.
 define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cgije %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define double @f11(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGHI instead.
 define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -143,7 +143,7 @@ define double @f12(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGHI range.
 define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -155,7 +155,7 @@ define double @f13(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGFI instead.
 define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f14(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGFI range.
 define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -179,7 +179,7 @@ define double @f15(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use register comparison.
 define double @f16(double %a, double %b, i64 %i1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cgrje
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-14.ll b/test/CodeGen/SystemZ/int-cmp-14.ll
index 11b56adcdce..4dbd0ece3af 100644
--- a/test/CodeGen/SystemZ/int-cmp-14.ll
+++ b/test/CodeGen/SystemZ/int-cmp-14.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgijlh %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGIJ range.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgijlh %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGHI instead.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGHI range.
 define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -50,7 +50,7 @@ define double @f4(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGFI.
 define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -62,7 +62,7 @@ define double @f5(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGFI range.
 define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -74,7 +74,7 @@ define double @f6(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which should use CLGFI instead.
 define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clgfi %r2, 2147483648
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CLGFI range.
 define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -98,7 +98,7 @@ define double @f8(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use a register comparison.
 define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgrjlh %r2,
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the negative CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cgijlh %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define double @f10(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGIJ range.
 define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cgijlh %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define double @f11(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGHI instead.
 define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -143,7 +143,7 @@ define double @f12(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGHI range.
 define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -155,7 +155,7 @@ define double @f13(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGFI instead.
 define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f14(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGFI range.
 define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -179,7 +179,7 @@ define double @f15(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use register comparison.
 define double @f16(double %a, double %b, i64 %i1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cgrjlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-15.ll b/test/CodeGen/SystemZ/int-cmp-15.ll
index 1868c5746bb..48a068e49e8 100644
--- a/test/CodeGen/SystemZ/int-cmp-15.ll
+++ b/test/CodeGen/SystemZ/int-cmp-15.ll
@@ -4,7 +4,7 @@
 
 ; Check ordered comparisons near the low end of the unsigned 8-bit range.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check ordered comparisons near the high end of the unsigned 8-bit range.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for negative bytes.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 
 ; ...and an alternative form.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for non-negative bytes.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; ...and an alternative form.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the low end of the signed 8-bit range.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the low end of the unsigned 8-bit range.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the high end of the signed 8-bit range.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the high end of the unsigned 8-bit range.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -124,7 +124,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the CLI range.
 define double @f11(double %a, double %b, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cli 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -136,7 +136,7 @@ define double @f11(double %a, double %b, i8 *%src) {
 
 ; Check the next byte up, which should use CLIY instead of CLI.
 define double @f12(double %a, double %b, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cliy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -148,7 +148,7 @@ define double @f12(double %a, double %b, i8 *%src) {
 
 ; Check the high end of the CLIY range.
 define double @f13(double %a, double %b, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cliy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -161,7 +161,7 @@ define double @f13(double %a, double %b, i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f14(double %a, double %b, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: agfi %r2, 524288
 ; CHECK: cli 0(%r2), 127
 ; CHECK: br %r14
@@ -174,7 +174,7 @@ define double @f14(double %a, double %b, i8 *%src) {
 
 ; Check the high end of the negative CLIY range.
 define double @f15(double %a, double %b, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cliy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -186,7 +186,7 @@ define double @f15(double %a, double %b, i8 *%src) {
 
 ; Check the low end of the CLIY range.
 define double @f16(double %a, double %b, i8 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cliy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -199,7 +199,7 @@ define double @f16(double %a, double %b, i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f17(double %a, double %b, i8 *%src) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: agfi %r2, -524289
 ; CHECK: cli 0(%r2), 127
 ; CHECK: br %r14
@@ -212,7 +212,7 @@ define double @f17(double %a, double %b, i8 *%src) {
 
 ; Check that CLI does not allow an index
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: agr %r2, %r3
 ; CHECK: cli 4095(%r2), 127
 ; CHECK: br %r14
@@ -227,7 +227,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) {
 
 ; Check that CLIY does not allow an index
 define double @f19(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: agr %r2, %r3
 ; CHECK: cliy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-16.ll b/test/CodeGen/SystemZ/int-cmp-16.ll
index a2c9e87a3b2..be206d9c947 100644
--- a/test/CodeGen/SystemZ/int-cmp-16.ll
+++ b/test/CodeGen/SystemZ/int-cmp-16.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-17.ll b/test/CodeGen/SystemZ/int-cmp-17.ll
index 83e4d2d5e42..3df4ecc6680 100644
--- a/test/CodeGen/SystemZ/int-cmp-17.ll
+++ b/test/CodeGen/SystemZ/int-cmp-17.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-18.ll b/test/CodeGen/SystemZ/int-cmp-18.ll
index 99cf68a6b53..d03d6ac9a2c 100644
--- a/test/CodeGen/SystemZ/int-cmp-18.ll
+++ b/test/CodeGen/SystemZ/int-cmp-18.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-19.ll b/test/CodeGen/SystemZ/int-cmp-19.ll
index 4f84687ee80..b5f0856b400 100644
--- a/test/CodeGen/SystemZ/int-cmp-19.ll
+++ b/test/CodeGen/SystemZ/int-cmp-19.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-20.ll b/test/CodeGen/SystemZ/int-cmp-20.ll
index eb21bd1749d..7ecde77ddd4 100644
--- a/test/CodeGen/SystemZ/int-cmp-20.ll
+++ b/test/CodeGen/SystemZ/int-cmp-20.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the low end of the CLI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -78,7 +78,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; unlikely to occur in practice, we don't bother optimizing the second case,
 ; and simply ignore CLI for this range.  First check the low end of the range.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -90,7 +90,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -103,7 +103,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -117,7 +117,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -130,7 +130,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -144,7 +144,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f11(double %a, double %b, i8 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i8 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -169,7 +169,7 @@ define double @f12(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for nonnegative values.
 define double @f13(double %a, double %b, i8 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -182,7 +182,7 @@ define double @f13(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f14(double %a, double %b, i8 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -195,7 +195,7 @@ define double @f14(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for negative values.
 define double @f15(double %a, double %b, i8 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -208,7 +208,7 @@ define double @f15(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f16(double %a, double %b, i8 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-21.ll b/test/CodeGen/SystemZ/int-cmp-21.ll
index 9f81ad88e9c..ca9225dead9 100644
--- a/test/CodeGen/SystemZ/int-cmp-21.ll
+++ b/test/CodeGen/SystemZ/int-cmp-21.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the low end of the CLI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -78,7 +78,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; unlikely to occur in practice, we don't bother optimizing the second case,
 ; and simply ignore CLI for this range.  First check the low end of the range.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -90,7 +90,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -103,7 +103,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -117,7 +117,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -130,7 +130,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -144,7 +144,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f11(double %a, double %b, i8 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i8 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -169,7 +169,7 @@ define double @f12(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for nonnegative values.
 define double @f13(double %a, double %b, i8 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -182,7 +182,7 @@ define double @f13(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f14(double %a, double %b, i8 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -195,7 +195,7 @@ define double @f14(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for negative values.
 define double @f15(double %a, double %b, i8 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -208,7 +208,7 @@ define double @f15(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f16(double %a, double %b, i8 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-22.ll b/test/CodeGen/SystemZ/int-cmp-22.ll
index 7cecacb8712..ea16604bd4e 100644
--- a/test/CodeGen/SystemZ/int-cmp-22.ll
+++ b/test/CodeGen/SystemZ/int-cmp-22.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: chhsi 0(%r2), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check a value near the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chhsi 0(%r2), -1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check a value near the low end of the 16-bit signed range.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: chhsi 0(%r2), -32766
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the CHHSI range.
 define double @f6(double %a, double %b, i16 %i1, i16 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: chhsi 4094(%r3), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 %i1, i16 *%base) {
 
 ; Check the next halfword up, which needs separate address logic,
 define double @f7(double %a, double %b, i16 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: aghi %r2, 4096
 ; CHECK: chhsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -98,7 +98,7 @@ define double @f7(double %a, double %b, i16 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f8(double %a, double %b, i16 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, -2
 ; CHECK: chhsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -113,7 +113,7 @@ define double @f8(double %a, double %b, i16 *%base) {
 
 ; Check that CHHSI does not allow indices.
 define double @f9(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: chhsi 0({{%r[23]}}), 0
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-23.ll b/test/CodeGen/SystemZ/int-cmp-23.ll
index 2ca89c54281..99fe74b1c78 100644
--- a/test/CodeGen/SystemZ/int-cmp-23.ll
+++ b/test/CodeGen/SystemZ/int-cmp-23.ll
@@ -4,7 +4,7 @@
 
 ; Check a value near the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check a value near the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the CLHHSI range.
 define double @f3(double %a, double %b, i16 %i1, i16 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 4094(%r3), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 %i1, i16 *%base) {
 
 ; Check the next halfword up, which needs separate address logic,
 define double @f4(double %a, double %b, i16 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -59,7 +59,7 @@ define double @f4(double %a, double %b, i16 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f5(double %a, double %b, i16 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -2
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -74,7 +74,7 @@ define double @f5(double %a, double %b, i16 *%base) {
 
 ; Check that CLHHSI does not allow indices.
 define double @f6(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clhhsi 0({{%r[23]}}), 1
 ; CHECK-NEXT: jh
diff --git a/test/CodeGen/SystemZ/int-cmp-24.ll b/test/CodeGen/SystemZ/int-cmp-24.ll
index 01cc7b3103b..1a8e587b034 100644
--- a/test/CodeGen/SystemZ/int-cmp-24.ll
+++ b/test/CodeGen/SystemZ/int-cmp-24.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-25.ll b/test/CodeGen/SystemZ/int-cmp-25.ll
index 8ea8d6c3ae3..50803df1ba9 100644
--- a/test/CodeGen/SystemZ/int-cmp-25.ll
+++ b/test/CodeGen/SystemZ/int-cmp-25.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-26.ll b/test/CodeGen/SystemZ/int-cmp-26.ll
index 9eb02f4d656..60778654b27 100644
--- a/test/CodeGen/SystemZ/int-cmp-26.ll
+++ b/test/CodeGen/SystemZ/int-cmp-26.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-27.ll b/test/CodeGen/SystemZ/int-cmp-27.ll
index 3a16e9ed9b8..3102f5c5faa 100644
--- a/test/CodeGen/SystemZ/int-cmp-27.ll
+++ b/test/CodeGen/SystemZ/int-cmp-27.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-28.ll b/test/CodeGen/SystemZ/int-cmp-28.ll
index d40a95d691d..c3b905974eb 100644
--- a/test/CodeGen/SystemZ/int-cmp-28.ll
+++ b/test/CodeGen/SystemZ/int-cmp-28.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-29.ll b/test/CodeGen/SystemZ/int-cmp-29.ll
index 221bbcf7ea8..1b40d8cfb2a 100644
--- a/test/CodeGen/SystemZ/int-cmp-29.ll
+++ b/test/CodeGen/SystemZ/int-cmp-29.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-30.ll b/test/CodeGen/SystemZ/int-cmp-30.ll
index 507191b96e2..6c9498cb332 100644
--- a/test/CodeGen/SystemZ/int-cmp-30.ll
+++ b/test/CodeGen/SystemZ/int-cmp-30.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLHHSI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the low end of the CLHHSI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -79,7 +79,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; and simply ignore CLHHSI for this range.  First check the low end of the
 ; range.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -91,7 +91,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -104,7 +104,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -118,7 +118,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -146,7 +146,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f11(double %a, double %b, i16 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: chhsi 0(%r2), -2
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -160,7 +160,7 @@ define double @f11(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i16 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -173,7 +173,7 @@ define double @f12(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CHHSI range, using sign
 ; extension.
 define double @f13(double %a, double %b, i16 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define double @f13(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f14(double %a, double %b, i16 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -200,7 +200,7 @@ define double @f14(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CHHSI range, using sign
 ; extension.
 define double @f15(double %a, double %b, i16 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: chhsi 0(%r2), -32767
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -214,7 +214,7 @@ define double @f15(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison below the low end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f16(double %a, double %b, i16 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-31.ll b/test/CodeGen/SystemZ/int-cmp-31.ll
index a70ce2b7b30..21539f20470 100644
--- a/test/CodeGen/SystemZ/int-cmp-31.ll
+++ b/test/CodeGen/SystemZ/int-cmp-31.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLHHSI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the low end of the CLHHSI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -79,7 +79,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; and simply ignore CLHHSI for this range.  First check the low end of the
 ; range.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -91,7 +91,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -104,7 +104,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -118,7 +118,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -146,7 +146,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f11(double %a, double %b, i16 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: chhsi 0(%r2), -2
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -160,7 +160,7 @@ define double @f11(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i16 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -173,7 +173,7 @@ define double @f12(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CHHSI range, using sign
 ; extension.
 define double @f13(double %a, double %b, i16 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define double @f13(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f14(double %a, double %b, i16 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -200,7 +200,7 @@ define double @f14(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CHHSI range, using sign
 ; extension.
 define double @f15(double %a, double %b, i16 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: chhsi 0(%r2), -32767
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -214,7 +214,7 @@ define double @f15(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison below the low end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f16(double %a, double %b, i16 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-32.ll b/test/CodeGen/SystemZ/int-cmp-32.ll
index f79182b91ec..96398dd8414 100644
--- a/test/CodeGen/SystemZ/int-cmp-32.ll
+++ b/test/CodeGen/SystemZ/int-cmp-32.ll
@@ -4,7 +4,7 @@
 
 ; Check ordered comparisons with 0.
 define double @f1(double %a, double %b, i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with 1.
 define double @f2(double %a, double %b, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: chsi 0(%r2), 1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chsi 0(%r2), 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CHSI.
 define double @f4(double %a, double %b, i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -54,7 +54,7 @@ define double @f4(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with -1.
 define double @f5(double %a, double %b, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: chsi 0(%r2), -1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -67,7 +67,7 @@ define double @f5(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with the low end of the 16-bit signed range.
 define double @f6(double %a, double %b, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: chsi 0(%r2), -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value down, which can't use CHSI.
 define double @f7(double %a, double %b, i32 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -91,7 +91,7 @@ define double @f7(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with 0.
 define double @f8(double %a, double %b, i32 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -104,7 +104,7 @@ define double @f8(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with 1.
 define double @f9(double %a, double %b, i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: chsi 0(%r2), 1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -117,7 +117,7 @@ define double @f9(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with the high end of the signed 16-bit range.
 define double @f10(double %a, double %b, i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: chsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -130,7 +130,7 @@ define double @f10(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CHSI.
 define double @f11(double %a, double %b, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -141,7 +141,7 @@ define double @f11(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with -1.
 define double @f12(double %a, double %b, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: chsi 0(%r2), -1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -154,7 +154,7 @@ define double @f12(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with the low end of the 16-bit signed range.
 define double @f13(double %a, double %b, i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: chsi 0(%r2), -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f13(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f14(double %a, double %b, i32 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -178,7 +178,7 @@ define double @f14(double %a, double %b, i32 *%ptr) {
 
 ; Check the high end of the CHSI range.
 define double @f15(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: chsi 4092(%r3), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -192,7 +192,7 @@ define double @f15(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which needs separate address logic,
 define double @f16(double %a, double %b, i32 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: aghi %r2, 4096
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -207,7 +207,7 @@ define double @f16(double %a, double %b, i32 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f17(double %a, double %b, i32 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: aghi %r2, -4
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -222,7 +222,7 @@ define double @f17(double %a, double %b, i32 *%base) {
 
 ; Check that CHSI does not allow indices.
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: chsi 0({{%r[23]}}), 0
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-33.ll b/test/CodeGen/SystemZ/int-cmp-33.ll
index 2c1a26ed52b..e5a653b3815 100644
--- a/test/CodeGen/SystemZ/int-cmp-33.ll
+++ b/test/CodeGen/SystemZ/int-cmp-33.ll
@@ -5,7 +5,7 @@
 ; Check ordered comparisons with a constant near the low end of the unsigned
 ; 16-bit range.
 define double @f1(double %a, double %b, i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clfhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clfhsi 0(%r2), 65535
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CLFHSI.
 define double @f3(double %a, double %b, i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i32 *%ptr) {
 ; Check equality comparisons with 32768, the lowest value for which
 ; we prefer CLFHSI to CHSI.
 define double @f4(double %a, double %b, i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clfhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with the high end of the unsigned 16-bit range.
 define double @f5(double %a, double %b, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clfhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CLFHSI.
 define double @f6(double %a, double %b, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i32 *%ptr) {
 
 ; Check the high end of the CLFHSI range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clfhsi 4092(%r3), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which needs separate address logic,
 define double @f8(double %a, double %b, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clfhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -109,7 +109,7 @@ define double @f8(double %a, double %b, i32 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f9(double %a, double %b, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -4
 ; CHECK: clfhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -124,7 +124,7 @@ define double @f9(double %a, double %b, i32 *%base) {
 
 ; Check that CLFHSI does not allow indices.
 define double @f10(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clfhsi 0({{%r[23]}}), 1
 ; CHECK-NEXT: jh
diff --git a/test/CodeGen/SystemZ/int-cmp-34.ll b/test/CodeGen/SystemZ/int-cmp-34.ll
index ff0914a3e56..53a5c766417 100644
--- a/test/CodeGen/SystemZ/int-cmp-34.ll
+++ b/test/CodeGen/SystemZ/int-cmp-34.ll
@@ -4,7 +4,7 @@
 
 ; Check ordered comparisons with 0.
 define double @f1(double %a, double %b, i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with 1.
 define double @f2(double %a, double %b, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cghsi 0(%r2), 1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghsi 0(%r2), 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CGHSI.
 define double @f4(double %a, double %b, i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -54,7 +54,7 @@ define double @f4(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with -1.
 define double @f5(double %a, double %b, i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cghsi 0(%r2), -1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -67,7 +67,7 @@ define double @f5(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with the low end of the 16-bit signed range.
 define double @f6(double %a, double %b, i64 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cghsi 0(%r2), -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f7(double %a, double %b, i64 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -91,7 +91,7 @@ define double @f7(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with 0.
 define double @f8(double %a, double %b, i64 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -104,7 +104,7 @@ define double @f8(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with 1.
 define double @f9(double %a, double %b, i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cghsi 0(%r2), 1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -117,7 +117,7 @@ define double @f9(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with the high end of the signed 16-bit range.
 define double @f10(double %a, double %b, i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cghsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -130,7 +130,7 @@ define double @f10(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CGHSI.
 define double @f11(double %a, double %b, i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -141,7 +141,7 @@ define double @f11(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with -1.
 define double @f12(double %a, double %b, i64 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghsi 0(%r2), -1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -154,7 +154,7 @@ define double @f12(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with the low end of the 16-bit signed range.
 define double @f13(double %a, double %b, i64 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cghsi 0(%r2), -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f13(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f14(double %a, double %b, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -178,7 +178,7 @@ define double @f14(double %a, double %b, i64 *%ptr) {
 
 ; Check the high end of the CGHSI range.
 define double @f15(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cghsi 4088(%r3), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -192,7 +192,7 @@ define double @f15(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the next doubleword up, which needs separate address logic,
 define double @f16(double %a, double %b, i64 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: aghi %r2, 4096
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -207,7 +207,7 @@ define double @f16(double %a, double %b, i64 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f17(double %a, double %b, i64 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: aghi %r2, -8
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -222,7 +222,7 @@ define double @f17(double %a, double %b, i64 *%base) {
 
 ; Check that CGHSI does not allow indices.
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: cghsi 0({{%r[23]}}), 0
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-35.ll b/test/CodeGen/SystemZ/int-cmp-35.ll
index b74d67ed1f8..539248a86a7 100644
--- a/test/CodeGen/SystemZ/int-cmp-35.ll
+++ b/test/CodeGen/SystemZ/int-cmp-35.ll
@@ -5,7 +5,7 @@
 ; Check ordered comparisons with a constant near the low end of the unsigned
 ; 16-bit range.
 define double @f1(double %a, double %b, i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clghsi 0(%r2), 2
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clghsi 0(%r2), 65535
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CLGHSI.
 define double @f3(double %a, double %b, i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 *%ptr) {
 ; Check equality comparisons with 32768, the lowest value for which
 ; we prefer CLGHSI to CGHSI.
 define double @f4(double %a, double %b, i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clghsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with the high end of the unsigned 16-bit range.
 define double @f5(double %a, double %b, i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clghsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CLGHSI.
 define double @f6(double %a, double %b, i64 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i64 *%ptr) {
 
 ; Check the high end of the CLGHSI range.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clghsi 4088(%r3), 2
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the next doubleword up, which needs separate address logic,
 define double @f8(double %a, double %b, i64 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clghsi 0(%r2), 2
 ; CHECK-NEXT: jl
@@ -109,7 +109,7 @@ define double @f8(double %a, double %b, i64 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f9(double %a, double %b, i64 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -8
 ; CHECK: clghsi 0(%r2), 2
 ; CHECK-NEXT: jl
@@ -124,7 +124,7 @@ define double @f9(double %a, double %b, i64 *%base) {
 
 ; Check that CLGHSI does not allow indices.
 define double @f10(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clghsi 0({{%r[23]}}), 2
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-36.ll b/test/CodeGen/SystemZ/int-cmp-36.ll
index df0e337cc8b..831b05fdf1f 100644
--- a/test/CodeGen/SystemZ/int-cmp-36.ll
+++ b/test/CodeGen/SystemZ/int-cmp-36.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparison.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check unsigned comparison, which cannot use CHRL.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: chrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: ch %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-37.ll b/test/CodeGen/SystemZ/int-cmp-37.ll
index 272df713136..97d210e5f56 100644
--- a/test/CodeGen/SystemZ/int-cmp-37.ll
+++ b/test/CodeGen/SystemZ/int-cmp-37.ll
@@ -8,7 +8,7 @@
 
 ; Check unsigned comparison.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check signed comparison.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clhrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: clr %r2, [[VAL]]
diff --git a/test/CodeGen/SystemZ/int-cmp-38.ll b/test/CodeGen/SystemZ/int-cmp-38.ll
index 54f325e6740..d5a852c0c4e 100644
--- a/test/CodeGen/SystemZ/int-cmp-38.ll
+++ b/test/CodeGen/SystemZ/int-cmp-38.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparisons.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: crl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ exit:
 
 ; Check unsigned comparisons.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 
 ; Check equality, which can use CRL or CLRL.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}rl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ exit:
 
 ; ...likewise inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}rl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: c %r2, 0([[REG]])
 ; CHECK-NEXT: jl
@@ -99,7 +99,7 @@ exit:
 
 ; Repeat f2 with an unaligned address.
 define i32 @f6(i32 %src1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cl %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-39.ll b/test/CodeGen/SystemZ/int-cmp-39.ll
index e99b240af8a..d4420583c01 100644
--- a/test/CodeGen/SystemZ/int-cmp-39.ll
+++ b/test/CodeGen/SystemZ/int-cmp-39.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check unsigned comparison, which cannot use CHRL.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: cghrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: cgh %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-40.ll b/test/CodeGen/SystemZ/int-cmp-40.ll
index 2d33c8fcd5e..6dab2db0d90 100644
--- a/test/CodeGen/SystemZ/int-cmp-40.ll
+++ b/test/CodeGen/SystemZ/int-cmp-40.ll
@@ -8,7 +8,7 @@
 
 ; Check unsigned comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check signed comparison.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clghrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llgh [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: clgr %r2, [[VAL]]
diff --git a/test/CodeGen/SystemZ/int-cmp-41.ll b/test/CodeGen/SystemZ/int-cmp-41.ll
index f68638a1b8a..099681db42a 100644
--- a/test/CodeGen/SystemZ/int-cmp-41.ll
+++ b/test/CodeGen/SystemZ/int-cmp-41.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check unsigned comparison, which cannot use CHRL.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: cgfrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cgf %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-42.ll b/test/CodeGen/SystemZ/int-cmp-42.ll
index dd3cb4a398f..26a268dda2b 100644
--- a/test/CodeGen/SystemZ/int-cmp-42.ll
+++ b/test/CodeGen/SystemZ/int-cmp-42.ll
@@ -8,7 +8,7 @@
 
 ; Check unsigned comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check signed comparison.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clgfrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: clgf %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-43.ll b/test/CodeGen/SystemZ/int-cmp-43.ll
index 7d4adcab061..e5e13900fd7 100644
--- a/test/CodeGen/SystemZ/int-cmp-43.ll
+++ b/test/CodeGen/SystemZ/int-cmp-43.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparisons.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ exit:
 
 ; Check unsigned comparisons.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clgrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 
 ; Check equality, which can use CRL or CLRL.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}grl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ exit:
 
 ; ...likewise inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}grl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cg %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-const-01.ll b/test/CodeGen/SystemZ/int-const-01.ll
index e714e9d1934..e94c05897fa 100644
--- a/test/CodeGen/SystemZ/int-const-01.ll
+++ b/test/CodeGen/SystemZ/int-const-01.ll
@@ -6,7 +6,7 @@ declare void @foo(i32, i32, i32, i32)
 
 ; Check 0.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r2, 0
 ; CHECK: br %r14
   ret i32 0
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Check the high end of the LHI range.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r2, 32767
 ; CHECK: br %r14
   ret i32 32767
@@ -22,7 +22,7 @@ define i32 @f2() {
 
 ; Check the next value up, which must use LLILL instead.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llill %r2, 32768
 ; CHECK: br %r14
   ret i32 32768
@@ -30,7 +30,7 @@ define i32 @f3() {
 
 ; Check the high end of the LLILL range.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llill %r2, 65535
 ; CHECK: br %r14
   ret i32 65535
@@ -38,7 +38,7 @@ define i32 @f4() {
 
 ; Check the first useful LLILH value, which is the next one up.
 define i32 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh %r2, 1
 ; CHECK: br %r14
   ret i32 65536
@@ -46,7 +46,7 @@ define i32 @f5() {
 
 ; Check the first useful IILF value, which is the next one up again.
 define i32 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: iilf %r2, 65537
 ; CHECK: br %r14
   ret i32 65537
@@ -54,7 +54,7 @@ define i32 @f6() {
 
 ; Check the high end of the LLILH range.
 define i32 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilh %r2, 65535
 ; CHECK: br %r14
   ret i32 -65536
@@ -62,7 +62,7 @@ define i32 @f7() {
 
 ; Check the next value up, which must use IILF.
 define i32 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: iilf %r2, 4294901761
 ; CHECK: br %r14
   ret i32 -65535
@@ -70,7 +70,7 @@ define i32 @f8() {
 
 ; Check the highest useful IILF value, 0xffff7fff
 define i32 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: iilf %r2, 4294934527
 ; CHECK: br %r14
   ret i32 -32769
@@ -78,7 +78,7 @@ define i32 @f9() {
 
 ; Check the next value up, which should use LHI.
 define i32 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lhi %r2, -32768
 ; CHECK: br %r14
   ret i32 -32768
@@ -86,7 +86,7 @@ define i32 @f10() {
 
 ; Check -1.
 define i32 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lhi %r2, -1
 ; CHECK: br %r14
   ret i32 -1
@@ -94,7 +94,7 @@ define i32 @f11() {
 
 ; Check that constant loads are rematerialized.
 define i32 @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-DAG: lhi %r2, 42
 ; CHECK-DAG: llill %r3, 32768
 ; CHECK-DAG: llilh %r4, 1
diff --git a/test/CodeGen/SystemZ/int-const-02.ll b/test/CodeGen/SystemZ/int-const-02.ll
index ba143c772d4..e71abc69b3b 100644
--- a/test/CodeGen/SystemZ/int-const-02.ll
+++ b/test/CodeGen/SystemZ/int-const-02.ll
@@ -6,7 +6,7 @@ declare void @foo(i64, i64, i64, i64)
 
 ; Check 0.
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghi %r2, 0
 ; CHECK-NEXT: br %r14
   ret i64 0
@@ -14,7 +14,7 @@ define i64 @f1() {
 
 ; Check the high end of the LGHI range.
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lghi %r2, 32767
 ; CHECK-NEXT: br %r14
   ret i64 32767
@@ -22,7 +22,7 @@ define i64 @f2() {
 
 ; Check the next value up, which must use LLILL instead.
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llill %r2, 32768
 ; CHECK-NEXT: br %r14
   ret i64 32768
@@ -30,7 +30,7 @@ define i64 @f3() {
 
 ; Check the high end of the LLILL range.
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llill %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 65535
@@ -38,7 +38,7 @@ define i64 @f4() {
 
 ; Check the first useful LLILH value, which is the next one up.
 define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh %r2, 1
 ; CHECK-NEXT: br %r14
   ret i64 65536
@@ -46,7 +46,7 @@ define i64 @f5() {
 
 ; Check the first useful LGFI value, which is the next one up again.
 define i64 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgfi %r2, 65537
 ; CHECK-NEXT: br %r14
   ret i64 65537
@@ -54,7 +54,7 @@ define i64 @f6() {
 
 ; Check the high end of the LGFI range.
 define i64 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgfi %r2, 2147483647
 ; CHECK-NEXT: br %r14
   ret i64 2147483647
@@ -62,7 +62,7 @@ define i64 @f7() {
 
 ; Check the next value up, which should use LLILH instead.
 define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llilh %r2, 32768
 ; CHECK-NEXT: br %r14
   ret i64 2147483648
@@ -70,7 +70,7 @@ define i64 @f8() {
 
 ; Check the next value up again, which should use LLILF.
 define i64 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: llilf %r2, 2147483649
 ; CHECK-NEXT: br %r14
   ret i64 2147483649
@@ -78,7 +78,7 @@ define i64 @f9() {
 
 ; Check the high end of the LLILH range.
 define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llilh %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 4294901760
@@ -86,7 +86,7 @@ define i64 @f10() {
 
 ; Check the next value up, which must use LLILF.
 define i64 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llilf %r2, 4294901761
 ; CHECK-NEXT: br %r14
   ret i64 4294901761
@@ -94,7 +94,7 @@ define i64 @f11() {
 
 ; Check the high end of the LLILF range.
 define i64 @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: llilf %r2, 4294967295
 ; CHECK-NEXT: br %r14
   ret i64 4294967295
@@ -102,7 +102,7 @@ define i64 @f12() {
 
 ; Check the lowest useful LLIHL value, which is the next one up.
 define i64 @f13() {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: br %r14
   ret i64 4294967296
@@ -110,7 +110,7 @@ define i64 @f13() {
 
 ; Check the next value up, which must use a combination of two instructions.
 define i64 @f14() {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oill %r2, 1
 ; CHECK-NEXT: br %r14
@@ -119,7 +119,7 @@ define i64 @f14() {
 
 ; Check the high end of the OILL range.
 define i64 @f15() {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oill %r2, 65535
 ; CHECK-NEXT: br %r14
@@ -128,7 +128,7 @@ define i64 @f15() {
 
 ; Check the next value up, which should use OILH instead.
 define i64 @f16() {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilh %r2, 1
 ; CHECK-NEXT: br %r14
@@ -137,7 +137,7 @@ define i64 @f16() {
 
 ; Check the next value up again, which should use OILF.
 define i64 @f17() {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilf %r2, 65537
 ; CHECK-NEXT: br %r14
@@ -146,7 +146,7 @@ define i64 @f17() {
 
 ; Check the high end of the OILH range.
 define i64 @f18() {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilh %r2, 65535
 ; CHECK-NEXT: br %r14
@@ -155,7 +155,7 @@ define i64 @f18() {
 
 ; Check the high end of the OILF range.
 define i64 @f19() {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilf %r2, 4294967295
 ; CHECK-NEXT: br %r14
@@ -164,7 +164,7 @@ define i64 @f19() {
 
 ; Check the high end of the LLIHL range.
 define i64 @f20() {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: llihl %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 281470681743360
@@ -172,7 +172,7 @@ define i64 @f20() {
 
 ; Check the lowest useful LLIHH value, which is 1<<32 greater than the above.
 define i64 @f21() {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: llihh %r2, 1
 ; CHECK-NEXT: br %r14
   ret i64 281474976710656
@@ -180,7 +180,7 @@ define i64 @f21() {
 
 ; Check the lowest useful LLIHF value, which is 1<<32 greater again.
 define i64 @f22() {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: llihf %r2, 65537
 ; CHECK-NEXT: br %r14
   ret i64 281479271677952
@@ -188,7 +188,7 @@ define i64 @f22() {
 
 ; Check the highest end of the LLIHH range.
 define i64 @f23() {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: llihh %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 -281474976710656
@@ -196,7 +196,7 @@ define i64 @f23() {
 
 ; Check the next value up, which must use OILL too.
 define i64 @f24() {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: llihh %r2, 65535
 ; CHECK-NEXT: oill %r2, 1
 ; CHECK-NEXT: br %r14
@@ -205,7 +205,7 @@ define i64 @f24() {
 
 ; Check the high end of the LLIHF range.
 define i64 @f25() {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK: llihf %r2, 4294967295
 ; CHECK-NEXT: br %r14
   ret i64 -4294967296
@@ -213,7 +213,7 @@ define i64 @f25() {
 
 ; Check -1.
 define i64 @f26() {
-; CHECK: f26:
+; CHECK-LABEL: f26:
 ; CHECK: lghi %r2, -1
 ; CHECK-NEXT: br %r14
   ret i64 -1
@@ -221,7 +221,7 @@ define i64 @f26() {
 
 ; Check the low end of the LGHI range.
 define i64 @f27() {
-; CHECK: f27:
+; CHECK-LABEL: f27:
 ; CHECK: lghi %r2, -32768
 ; CHECK-NEXT: br %r14
   ret i64 -32768
@@ -229,7 +229,7 @@ define i64 @f27() {
 
 ; Check the next value down, which must use LGFI instead.
 define i64 @f28() {
-; CHECK: f28:
+; CHECK-LABEL: f28:
 ; CHECK: lgfi %r2, -32769
 ; CHECK-NEXT: br %r14
   ret i64 -32769
@@ -237,7 +237,7 @@ define i64 @f28() {
 
 ; Check the low end of the LGFI range.
 define i64 @f29() {
-; CHECK: f29:
+; CHECK-LABEL: f29:
 ; CHECK: lgfi %r2, -2147483648
 ; CHECK-NEXT: br %r14
   ret i64 -2147483648
@@ -245,7 +245,7 @@ define i64 @f29() {
 
 ; Check the next value down, which needs a two-instruction sequence.
 define i64 @f30() {
-; CHECK: f30:
+; CHECK-LABEL: f30:
 ; CHECK: llihf %r2, 4294967295
 ; CHECK-NEXT: oilf %r2, 2147483647
 ; CHECK-NEXT: br %r14
@@ -254,7 +254,7 @@ define i64 @f30() {
 
 ; Check that constant loads are rematerialized.
 define i64 @f31() {
-; CHECK: f31:
+; CHECK-LABEL: f31:
 ; CHECK-DAG: lghi %r2, 42
 ; CHECK-DAG: lgfi %r3, 65537
 ; CHECK-DAG: llilf %r4, 2147483649
diff --git a/test/CodeGen/SystemZ/int-const-03.ll b/test/CodeGen/SystemZ/int-const-03.ll
index 807b7e463ce..78db9637e4e 100644
--- a/test/CodeGen/SystemZ/int-const-03.ll
+++ b/test/CodeGen/SystemZ/int-const-03.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned range.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: br %r14
   store i8 0, i8 *%ptr
@@ -13,7 +13,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the high end of the signed range.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvi 0(%r2), 127
 ; CHECK: br %r14
   store i8 127, i8 *%ptr
@@ -22,7 +22,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the next value up.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   store i8 -128, i8 *%ptr
@@ -31,7 +31,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the high end of the unsigned range.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   store i8 255, i8 *%ptr
@@ -40,7 +40,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check -1.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   store i8 -1, i8 *%ptr
@@ -49,7 +49,7 @@ define void @f5(i8 *%ptr) {
 
 ; Check the low end of the signed range.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   store i8 -128, i8 *%ptr
@@ -58,7 +58,7 @@ define void @f6(i8 *%ptr) {
 
 ; Check the next value down.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvi 0(%r2), 127
 ; CHECK: br %r14
   store i8 -129, i8 *%ptr
@@ -67,7 +67,7 @@ define void @f7(i8 *%ptr) {
 
 ; Check the high end of the MVI range.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvi 4095(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -77,7 +77,7 @@ define void @f8(i8 *%src) {
 
 ; Check the next byte up, which should use MVIY instead of MVI.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mviy 4096(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -87,7 +87,7 @@ define void @f9(i8 *%src) {
 
 ; Check the high end of the MVIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mviy 524287(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -98,7 +98,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, 524288
 ; CHECK: mvi 0(%r2), 42
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define void @f11(i8 *%src) {
 
 ; Check the high end of the negative MVIY range.
 define void @f12(i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mviy -1(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -119,7 +119,7 @@ define void @f12(i8 *%src) {
 
 ; Check the low end of the MVIY range.
 define void @f13(i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: mviy -524288(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -130,7 +130,7 @@ define void @f13(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f14(i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: agfi %r2, -524289
 ; CHECK: mvi 0(%r2), 42
 ; CHECK: br %r14
@@ -141,7 +141,7 @@ define void @f14(i8 *%src) {
 
 ; Check that MVI does not allow an index
 define void @f15(i64 %src, i64 %index) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvi 4095(%r2), 42
 ; CHECK: br %r14
@@ -154,7 +154,7 @@ define void @f15(i64 %src, i64 %index) {
 
 ; Check that MVIY does not allow an index
 define void @f16(i64 %src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: agr %r2, %r3
 ; CHECK: mviy 4096(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-const-04.ll b/test/CodeGen/SystemZ/int-const-04.ll
index 41c7306c89a..c109faab20d 100644
--- a/test/CodeGen/SystemZ/int-const-04.ll
+++ b/test/CodeGen/SystemZ/int-const-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned range.
 define void @f1(i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvhhi 0(%r2), 0
 ; CHECK: br %r14
   store i16 0, i16 *%ptr
@@ -13,7 +13,7 @@ define void @f1(i16 *%ptr) {
 
 ; Check the high end of the signed range.
 define void @f2(i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvhhi 0(%r2), 32767
 ; CHECK: br %r14
   store i16 32767, i16 *%ptr
@@ -22,7 +22,7 @@ define void @f2(i16 *%ptr) {
 
 ; Check the next value up.
 define void @f3(i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvhhi 0(%r2), -32768
 ; CHECK: br %r14
   store i16 -32768, i16 *%ptr
@@ -31,7 +31,7 @@ define void @f3(i16 *%ptr) {
 
 ; Check the high end of the unsigned range.
 define void @f4(i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   store i16 65535, i16 *%ptr
@@ -40,7 +40,7 @@ define void @f4(i16 *%ptr) {
 
 ; Check -1.
 define void @f5(i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   store i16 -1, i16 *%ptr
@@ -49,7 +49,7 @@ define void @f5(i16 *%ptr) {
 
 ; Check the low end of the signed range.
 define void @f6(i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvhhi 0(%r2), -32768
 ; CHECK: br %r14
   store i16 -32768, i16 *%ptr
@@ -58,7 +58,7 @@ define void @f6(i16 *%ptr) {
 
 ; Check the next value down.
 define void @f7(i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvhhi 0(%r2), 32767
 ; CHECK: br %r14
   store i16 -32769, i16 *%ptr
@@ -67,7 +67,7 @@ define void @f7(i16 *%ptr) {
 
 ; Check the high end of the MVHHI range.
 define void @f8(i16 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvhhi 4094(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%a, i64 2047
@@ -78,7 +78,7 @@ define void @f8(i16 *%a) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i16 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mvhhi 0(%r2), 42
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define void @f9(i16 *%a) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f10(i16 *%a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: aghi %r2, -2
 ; CHECK: mvhhi 0(%r2), 42
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define void @f10(i16 *%a) {
 
 ; Check that MVHHI does not allow an index
 define void @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvhhi 0(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-const-05.ll b/test/CodeGen/SystemZ/int-const-05.ll
index b85fd6b6820..d0c85691493 100644
--- a/test/CodeGen/SystemZ/int-const-05.ll
+++ b/test/CodeGen/SystemZ/int-const-05.ll
@@ -4,7 +4,7 @@
 
 ; Check moves of zero.
 define void @f1(i32 *%a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   store i32 0, i32 *%a
@@ -13,7 +13,7 @@ define void @f1(i32 *%a) {
 
 ; Check the high end of the signed 16-bit range.
 define void @f2(i32 *%a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvhi 0(%r2), 32767
 ; CHECK: br %r14
   store i32 32767, i32 *%a
@@ -22,7 +22,7 @@ define void @f2(i32 *%a) {
 
 ; Check the next value up, which can't use MVHI.
 define void @f3(i32 *%a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: mvhi
 ; CHECK: br %r14
   store i32 32768, i32 *%a
@@ -31,7 +31,7 @@ define void @f3(i32 *%a) {
 
 ; Check moves of -1.
 define void @f4(i32 *%a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvhi 0(%r2), -1
 ; CHECK: br %r14
   store i32 -1, i32 *%a
@@ -40,7 +40,7 @@ define void @f4(i32 *%a) {
 
 ; Check the low end of the MVHI range.
 define void @f5(i32 *%a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhi 0(%r2), -32768
 ; CHECK: br %r14
   store i32 -32768, i32 *%a
@@ -49,7 +49,7 @@ define void @f5(i32 *%a) {
 
 ; Check the next value down, which can't use MVHI.
 define void @f6(i32 *%a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: mvhi
 ; CHECK: br %r14
   store i32 -32769, i32 *%a
@@ -58,7 +58,7 @@ define void @f6(i32 *%a) {
 
 ; Check the high end of the MVHI range.
 define void @f7(i32 *%a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvhi 4092(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%a, i64 1023
@@ -69,7 +69,7 @@ define void @f7(i32 *%a) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i32 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mvhi 0(%r2), 42
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define void @f8(i32 *%a) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f9(i32 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -4
 ; CHECK: mvhi 0(%r2), 42
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define void @f9(i32 *%a) {
 
 ; Check that MVHI does not allow an index
 define void @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvhi 0(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-const-06.ll b/test/CodeGen/SystemZ/int-const-06.ll
index 9f14347cf88..12a555c61e4 100644
--- a/test/CodeGen/SystemZ/int-const-06.ll
+++ b/test/CodeGen/SystemZ/int-const-06.ll
@@ -4,7 +4,7 @@
 
 ; Check moves of zero.
 define void @f1(i64 *%a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvghi 0(%r2), 0
 ; CHECK: br %r14
   store i64 0, i64 *%a
@@ -13,7 +13,7 @@ define void @f1(i64 *%a) {
 
 ; Check the high end of the signed 16-bit range.
 define void @f2(i64 *%a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvghi 0(%r2), 32767
 ; CHECK: br %r14
   store i64 32767, i64 *%a
@@ -22,7 +22,7 @@ define void @f2(i64 *%a) {
 
 ; Check the next value up, which can't use MVGHI.
 define void @f3(i64 *%a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: mvghi
 ; CHECK: br %r14
   store i64 32768, i64 *%a
@@ -31,7 +31,7 @@ define void @f3(i64 *%a) {
 
 ; Check moves of -1.
 define void @f4(i64 *%a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvghi 0(%r2), -1
 ; CHECK: br %r14
   store i64 -1, i64 *%a
@@ -40,7 +40,7 @@ define void @f4(i64 *%a) {
 
 ; Check the low end of the MVGHI range.
 define void @f5(i64 *%a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvghi 0(%r2), -32768
 ; CHECK: br %r14
   store i64 -32768, i64 *%a
@@ -49,7 +49,7 @@ define void @f5(i64 *%a) {
 
 ; Check the next value down, which can't use MVGHI.
 define void @f6(i64 *%a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: mvghi
 ; CHECK: br %r14
   store i64 -32769, i64 *%a
@@ -58,7 +58,7 @@ define void @f6(i64 *%a) {
 
 ; Check the high end of the MVGHI range.
 define void @f7(i64 *%a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvghi 4088(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%a, i64 511
@@ -69,7 +69,7 @@ define void @f7(i64 *%a) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i64 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mvghi 0(%r2), 42
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define void @f8(i64 *%a) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f9(i64 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -8
 ; CHECK: mvghi 0(%r2), 42
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define void @f9(i64 *%a) {
 
 ; Check that MVGHI does not allow an index
 define void @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvghi 0(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-conv-01.ll b/test/CodeGen/SystemZ/int-conv-01.ll
index 335cf7587df..e5c411cdec1 100644
--- a/test/CodeGen/SystemZ/int-conv-01.ll
+++ b/test/CodeGen/SystemZ/int-conv-01.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lbr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lbr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check LB with no displacement.
 define i32 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -34,7 +34,7 @@ define i32 @f3(i8 *%src) {
 
 ; Check the high end of the LB range.
 define i32 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -46,7 +46,7 @@ define i32 @f4(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i32 @f5(i8 *%src) {
 
 ; Check the high end of the negative LB range.
 define i32 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lb %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -69,7 +69,7 @@ define i32 @f6(i8 *%src) {
 
 ; Check the low end of the LB range.
 define i32 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lb %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -81,7 +81,7 @@ define i32 @f7(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524289
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f8(i8 *%src) {
 
 ; Check that LB allows an index
 define i32 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lb %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -107,7 +107,7 @@ define i32 @f9(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LBR.  We want
 ; to use LB if possible.
 define void @f10(i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lb {{%r[0-9]+}}, 16{{[37]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-02.ll b/test/CodeGen/SystemZ/int-conv-02.ll
index 05d1cd9e2a1..18cfd4a87fa 100644
--- a/test/CodeGen/SystemZ/int-conv-02.ll
+++ b/test/CodeGen/SystemZ/int-conv-02.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llcr %r2, %r2
 ; CHECK: br %r14
   %ext = and i32 %a, 255
@@ -33,7 +33,7 @@ define i32 @f3(i32 %a) {
 
 ; Check LLC with no displacement.
 define i32 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -43,7 +43,7 @@ define i32 @f4(i8 *%src) {
 
 ; Check the high end of the LLC range.
 define i32 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llc %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -55,7 +55,7 @@ define i32 @f5(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i32 @f6(i8 *%src) {
 
 ; Check the high end of the negative LLC range.
 define i32 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llc %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f7(i8 *%src) {
 
 ; Check the low end of the LLC range.
 define i32 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llc %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -90,7 +90,7 @@ define i32 @f8(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524289
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i32 @f9(i8 *%src) {
 
 ; Check that LLC allows an index
 define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llc %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -116,7 +116,7 @@ define i32 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLCR.  We want
 ; to use LLC if possible.
 define void @f11(i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llc {{%r[0-9]+}}, 16{{[37]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-03.ll b/test/CodeGen/SystemZ/int-conv-03.ll
index e3a2cdd7fa7..cad9581296a 100644
--- a/test/CodeGen/SystemZ/int-conv-03.ll
+++ b/test/CodeGen/SystemZ/int-conv-03.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgbr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgbr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a) {
 
 ; Check LGB with no displacement.
 define i64 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -34,7 +34,7 @@ define i64 @f3(i8 *%src) {
 
 ; Check the high end of the LGB range.
 define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgb %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -46,7 +46,7 @@ define i64 @f4(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i64 @f5(i8 *%src) {
 
 ; Check the high end of the negative LGB range.
 define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgb %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -69,7 +69,7 @@ define i64 @f6(i8 *%src) {
 
 ; Check the low end of the LGB range.
 define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgb %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -81,7 +81,7 @@ define i64 @f7(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524289
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i64 @f8(i8 *%src) {
 
 ; Check that LGB allows an index
 define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgb %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -107,7 +107,7 @@ define i64 @f9(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LGBR.  We want
 ; to use LGB if possible.
 define void @f10(i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lgb {{%r[0-9]+}}, 167(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-04.ll b/test/CodeGen/SystemZ/int-conv-04.ll
index c3d445a5756..1c6be7b6e8a 100644
--- a/test/CodeGen/SystemZ/int-conv-04.ll
+++ b/test/CodeGen/SystemZ/int-conv-04.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i32 %a to i8
@@ -14,7 +14,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %byte = trunc i64 %a to i8
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: br %r14
   %ext = and i64 %a, 255
@@ -33,7 +33,7 @@ define i64 @f3(i64 %a) {
 
 ; Check LLGC with no displacement.
 define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -43,7 +43,7 @@ define i64 @f4(i8 *%src) {
 
 ; Check the high end of the LLGC range.
 define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgc %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -55,7 +55,7 @@ define i64 @f5(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i8 *%src) {
 
 ; Check the high end of the negative LLGC range.
 define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgc %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -78,7 +78,7 @@ define i64 @f7(i8 *%src) {
 
 ; Check the low end of the LLGC range.
 define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgc %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -90,7 +90,7 @@ define i64 @f8(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524289
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i64 @f9(i8 *%src) {
 
 ; Check that LLGC allows an index
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgc %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -116,7 +116,7 @@ define i64 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLGCR.  We want
 ; to use LLGC if possible.
 define void @f11(i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llgc {{%r[0-9]+}}, 167(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-05.ll b/test/CodeGen/SystemZ/int-conv-05.ll
index b5f23af6f9e..5eade93ac58 100644
--- a/test/CodeGen/SystemZ/int-conv-05.ll
+++ b/test/CodeGen/SystemZ/int-conv-05.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i32 %a to i16
@@ -14,7 +14,7 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i64 %a to i16
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check the low end of the LH range.
 define i32 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -34,7 +34,7 @@ define i32 @f3(i16 *%src) {
 
 ; Check the high end of the LH range.
 define i32 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lh %r2, 4094(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -45,7 +45,7 @@ define i32 @f4(i16 *%src) {
 
 ; Check the next halfword up, which needs LHY rather than LH.
 define i32 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lhy %r2, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -56,7 +56,7 @@ define i32 @f5(i16 *%src) {
 
 ; Check the high end of the LHY range.
 define i32 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lhy %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -68,7 +68,7 @@ define i32 @f6(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define i32 @f7(i16 *%src) {
 
 ; Check the high end of the negative LHY range.
 define i32 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lhy %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -91,7 +91,7 @@ define i32 @f8(i16 *%src) {
 
 ; Check the low end of the LHY range.
 define i32 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lhy %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -103,7 +103,7 @@ define i32 @f9(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f10(i16 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524290
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -115,7 +115,7 @@ define i32 @f10(i16 *%src) {
 
 ; Check that LH allows an index
 define i32 @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lh %r2, 4094(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -128,7 +128,7 @@ define i32 @f11(i64 %src, i64 %index) {
 
 ; Check that LH allows an index
 define i32 @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lhy %r2, 4096(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -142,7 +142,7 @@ define i32 @f12(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LHR.  We want
 ; to use LH if possible.
 define void @f13(i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: lh {{%r[0-9]+}}, 16{{[26]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-06.ll b/test/CodeGen/SystemZ/int-conv-06.ll
index 90a142b7739..9c95badb2c0 100644
--- a/test/CodeGen/SystemZ/int-conv-06.ll
+++ b/test/CodeGen/SystemZ/int-conv-06.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llhr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i32 %a to i16
@@ -14,7 +14,7 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llhr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i64 %a to i16
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llhr %r2, %r2
 ; CHECK: br %r14
   %ext = and i32 %a, 65535
@@ -33,7 +33,7 @@ define i32 @f3(i32 %a) {
 
 ; Check LLH with no displacement.
 define i32 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -43,7 +43,7 @@ define i32 @f4(i16 *%src) {
 
 ; Check the high end of the LLH range.
 define i32 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llh %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -55,7 +55,7 @@ define i32 @f5(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i32 @f6(i16 *%src) {
 
 ; Check the high end of the negative LLH range.
 define i32 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llh %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f7(i16 *%src) {
 
 ; Check the low end of the LLH range.
 define i32 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llh %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -90,7 +90,7 @@ define i32 @f8(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524290
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i32 @f9(i16 *%src) {
 
 ; Check that LLH allows an index
 define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llh %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -116,7 +116,7 @@ define i32 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLHR.  We want
 ; to use LLH if possible.
 define void @f11(i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llh {{%r[0-9]+}}, 16{{[26]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-07.ll b/test/CodeGen/SystemZ/int-conv-07.ll
index 9b9df46be9c..4b78c773d1e 100644
--- a/test/CodeGen/SystemZ/int-conv-07.ll
+++ b/test/CodeGen/SystemZ/int-conv-07.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i64 %a to i16
@@ -14,7 +14,7 @@ define i64 @f1(i64 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lghr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i32 %a to i16
@@ -24,7 +24,7 @@ define i64 @f2(i32 %a) {
 
 ; Check LGH with no displacement.
 define i64 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -34,7 +34,7 @@ define i64 @f3(i16 *%src) {
 
 ; Check the high end of the LGH range.
 define i64 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgh %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -46,7 +46,7 @@ define i64 @f4(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i64 @f5(i16 *%src) {
 
 ; Check the high end of the negative LGH range.
 define i64 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgh %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -69,7 +69,7 @@ define i64 @f6(i16 *%src) {
 
 ; Check the low end of the LGH range.
 define i64 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgh %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -81,7 +81,7 @@ define i64 @f7(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524290
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i64 @f8(i16 *%src) {
 
 ; Check that LGH allows an index.
 define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgh %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -107,7 +107,7 @@ define i64 @f9(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LGHR.  We want
 ; to use LGH if possible.
 define void @f10(i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lgh {{%r[0-9]+}}, 166(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-08.ll b/test/CodeGen/SystemZ/int-conv-08.ll
index 0616f1e4561..6b6cb672fb9 100644
--- a/test/CodeGen/SystemZ/int-conv-08.ll
+++ b/test/CodeGen/SystemZ/int-conv-08.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llghr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i32 %a to i16
@@ -14,7 +14,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llghr %r2, %r2
 ; CHECK: br %r14
   %half = trunc i64 %a to i16
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llghr %r2, %r2
 ; CHECK: br %r14
   %ext = and i64 %a, 65535
@@ -33,7 +33,7 @@ define i64 @f3(i64 %a) {
 
 ; Check LLGH with no displacement.
 define i64 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -43,7 +43,7 @@ define i64 @f4(i16 *%src) {
 
 ; Check the high end of the LLGH range.
 define i64 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgh %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -55,7 +55,7 @@ define i64 @f5(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i16 *%src) {
 
 ; Check the high end of the negative LLGH range.
 define i64 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgh %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i64 @f7(i16 *%src) {
 
 ; Check the low end of the LLGH range.
 define i64 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgh %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -90,7 +90,7 @@ define i64 @f8(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524290
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i64 @f9(i16 *%src) {
 
 ; Check that LLGH allows an index
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgh %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -116,7 +116,7 @@ define i64 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLGHR.  We want
 ; to use LLGH if possible.
 define void @f11(i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llgh {{%r[0-9]+}}, 166(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i64 *%ptr
diff --git a/test/CodeGen/SystemZ/int-conv-09.ll b/test/CodeGen/SystemZ/int-conv-09.ll
index ab6c463092c..db4c333a30b 100644
--- a/test/CodeGen/SystemZ/int-conv-09.ll
+++ b/test/CodeGen/SystemZ/int-conv-09.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgfr %r2, %r2
 ; CHECK: br %r14
   %ext = sext i32 %a to i64
@@ -13,7 +13,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgfr %r2, %r2
 ; CHECK: br %r14
   %word = trunc i64 %a to i32
@@ -23,7 +23,7 @@ define i64 @f2(i64 %a) {
 
 ; Check LGF with no displacement.
 define i64 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
   %word = load i32 *%src
@@ -33,7 +33,7 @@ define i64 @f3(i32 *%src) {
 
 ; Check the high end of the LGF range.
 define i64 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgf %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -45,7 +45,7 @@ define i64 @f4(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -57,7 +57,7 @@ define i64 @f5(i32 *%src) {
 
 ; Check the high end of the negative LGF range.
 define i64 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgf %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -68,7 +68,7 @@ define i64 @f6(i32 *%src) {
 
 ; Check the low end of the LGF range.
 define i64 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgf %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -80,7 +80,7 @@ define i64 @f7(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -92,7 +92,7 @@ define i64 @f8(i32 *%src) {
 
 ; Check that LGF allows an index.
 define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgf %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -106,7 +106,7 @@ define i64 @f9(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LGFR.  We want
 ; to use LGF if possible.
 define void @f10(i64 *%ptr1, i32 *%ptr2) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr2
diff --git a/test/CodeGen/SystemZ/int-conv-10.ll b/test/CodeGen/SystemZ/int-conv-10.ll
index 4b078f95455..f2f71d90dce 100644
--- a/test/CodeGen/SystemZ/int-conv-10.ll
+++ b/test/CodeGen/SystemZ/int-conv-10.ll
@@ -4,7 +4,7 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgfr %r2, %r2
 ; CHECK: br %r14
   %ext = zext i32 %a to i64
@@ -13,7 +13,7 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgfr %r2, %r2
 ; CHECK: br %r14
   %word = trunc i64 %a to i32
@@ -23,7 +23,7 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgfr %r2, %r2
 ; CHECK: br %r14
   %ext = and i64 %a, 4294967295
@@ -32,7 +32,7 @@ define i64 @f3(i64 %a) {
 
 ; Check LLGF with no displacement.
 define i64 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
   %word = load i32 *%src
@@ -42,7 +42,7 @@ define i64 @f4(i32 *%src) {
 
 ; Check the high end of the LLGF range.
 define i64 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgf %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -54,7 +54,7 @@ define i64 @f5(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i64 @f6(i32 *%src) {
 
 ; Check the high end of the negative LLGF range.
 define i64 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgf %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -77,7 +77,7 @@ define i64 @f7(i32 *%src) {
 
 ; Check the low end of the LLGF range.
 define i64 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgf %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -89,7 +89,7 @@ define i64 @f8(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524292
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -101,7 +101,7 @@ define i64 @f9(i32 *%src) {
 
 ; Check that LLGF allows an index.
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgf %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -115,7 +115,7 @@ define i64 @f10(i64 %src, i64 %index) {
 ; Test a case where we spill the source of at least one LLGFR.  We want
 ; to use LLGF if possible.
 define void @f11(i64 *%ptr1, i32 *%ptr2) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
   %val0 = load volatile i32 *%ptr2
diff --git a/test/CodeGen/SystemZ/int-div-01.ll b/test/CodeGen/SystemZ/int-div-01.ll
index 9fa019b98c5..2c21186e336 100644
--- a/test/CodeGen/SystemZ/int-div-01.ll
+++ b/test/CodeGen/SystemZ/int-div-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Test register division.  The result is in the second of the two registers.
 define void @f1(i32 *%dest, i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgfr %r0, %r4
 ; CHECK: st %r1, 0(%r2)
@@ -18,7 +18,7 @@ define void @f1(i32 *%dest, i32 %a, i32 %b) {
 
 ; Test register remainder.  The result is in the first of the two registers.
 define void @f2(i32 *%dest, i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgfr %r0, %r4
 ; CHECK: st %r0, 0(%r2)
@@ -30,7 +30,7 @@ define void @f2(i32 *%dest, i32 %a, i32 %b) {
 
 ; Test that division and remainder use a single instruction.
 define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: lgfr %r3, %r3
 ; CHECK-NOT: %r2
@@ -47,7 +47,7 @@ define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
 ; Check that the sign extension of the dividend is elided when the argument
 ; is already sign-extended.
 define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK-NOT: dsgfr
@@ -61,7 +61,7 @@ define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
 
 ; Test that memory dividends are loaded using sign extension (LGF).
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: lgf %r3, 0(%r3)
 ; CHECK-NOT: %r2
@@ -78,7 +78,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Test memory division with no displacement.
 define void @f6(i32 *%dest, i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgf %r0, 0(%r4)
 ; CHECK: st %r1, 0(%r2)
@@ -91,7 +91,7 @@ define void @f6(i32 *%dest, i32 %a, i32 *%src) {
 
 ; Test memory remainder with no displacement.
 define void @f7(i32 *%dest, i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgf %r0, 0(%r4)
 ; CHECK: st %r0, 0(%r2)
@@ -104,7 +104,7 @@ define void @f7(i32 *%dest, i32 %a, i32 *%src) {
 
 ; Test both memory division and memory remainder.
 define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: lgfr %r3, %r3
 ; CHECK-NOT: %r2
@@ -121,7 +121,7 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the DSGF range.
 define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dsgf %r2, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -133,7 +133,7 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -145,7 +145,7 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned DSGF range.
 define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: dsgf %r2, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -156,7 +156,7 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the low end of the DSGF range.
 define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dsgf %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -168,7 +168,7 @@ define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agfi %r4, -524292
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -180,7 +180,7 @@ define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check that DSGF allows an index.
 define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: dsgf %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -194,7 +194,7 @@ define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
 ; Make sure that we still use DSGFR rather than DSGR in cases where
 ; a load and division cannot be combined.
 define void @f15(i32 *%dest, i32 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: l [[B:%r[0-9]+]], 0(%r3)
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: lgfr %r1, %r2
@@ -209,7 +209,7 @@ define void @f15(i32 *%dest, i32 *%src) {
 
 ; Check that divisions of spilled values can use DSGF rather than DSGFR.
 define i32 @f16(i32 *%ptr0) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dsgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-div-02.ll b/test/CodeGen/SystemZ/int-div-02.ll
index b09172df9da..f3287a56c6c 100644
--- a/test/CodeGen/SystemZ/int-div-02.ll
+++ b/test/CodeGen/SystemZ/int-div-02.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Test register division.  The result is in the second of the two registers.
 define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -20,7 +20,7 @@ define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
 
 ; Test register remainder.  The result is in the first of the two registers.
 define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -34,7 +34,7 @@ define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
 
 ; Test that division and remainder use a single instruction.
 define i32 @f3(i32 %dummy1, i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -50,7 +50,7 @@ define i32 @f3(i32 %dummy1, i32 %a, i32 %b) {
 
 ; Test memory division with no displacement.
 define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -65,7 +65,7 @@ define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
 
 ; Test memory remainder with no displacement.
 define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -80,7 +80,7 @@ define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
 
 ; Test both memory division and memory remainder.
 define i32 @f6(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -97,7 +97,7 @@ define i32 @f6(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the DL range.
 define i32 @f7(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: dl %r2, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -109,7 +109,7 @@ define i32 @f7(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned DL range.
 define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dl %r2, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -132,7 +132,7 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the low end of the DL range.
 define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dl %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -144,7 +144,7 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524292
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: br %r14
@@ -156,7 +156,7 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check that DL allows an index.
 define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dl %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -169,7 +169,7 @@ define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {
 
 ; Check that divisions of spilled values can use DL rather than DLR.
 define i32 @f13(i32 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dl {{%r[0-9]+}}, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-div-03.ll b/test/CodeGen/SystemZ/int-div-03.ll
index 652fddc1be3..7c0409018f1 100644
--- a/test/CodeGen/SystemZ/int-div-03.ll
+++ b/test/CodeGen/SystemZ/int-div-03.ll
@@ -7,7 +7,7 @@ declare i64 @foo()
 
 ; Test register division.  The result is in the second of the two registers.
 define void @f1(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK: stg %r3, 0(%r5)
@@ -20,7 +20,7 @@ define void @f1(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; Test register remainder.  The result is in the first of the two registers.
 define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK: stg %r2, 0(%r5)
@@ -33,7 +33,7 @@ define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; Test that division and remainder use a single instruction.
 define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK: ogr %r2, %r3
@@ -48,7 +48,7 @@ define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
 ; Test register division when the dividend is zero rather than sign extended.
 ; We can't use dsgfr here
 define void @f4(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: dsgfr
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -59,7 +59,7 @@ define void @f4(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; ...likewise remainder.
 define void @f5(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: dsgfr
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -70,7 +70,7 @@ define void @f5(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; Test memory division with no displacement.
 define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: stg %r3, 0(%r5)
@@ -84,7 +84,7 @@ define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
 
 ; Test memory remainder with no displacement.
 define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: stg %r2, 0(%r5)
@@ -98,7 +98,7 @@ define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
 
 ; Test both memory division and memory remainder.
 define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK-NOT: {{dsgf|dsgfr}}
@@ -114,7 +114,7 @@ define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check the high end of the DSGF range.
 define i64 @f9(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dsgf %r2, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -127,7 +127,7 @@ define i64 @f9(i64 %dummy, i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f10(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -140,7 +140,7 @@ define i64 @f10(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned DSGF range.
 define i64 @f11(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: dsgf %r2, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -152,7 +152,7 @@ define i64 @f11(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check the low end of the DSGF range.
 define i64 @f12(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dsgf %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -165,7 +165,7 @@ define i64 @f12(i64 %dummy, i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f13(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agfi %r4, -524292
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -178,7 +178,7 @@ define i64 @f13(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check that DSGF allows an index.
 define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: dsgf %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -193,7 +193,7 @@ define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
 ; Make sure that we still use DSGFR rather than DSGR in cases where
 ; a load and division cannot be combined.
 define void @f15(i64 *%dest, i32 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: l [[B:%r[0-9]+]], 0(%r3)
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: lgr %r1, %r2
diff --git a/test/CodeGen/SystemZ/int-div-04.ll b/test/CodeGen/SystemZ/int-div-04.ll
index b2710a17b1d..87f1e105f6a 100644
--- a/test/CodeGen/SystemZ/int-div-04.ll
+++ b/test/CodeGen/SystemZ/int-div-04.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Testg register division.  The result is in the second of the two registers.
 define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgr %r2, %r4
 ; CHECK: stg %r3, 0(%r5)
@@ -18,7 +18,7 @@ define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg register remainder.  The result is in the first of the two registers.
 define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgr %r2, %r4
 ; CHECK: stg %r2, 0(%r5)
@@ -30,7 +30,7 @@ define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg that division and remainder use a single instruction.
 define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgr %r2, %r4
 ; CHECK-NOT: dsgr
@@ -44,7 +44,7 @@ define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
 
 ; Testg memory division with no displacement.
 define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: stg %r3, 0(%r5)
@@ -57,7 +57,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg memory remainder with no displacement.
 define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: stg %r2, 0(%r5)
@@ -70,7 +70,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg both memory division and memory remainder.
 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK-NOT: {{dsg|dsgr}}
@@ -85,7 +85,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the DSG range.
 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: dsg %r2, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -97,7 +97,7 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned DSG range.
 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dsg %r2, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -120,7 +120,7 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the low end of the DSG range.
 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dsg %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -132,7 +132,7 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524296
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -144,7 +144,7 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check that DSG allows an index.
 define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dsg %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -157,7 +157,7 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
 
 ; Check that divisions of spilled values can use DSG rather than DSGR.
 define i64 @f13(i64 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dsg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-div-05.ll b/test/CodeGen/SystemZ/int-div-05.ll
index 31415034986..817983005a9 100644
--- a/test/CodeGen/SystemZ/int-div-05.ll
+++ b/test/CodeGen/SystemZ/int-div-05.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Testg register division.  The result is in the second of the two registers.
 define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -20,7 +20,7 @@ define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg register remainder.  The result is in the first of the two registers.
 define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -34,7 +34,7 @@ define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg that division and remainder use a single instruction.
 define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -50,7 +50,7 @@ define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
 
 ; Testg memory division with no displacement.
 define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -65,7 +65,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg memory remainder with no displacement.
 define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -80,7 +80,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg both memory division and memory remainder.
 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -97,7 +97,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the DLG range.
 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: dlg %r2, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -109,7 +109,7 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned DLG range.
 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dlg %r2, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -132,7 +132,7 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the low end of the DLG range.
 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dlg %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -144,7 +144,7 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524296
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -156,7 +156,7 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check that DLG allows an index.
 define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dlg %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -169,7 +169,7 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
 
 ; Check that divisions of spilled values can use DLG rather than DLGR.
 define i64 @f13(i64 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: dlg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-move-01.ll b/test/CodeGen/SystemZ/int-move-01.ll
index ae890ade327..038e6887d67 100644
--- a/test/CodeGen/SystemZ/int-move-01.ll
+++ b/test/CodeGen/SystemZ/int-move-01.ll
@@ -4,7 +4,7 @@
 
 ; Test 8-bit moves, which should get promoted to i32.
 define i8 @f1(i8 %a, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   ret i8 %b
@@ -12,7 +12,7 @@ define i8 @f1(i8 %a, i8 %b) {
 
 ; Test 16-bit moves, which again should get promoted to i32.
 define i16 @f2(i16 %a, i16 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   ret i16 %b
@@ -20,7 +20,7 @@ define i16 @f2(i16 %a, i16 %b) {
 
 ; Test 32-bit moves.
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   ret i32 %b
@@ -28,7 +28,7 @@ define i32 @f3(i32 %a, i32 %b) {
 
 ; Test 64-bit moves.
 define i64 @f4(i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   ret i64 %b
diff --git a/test/CodeGen/SystemZ/int-move-02.ll b/test/CodeGen/SystemZ/int-move-02.ll
index 467e22d89c5..5fc0843290f 100644
--- a/test/CodeGen/SystemZ/int-move-02.ll
+++ b/test/CodeGen/SystemZ/int-move-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the L range.
 define i32 @f1(i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
   %val = load i32 *%src
@@ -13,7 +13,7 @@ define i32 @f1(i32 *%src) {
 
 ; Check the high end of the aligned L range.
 define i32 @f2(i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -23,7 +23,7 @@ define i32 @f2(i32 *%src) {
 
 ; Check the next word up, which should use LY instead of L.
 define i32 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ly %r2, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -33,7 +33,7 @@ define i32 @f3(i32 *%src) {
 
 ; Check the high end of the aligned LY range.
 define i32 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ly %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -44,7 +44,7 @@ define i32 @f4(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define i32 @f5(i32 *%src) {
 
 ; Check the high end of the negative aligned LY range.
 define i32 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ly %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i32 @f6(i32 *%src) {
 
 ; Check the low end of the LY range.
 define i32 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ly %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +76,7 @@ define i32 @f7(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define i32 @f8(i32 *%src) {
 
 ; Check that L allows an index.
 define i32 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: l %r2, 4095({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define i32 @f9(i64 %src, i64 %index) {
 
 ; Check that LY allows an index.
 define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ly %r2, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-move-03.ll b/test/CodeGen/SystemZ/int-move-03.ll
index 97c70a2740c..2894512e8ee 100644
--- a/test/CodeGen/SystemZ/int-move-03.ll
+++ b/test/CodeGen/SystemZ/int-move-03.ll
@@ -4,7 +4,7 @@
 
 ; Check LG with no displacement.
 define i64 @f1(i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
   %val = load i64 *%src
@@ -13,7 +13,7 @@ define i64 @f1(i64 *%src) {
 
 ; Check the high end of the aligned LG range.
 define i64 @f2(i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -24,7 +24,7 @@ define i64 @f2(i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f3(i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define i64 @f3(i64 *%src) {
 
 ; Check the high end of the negative aligned LG range.
 define i64 @f4(i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -45,7 +45,7 @@ define i64 @f4(i64 *%src) {
 
 ; Check the low end of the LG range.
 define i64 @f5(i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lg %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -56,7 +56,7 @@ define i64 @f5(i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i64 *%src) {
 
 ; Check that LG allows an index.
 define i64 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lg %r2, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-move-04.ll b/test/CodeGen/SystemZ/int-move-04.ll
index 9736657b1ef..d97ed2f54a4 100644
--- a/test/CodeGen/SystemZ/int-move-04.ll
+++ b/test/CodeGen/SystemZ/int-move-04.ll
@@ -4,7 +4,7 @@
 
 ; Test an i8 store, which should get converted into an i32 truncation.
 define void @f1(i8 *%dst, i8 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   store i8 %val, i8 *%dst
@@ -13,7 +13,7 @@ define void @f1(i8 *%dst, i8 %val) {
 
 ; Test an i32 truncating store.
 define void @f2(i8 *%dst, i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i32 %val to i8
@@ -23,7 +23,7 @@ define void @f2(i8 *%dst, i32 %val) {
 
 ; Test an i64 truncating store.
 define void @f3(i8 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i64 %val to i8
@@ -33,7 +33,7 @@ define void @f3(i8 *%dst, i64 %val) {
 
 ; Check the high end of the STC range.
 define void @f4(i8 *%dst, i8 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stc %r3, 4095(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 4095
@@ -43,7 +43,7 @@ define void @f4(i8 *%dst, i8 %val) {
 
 ; Check the next byte up, which should use STCY instead of STC.
 define void @f5(i8 *%dst, i8 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stcy %r3, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 4096
@@ -53,7 +53,7 @@ define void @f5(i8 *%dst, i8 %val) {
 
 ; Check the high end of the STCY range.
 define void @f6(i8 *%dst, i8 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stcy %r3, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 524287
@@ -64,7 +64,7 @@ define void @f6(i8 *%dst, i8 %val) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i8 *%dst, i8 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f7(i8 *%dst, i8 %val) {
 
 ; Check the high end of the negative STCY range.
 define void @f8(i8 *%dst, i8 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: stcy %r3, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 -1
@@ -85,7 +85,7 @@ define void @f8(i8 *%dst, i8 %val) {
 
 ; Check the low end of the STCY range.
 define void @f9(i8 *%dst, i8 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: stcy %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 -524288
@@ -96,7 +96,7 @@ define void @f9(i8 *%dst, i8 %val) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i8 *%dst, i8 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524289
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define void @f10(i8 *%dst, i8 %val) {
 
 ; Check that STC allows an index.
 define void @f11(i64 %dst, i64 %index, i8 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: stc %r4, 4095(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
@@ -119,7 +119,7 @@ define void @f11(i64 %dst, i64 %index, i8 %val) {
 
 ; Check that STCY allows an index.
 define void @f12(i64 %dst, i64 %index, i8 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: stcy %r4, 4096(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-05.ll b/test/CodeGen/SystemZ/int-move-05.ll
index f61477e7183..c21b88aa7ba 100644
--- a/test/CodeGen/SystemZ/int-move-05.ll
+++ b/test/CodeGen/SystemZ/int-move-05.ll
@@ -4,7 +4,7 @@
 
 ; Test an i16 store, which should get converted into an i32 truncation.
 define void @f1(i16 *%dst, i16 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   store i16 %val, i16 *%dst
@@ -13,7 +13,7 @@ define void @f1(i16 *%dst, i16 %val) {
 
 ; Test an i32 truncating store.
 define void @f2(i16 *%dst, i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i32 %val to i16
@@ -23,7 +23,7 @@ define void @f2(i16 *%dst, i32 %val) {
 
 ; Test an i64 truncating store.
 define void @f3(i16 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i64 %val to i16
@@ -33,7 +33,7 @@ define void @f3(i16 *%dst, i64 %val) {
 
 ; Check the high end of the STH range.
 define void @f4(i16 *%dst, i16 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sth %r3, 4094(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 2047
@@ -43,7 +43,7 @@ define void @f4(i16 *%dst, i16 %val) {
 
 ; Check the next halfword up, which should use STHY instead of STH.
 define void @f5(i16 *%dst, i16 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sthy %r3, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 2048
@@ -53,7 +53,7 @@ define void @f5(i16 *%dst, i16 %val) {
 
 ; Check the high end of the aligned STHY range.
 define void @f6(i16 *%dst, i16 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sthy %r3, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 262143
@@ -64,7 +64,7 @@ define void @f6(i16 *%dst, i16 %val) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i16 *%dst, i16 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f7(i16 *%dst, i16 %val) {
 
 ; Check the high end of the negative aligned STHY range.
 define void @f8(i16 *%dst, i16 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sthy %r3, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 -1
@@ -85,7 +85,7 @@ define void @f8(i16 *%dst, i16 %val) {
 
 ; Check the low end of the STHY range.
 define void @f9(i16 *%dst, i16 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: sthy %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 -262144
@@ -96,7 +96,7 @@ define void @f9(i16 *%dst, i16 %val) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i16 *%dst, i16 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524290
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define void @f10(i16 *%dst, i16 %val) {
 
 ; Check that STH allows an index.
 define void @f11(i64 %dst, i64 %index, i16 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sth %r4, 4094({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
@@ -119,7 +119,7 @@ define void @f11(i64 %dst, i64 %index, i16 %val) {
 
 ; Check that STHY allows an index.
 define void @f12(i64 %dst, i64 %index, i16 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: sthy %r4, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-06.ll b/test/CodeGen/SystemZ/int-move-06.ll
index 5b35a32ff54..b8c6f53e15d 100644
--- a/test/CodeGen/SystemZ/int-move-06.ll
+++ b/test/CodeGen/SystemZ/int-move-06.ll
@@ -4,7 +4,7 @@
 
 ; Test an i32 store.
 define void @f1(i32 *%dst, i32 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
   store i32 %val, i32 *%dst
@@ -20,7 +20,7 @@ define void @f2(i32 *%dst, i64 %val) {
 
 ; Check the high end of the aligned ST range.
 define void @f3(i32 *%dst, i32 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: st %r3, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 1023
@@ -30,7 +30,7 @@ define void @f3(i32 *%dst, i32 %val) {
 
 ; Check the next word up, which should use STY instead of ST.
 define void @f4(i32 *%dst, i32 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sty %r3, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 1024
@@ -40,7 +40,7 @@ define void @f4(i32 *%dst, i32 %val) {
 
 ; Check the high end of the aligned STY range.
 define void @f5(i32 *%dst, i32 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sty %r3, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 131071
@@ -51,7 +51,7 @@ define void @f5(i32 *%dst, i32 %val) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i32 *%dst, i32 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f6(i32 *%dst, i32 %val) {
 
 ; Check the high end of the negative aligned STY range.
 define void @f7(i32 *%dst, i32 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sty %r3, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -1
@@ -72,7 +72,7 @@ define void @f7(i32 *%dst, i32 %val) {
 
 ; Check the low end of the STY range.
 define void @f8(i32 *%dst, i32 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sty %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -131072
@@ -83,7 +83,7 @@ define void @f8(i32 *%dst, i32 %val) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i32 *%dst, i32 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524292
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
@@ -94,7 +94,7 @@ define void @f9(i32 *%dst, i32 %val) {
 
 ; Check that ST allows an index.
 define void @f10(i64 %dst, i64 %index, i32 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: st %r4, 4095(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
@@ -106,7 +106,7 @@ define void @f10(i64 %dst, i64 %index, i32 %val) {
 
 ; Check that STY allows an index.
 define void @f11(i64 %dst, i64 %index, i32 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sty %r4, 4096(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-07.ll b/test/CodeGen/SystemZ/int-move-07.ll
index ab21ab03953..5cac1e5b1a2 100644
--- a/test/CodeGen/SystemZ/int-move-07.ll
+++ b/test/CodeGen/SystemZ/int-move-07.ll
@@ -4,7 +4,7 @@
 
 ; Check STG with no displacement.
 define void @f1(i64 *%dst, i64 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
   store i64 %val, i64 *%dst
@@ -13,7 +13,7 @@ define void @f1(i64 *%dst, i64 %val) {
 
 ; Check the high end of the aligned STG range.
 define void @f2(i64 *%dst, i64 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stg %r3, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 65535
@@ -24,7 +24,7 @@ define void @f2(i64 *%dst, i64 %val) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f3(i64 *%dst, i64 %val) {
 
 ; Check the high end of the negative aligned STG range.
 define void @f4(i64 *%dst, i64 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stg %r3, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -1
@@ -45,7 +45,7 @@ define void @f4(i64 *%dst, i64 %val) {
 
 ; Check the low end of the STG range.
 define void @f5(i64 *%dst, i64 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stg %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -65536
@@ -56,7 +56,7 @@ define void @f5(i64 *%dst, i64 %val) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%dst, i64 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define void @f6(i64 *%dst, i64 %val) {
 
 ; Check that STG allows an index.
 define void @f7(i64 %dst, i64 %index, i64 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stg %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-08.ll b/test/CodeGen/SystemZ/int-move-08.ll
index e6022aa6cae..f16dd8e3808 100644
--- a/test/CodeGen/SystemZ/int-move-08.ll
+++ b/test/CodeGen/SystemZ/int-move-08.ll
@@ -13,7 +13,7 @@
 
 ; Check sign-extending loads from i16.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -23,7 +23,7 @@ define i32 @f1() {
 
 ; Check zero-extending loads from i16.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llhrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -33,7 +33,7 @@ define i32 @f2() {
 
 ; Check truncating 16-bit stores.
 define void @f3(i32 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sthrl %r2, gdst16
 ; CHECK: br %r14
   %half = trunc i32 %val to i16
@@ -43,7 +43,7 @@ define void @f3(i32 %val) {
 
 ; Check plain loads and stores.
 define void @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lrl %r0, gsrc32
 ; CHECK: strl %r0, gdst32
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define void @f4() {
 
 ; Repeat f1 with an unaligned variable.
 define i32 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: lh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define i32 @f5() {
 
 ; Repeat f2 with an unaligned variable.
 define i32 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: llh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define i32 @f6() {
 
 ; Repeat f3 with an unaligned variable.
 define void @f7(i32 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgrl [[REG:%r[0-5]]], gdst16u
 ; CHECK: sth %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define void @f7(i32 %val) {
 
 ; Repeat f4 with unaligned variables.
 define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: larl [[REG:%r[0-5]]], gdst32u
diff --git a/test/CodeGen/SystemZ/int-move-09.ll b/test/CodeGen/SystemZ/int-move-09.ll
index 9167405aa97..b5c9cb13d28 100644
--- a/test/CodeGen/SystemZ/int-move-09.ll
+++ b/test/CodeGen/SystemZ/int-move-09.ll
@@ -17,7 +17,7 @@
 
 ; Check sign-extending loads from i16.
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -27,7 +27,7 @@ define i64 @f1() {
 
 ; Check zero-extending loads from i16.
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llghrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -37,7 +37,7 @@ define i64 @f2() {
 
 ; Check sign-extending loads from i32.
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgfrl %r2, gsrc32
 ; CHECK: br %r14
   %val = load i32 *@gsrc32
@@ -47,7 +47,7 @@ define i64 @f3() {
 
 ; Check zero-extending loads from i32.
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgfrl %r2, gsrc32
 ; CHECK: br %r14
   %val = load i32 *@gsrc32
@@ -57,7 +57,7 @@ define i64 @f4() {
 
 ; Check truncating 16-bit stores.
 define void @f5(i64 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sthrl %r2, gdst16
 ; CHECK: br %r14
   %half = trunc i64 %val to i16
@@ -67,7 +67,7 @@ define void @f5(i64 %val) {
 
 ; Check truncating 32-bit stores.
 define void @f6(i64 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: strl %r2, gdst32
 ; CHECK: br %r14
   %word = trunc i64 %val to i32
@@ -77,7 +77,7 @@ define void @f6(i64 %val) {
 
 ; Check plain loads and stores.
 define void @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgrl %r0, gsrc64
 ; CHECK: stgrl %r0, gdst64
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define void @f7() {
 
 ; Repeat f1 with an unaligned variable.
 define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: lgh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define i64 @f8() {
 
 ; Repeat f2 with an unaligned variable.
 define i64 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: llgh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define i64 @f9() {
 
 ; Repeat f3 with an unaligned variable.
 define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: lgf %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i64 @f10() {
 
 ; Repeat f4 with an unaligned variable.
 define i64 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: llgf %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define i64 @f11() {
 
 ; Repeat f5 with an unaligned variable.
 define void @f12(i64 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lgrl [[REG:%r[0-5]]], gdst16u@GOT
 ; CHECK: sth %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -143,7 +143,7 @@ define void @f12(i64 %val) {
 
 ; Repeat f6 with an unaligned variable.
 define void @f13(i64 %val) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: larl [[REG:%r[0-5]]], gdst32u
 ; CHECK: st %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -154,7 +154,7 @@ define void @f13(i64 %val) {
 
 ; Repeat f7 with unaligned variables.
 define void @f14() {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc64u
 ; CHECK: lg [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: larl [[REG:%r[0-5]]], gdst64u
diff --git a/test/CodeGen/SystemZ/int-mul-01.ll b/test/CodeGen/SystemZ/int-mul-01.ll
index e1246e2156e..d5f7155f8c4 100644
--- a/test/CodeGen/SystemZ/int-mul-01.ll
+++ b/test/CodeGen/SystemZ/int-mul-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the MH range.
 define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned MH range.
 define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mh %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -28,7 +28,7 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 
 ; Check the next halfword up, which should use MHY instead of MH.
 define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mhy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -40,7 +40,7 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned MHY range.
 define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mhy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -53,7 +53,7 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the negative aligned MHY range.
 define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mhy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 
 ; Check the low end of the MHY range.
 define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mhy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -91,7 +91,7 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 
 ; Check that MH allows an index.
 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mh %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -118,7 +118,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
 
 ; Check that MHY allows an index.
 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mhy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-mul-02.ll b/test/CodeGen/SystemZ/int-mul-02.ll
index 72990a73b70..d002a7f2f9b 100644
--- a/test/CodeGen/SystemZ/int-mul-02.ll
+++ b/test/CodeGen/SystemZ/int-mul-02.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check MSR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msr %r2, %r3
 ; CHECK: br %r14
   %mul = mul i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the MS range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned MS range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ms %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use MSY instead of MS.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: msy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned MSY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned MSY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: msy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the MSY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that MS allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ms %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that MSY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: msy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that multiplications of spilled values can use MS rather than MSR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: ms %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-mul-03.ll b/test/CodeGen/SystemZ/int-mul-03.ll
index f027bd06065..df18050d024 100644
--- a/test/CodeGen/SystemZ/int-mul-03.ll
+++ b/test/CodeGen/SystemZ/int-mul-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check MSGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msgfr %r2, %r3
 ; CHECK: br %r14
   %bext = sext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check MSGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned MSGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msgf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned MSGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msgf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the MSGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msgf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that MSGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that multiplications of spilled values can use MSGF rather than MSGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: msgf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-mul-04.ll b/test/CodeGen/SystemZ/int-mul-04.ll
index b37b043fb6a..183a9a748c3 100644
--- a/test/CodeGen/SystemZ/int-mul-04.ll
+++ b/test/CodeGen/SystemZ/int-mul-04.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check MSGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msgr %r2, %r3
 ; CHECK: br %r14
   %mul = mul i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check MSG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned MSG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msg %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned MSG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msg %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the MSG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msg %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that MSG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that multiplications of spilled values can use MSG rather than MSGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: msg %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-mul-05.ll b/test/CodeGen/SystemZ/int-mul-05.ll
index 5e4031b5d77..93f140d8450 100644
--- a/test/CodeGen/SystemZ/int-mul-05.ll
+++ b/test/CodeGen/SystemZ/int-mul-05.ll
@@ -4,7 +4,7 @@
 
 ; Check multiplication by 2, which should use shifts.
 define i32 @f1(i32 %a, i32 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sll %r2, 1
 ; CHECK: br %r14
   %mul = mul i32 %a, 2
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a, i32 *%dest) {
 
 ; Check multiplication by 3.
 define i32 @f2(i32 %a, i32 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mhi %r2, 3
 ; CHECK: br %r14
   %mul = mul i32 %a, 3
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a, i32 *%dest) {
 
 ; Check the high end of the MHI range.
 define i32 @f3(i32 %a, i32 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mhi %r2, 32767
 ; CHECK: br %r14
   %mul = mul i32 %a, 32767
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a, i32 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i32 @f4(i32 %a, i32 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sll %r2, 15
 ; CHECK: br %r14
   %mul = mul i32 %a, 32768
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a, i32 *%dest) {
 
 ; Check the next value up again, which can use MSFI.
 define i32 @f5(i32 %a, i32 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msfi %r2, 32769
 ; CHECK: br %r14
   %mul = mul i32 %a, 32769
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a, i32 *%dest) {
 
 ; Check the high end of the MSFI range.
 define i32 @f6(i32 %a, i32 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msfi %r2, 2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, 2147483647
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a, i32 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i32 @f7(i32 %a, i32 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sll %r2, 31
 ; CHECK: br %r14
   %mul = mul i32 %a, 2147483648
@@ -67,7 +67,7 @@ define i32 @f7(i32 %a, i32 *%dest) {
 
 ; Check the next value up again, which is treated as a negative value.
 define i32 @f8(i32 %a, i32 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msfi %r2, -2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, 2147483649
@@ -76,7 +76,7 @@ define i32 @f8(i32 %a, i32 *%dest) {
 
 ; Check multiplication by -1, which is a negation.
 define i32 @f9(i32 %a, i32 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
   %mul = mul i32 %a, -1
@@ -85,7 +85,7 @@ define i32 @f9(i32 %a, i32 *%dest) {
 
 ; Check multiplication by -2, which should use shifts.
 define i32 @f10(i32 %a, i32 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sll %r2, 1
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i32 @f10(i32 %a, i32 *%dest) {
 
 ; Check multiplication by -3.
 define i32 @f11(i32 %a, i32 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mhi %r2, -3
 ; CHECK: br %r14
   %mul = mul i32 %a, -3
@@ -104,7 +104,7 @@ define i32 @f11(i32 %a, i32 *%dest) {
 
 ; Check the lowest useful MHI value.
 define i32 @f12(i32 %a, i32 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mhi %r2, -32767
 ; CHECK: br %r14
   %mul = mul i32 %a, -32767
@@ -113,7 +113,7 @@ define i32 @f12(i32 %a, i32 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i32 @f13(i32 %a, i32 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: sll %r2, 15
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
@@ -123,7 +123,7 @@ define i32 @f13(i32 %a, i32 *%dest) {
 
 ; Check the next value down again, which can use MSFI.
 define i32 @f14(i32 %a, i32 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: msfi %r2, -32769
 ; CHECK: br %r14
   %mul = mul i32 %a, -32769
@@ -132,7 +132,7 @@ define i32 @f14(i32 %a, i32 *%dest) {
 
 ; Check the lowest useful MSFI value.
 define i32 @f15(i32 %a, i32 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: msfi %r2, -2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, -2147483647
@@ -141,7 +141,7 @@ define i32 @f15(i32 %a, i32 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i32 @f16(i32 %a, i32 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: sll %r2, 31
 ; CHECK-NOT: lcr
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define i32 @f16(i32 %a, i32 *%dest) {
 
 ; Check the next value down again, which is treated as a positive value.
 define i32 @f17(i32 %a, i32 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: msfi %r2, 2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, -2147483649
diff --git a/test/CodeGen/SystemZ/int-mul-06.ll b/test/CodeGen/SystemZ/int-mul-06.ll
index a3546059c02..ae9f9c6e4db 100644
--- a/test/CodeGen/SystemZ/int-mul-06.ll
+++ b/test/CodeGen/SystemZ/int-mul-06.ll
@@ -4,7 +4,7 @@
 
 ; Check multiplication by 2, which should use shifts.
 define i64 @f1(i64 %a, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK: br %r14
   %mul = mul i64 %a, 2
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a, i64 *%dest) {
 
 ; Check multiplication by 3.
 define i64 @f2(i64 %a, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mghi %r2, 3
 ; CHECK: br %r14
   %mul = mul i64 %a, 3
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a, i64 *%dest) {
 
 ; Check the high end of the MGHI range.
 define i64 @f3(i64 %a, i64 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mghi %r2, 32767
 ; CHECK: br %r14
   %mul = mul i64 %a, 32767
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a, i64 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i64 @f4(i64 %a, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sllg %r2, %r2, 15
 ; CHECK: br %r14
   %mul = mul i64 %a, 32768
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 *%dest) {
 
 ; Check the next value up again, which can use MSGFI.
 define i64 @f5(i64 %a, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msgfi %r2, 32769
 ; CHECK: br %r14
   %mul = mul i64 %a, 32769
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a, i64 *%dest) {
 
 ; Check the high end of the MSGFI range.
 define i64 @f6(i64 %a, i64 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msgfi %r2, 2147483647
 ; CHECK: br %r14
   %mul = mul i64 %a, 2147483647
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a, i64 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i64 @f7(i64 %a, i64 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r2, %r2, 31
 ; CHECK: br %r14
   %mul = mul i64 %a, 2147483648
@@ -67,7 +67,7 @@ define i64 @f7(i64 %a, i64 *%dest) {
 
 ; Check the next value up again, which cannot use a constant multiplicatoin.
 define i64 @f8(i64 %a, i64 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: msgfi
 ; CHECK: br %r14
   %mul = mul i64 %a, 2147483649
@@ -76,7 +76,7 @@ define i64 @f8(i64 %a, i64 *%dest) {
 
 ; Check multiplication by -1, which is a negation.
 define i64 @f9(i64 %a, i64 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lcgr {{%r[0-5]}}, %r2
 ; CHECK: br %r14
   %mul = mul i64 %a, -1
@@ -85,7 +85,7 @@ define i64 @f9(i64 %a, i64 *%dest) {
 
 ; Check multiplication by -2, which should use shifts.
 define i64 @f10(i64 %a, i64 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 1
 ; CHECK: lcgr %r2, [[SHIFTED]]
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f10(i64 %a, i64 *%dest) {
 
 ; Check multiplication by -3.
 define i64 @f11(i64 %a, i64 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mghi %r2, -3
 ; CHECK: br %r14
   %mul = mul i64 %a, -3
@@ -104,7 +104,7 @@ define i64 @f11(i64 %a, i64 *%dest) {
 
 ; Check the lowest useful MGHI value.
 define i64 @f12(i64 %a, i64 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mghi %r2, -32767
 ; CHECK: br %r14
   %mul = mul i64 %a, -32767
@@ -113,7 +113,7 @@ define i64 @f12(i64 %a, i64 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i64 @f13(i64 %a, i64 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 15
 ; CHECK: lcgr %r2, [[SHIFTED]]
 ; CHECK: br %r14
@@ -123,7 +123,7 @@ define i64 @f13(i64 %a, i64 *%dest) {
 
 ; Check the next value down again, which can use MSGFI.
 define i64 @f14(i64 %a, i64 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: msgfi %r2, -32769
 ; CHECK: br %r14
   %mul = mul i64 %a, -32769
@@ -132,7 +132,7 @@ define i64 @f14(i64 %a, i64 *%dest) {
 
 ; Check the lowest useful MSGFI value.
 define i64 @f15(i64 %a, i64 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: msgfi %r2, -2147483647
 ; CHECK: br %r14
   %mul = mul i64 %a, -2147483647
@@ -141,7 +141,7 @@ define i64 @f15(i64 %a, i64 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i64 @f16(i64 %a, i64 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 31
 ; CHECK: lcgr %r2, [[SHIFTED]]
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define i64 @f16(i64 %a, i64 *%dest) {
 
 ; Check the next value down again, which cannot use constant multiplication
 define i64 @f17(i64 %a, i64 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK-NOT: msgfi
 ; CHECK: br %r14
   %mul = mul i64 %a, -2147483649
diff --git a/test/CodeGen/SystemZ/int-mul-07.ll b/test/CodeGen/SystemZ/int-mul-07.ll
index 2459cc35993..874f43dd398 100644
--- a/test/CodeGen/SystemZ/int-mul-07.ll
+++ b/test/CodeGen/SystemZ/int-mul-07.ll
@@ -7,7 +7,7 @@
 
 ; Check zero-extended multiplication in which only the high part is used.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msgr
 ; CHECK: br %r14
   %ax = zext i32 %a to i64
@@ -20,7 +20,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check sign-extended multiplication in which only the high part is used.
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msgfr
 ; CHECK: br %r14
   %ax = sext i32 %a to i64
@@ -34,7 +34,7 @@ define i32 @f2(i32 %a, i32 %b) {
 ; Check zero-extended multiplication in which the result is split into
 ; high and low halves.
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msgr
 ; CHECK: br %r14
   %ax = zext i32 %a to i64
@@ -50,7 +50,7 @@ define i32 @f3(i32 %a, i32 %b) {
 ; Check sign-extended multiplication in which the result is split into
 ; high and low halves.
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: msgfr
 ; CHECK: br %r14
   %ax = sext i32 %a to i64
diff --git a/test/CodeGen/SystemZ/int-mul-08.ll b/test/CodeGen/SystemZ/int-mul-08.ll
index e06cfc2cc20..a245760e180 100644
--- a/test/CodeGen/SystemZ/int-mul-08.ll
+++ b/test/CodeGen/SystemZ/int-mul-08.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check zero-extended multiplication in which only the high part is used.
 define i64 @f1(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlgr %r2, %r4
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f1(i64 %dummy, i64 %a, i64 %b) {
 ; Check sign-extended multiplication in which only the high part is used.
 ; This needs a rather convoluted sequence.
 define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mlgr
 ; CHECK: agr
 ; CHECK: agr
@@ -37,7 +37,7 @@ define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
 ; Check zero-extended multiplication in which only part of the high half
 ; is used.
 define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlgr %r2, %r4
 ; CHECK: srlg %r2, %r2, 3
@@ -53,7 +53,7 @@ define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
 ; Check zero-extended multiplication in which the result is split into
 ; high and low halves.
 define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlgr %r2, %r4
 ; CHECK: ogr %r2, %r3
@@ -70,7 +70,7 @@ define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
 
 ; Check division by a constant, which should use multiplication instead.
 define i64 @f5(i64 %dummy, i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mlgr %r2,
 ; CHECK: srlg %r2, %r2,
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define i64 @f5(i64 %dummy, i64 %a) {
 
 ; Check MLG with no displacement.
 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned MLG range.
 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mlg %r2, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -111,7 +111,7 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword up, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -127,7 +127,7 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned MLG range.
 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mlg %r2, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -142,7 +142,7 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the low end of the MLG range.
 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mlg %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -158,7 +158,7 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f11(i64 *%dest, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524296
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -174,7 +174,7 @@ define i64 @f11(i64 *%dest, i64 %a, i64 *%src) {
 
 ; Check that MLG allows an index.
 define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mlg %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -191,7 +191,7 @@ define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) {
 
 ; Check that multiplications of spilled values can use MLG rather than MLGR.
 define i64 @f13(i64 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mlg {{%r[0-9]+}}, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-neg-01.ll b/test/CodeGen/SystemZ/int-neg-01.ll
index 6114f4efbc9..a342fa79220 100644
--- a/test/CodeGen/SystemZ/int-neg-01.ll
+++ b/test/CodeGen/SystemZ/int-neg-01.ll
@@ -4,7 +4,7 @@
 
 ; Test i32->i32 negation.
 define i32 @f1(i32 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
   %neg = sub i32 0, %val
@@ -13,7 +13,7 @@ define i32 @f1(i32 %val) {
 
 ; Test i32->i64 negation.
 define i64 @f2(i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lcgfr %r2, %r2
 ; CHECK: br %r14
   %ext = sext i32 %val to i64
@@ -23,7 +23,7 @@ define i64 @f2(i32 %val) {
 
 ; Test i32->i64 negation that uses an "in-register" form of sign extension.
 define i64 @f3(i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lcgfr %r2, %r2
 ; CHECK: br %r14
   %trunc = trunc i64 %val to i32
@@ -34,7 +34,7 @@ define i64 @f3(i64 %val) {
 
 ; Test i64 negation.
 define i64 @f4(i64 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lcgr %r2, %r2
 ; CHECK: br %r14
   %neg = sub i64 0, %val
diff --git a/test/CodeGen/SystemZ/int-sub-01.ll b/test/CodeGen/SystemZ/int-sub-01.ll
index 96ce36190dc..ac3a5ff68b9 100644
--- a/test/CodeGen/SystemZ/int-sub-01.ll
+++ b/test/CodeGen/SystemZ/int-sub-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check SR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sr %r2, %r3
 ; CHECK: br %r14
   %sub = sub i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the S range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned S range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: s %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use SY instead of S.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned SY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned SY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the SY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that S allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: s %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that SY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that subtractions of spilled values can use S rather than SR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: s %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-sub-02.ll b/test/CodeGen/SystemZ/int-sub-02.ll
index 99d1c7b7c85..a1c5ec50ee9 100644
--- a/test/CodeGen/SystemZ/int-sub-02.ll
+++ b/test/CodeGen/SystemZ/int-sub-02.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check SGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sgfr %r2, %r3
 ; CHECK: br %r14
   %bext = sext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check SGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned SGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sgf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned SGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sgf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the SGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sgf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that SGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that subtractions of spilled values can use SGF rather than SGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: sgf %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-sub-03.ll b/test/CodeGen/SystemZ/int-sub-03.ll
index 49040177fde..44edd84bda4 100644
--- a/test/CodeGen/SystemZ/int-sub-03.ll
+++ b/test/CodeGen/SystemZ/int-sub-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check SLGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: slgfr %r2, %r3
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check SLGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -27,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned SLGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: slgf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned SLGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: slgf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the SLGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: slgf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -78,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that SLGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: slgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -105,7 +105,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that subtractions of spilled values can use SLGF rather than SLGFR.
 define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: slgf %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-sub-04.ll b/test/CodeGen/SystemZ/int-sub-04.ll
index 554f7f61bc0..954775612b1 100644
--- a/test/CodeGen/SystemZ/int-sub-04.ll
+++ b/test/CodeGen/SystemZ/int-sub-04.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check SGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sgr %r2, %r3
 ; CHECK: br %r14
   %sub = sub i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check SG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned SG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sg %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned SG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sg %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the SG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sg %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that SG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that subtractions of spilled values can use SG rather than SGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: sg %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-sub-05.ll b/test/CodeGen/SystemZ/int-sub-05.ll
index 5d95e79080b..9ec66d090fe 100644
--- a/test/CodeGen/SystemZ/int-sub-05.ll
+++ b/test/CodeGen/SystemZ/int-sub-05.ll
@@ -6,7 +6,7 @@ declare i128 *@foo()
 
 ; Test register addition.
 define void @f1(i128 *%ptr, i64 %high, i64 %low) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: slgr {{%r[0-5]}}, %r4
 ; CHECK: slbgr {{%r[0-5]}}, %r3
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define void @f1(i128 *%ptr, i64 %high, i64 %low) {
 
 ; Test memory addition with no offset.
 define void @f2(i64 %addr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: slg {{%r[0-5]}}, 8(%r2)
 ; CHECK: slbg {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define void @f2(i64 %addr) {
 
 ; Test the highest aligned offset that is in range of both SLG and SLBG.
 define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: slg {{%r[0-5]}}, 524280(%r2)
 ; CHECK: slbg {{%r[0-5]}}, 524272(%r2)
 ; CHECK: br %r14
@@ -53,7 +53,7 @@ define void @f3(i64 %base) {
 
 ; Test the next doubleword up, which requires separate address logic for SLG.
 define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgr [[BASE:%r[1-5]]], %r2
 ; CHECK: agfi [[BASE]], 524288
 ; CHECK: slg {{%r[0-5]}}, 0([[BASE]])
@@ -73,7 +73,7 @@ define void @f4(i64 %base) {
 ; both instructions.  It would be better to create an anchor at 524288
 ; that both instructions can use, but that isn't implemented yet.
 define void @f5(i64 %base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: slg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define void @f5(i64 %base) {
 
 ; Test the lowest displacement that is in range of both SLG and SLBG.
 define void @f6(i64 %base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: slg {{%r[0-5]}}, -524280(%r2)
 ; CHECK: slbg {{%r[0-5]}}, -524288(%r2)
 ; CHECK: br %r14
@@ -105,7 +105,7 @@ define void @f6(i64 %base) {
 
 ; Test the next doubleword down, which is out of range of the SLBG.
 define void @f7(i64 %base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: slg {{%r[0-5]}}, -524288(%r2)
 ; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define void @f7(i64 %base) {
 ; Check that subtractions of spilled values can use SLG and SLBG rather than
 ; SLGR and SLBGR.
 define void @f8(i128 *%ptr0) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: slg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
 ; CHECK: slbg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
diff --git a/test/CodeGen/SystemZ/int-sub-06.ll b/test/CodeGen/SystemZ/int-sub-06.ll
index 0e04d51e2bc..395d584b23d 100644
--- a/test/CodeGen/SystemZ/int-sub-06.ll
+++ b/test/CodeGen/SystemZ/int-sub-06.ll
@@ -5,7 +5,7 @@
 ; Check register additions.  The XOR ensures that we don't instead zero-extend
 ; %b into a register and use memory addition.
 define void @f1(i128 *%aptr, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define void @f1(i128 *%aptr, i32 %b) {
 
 ; Like f1, but using an "in-register" extension.
 define void @f2(i128 *%aptr, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f2(i128 *%aptr, i64 %b) {
 ; Test register addition in cases where the second operand is zero extended
 ; from i64 rather than i32, but is later masked to i32 range.
 define void @f3(i128 *%aptr, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f3(i128 *%aptr, i64 %b) {
 
 ; Test SLGF with no offset.
 define void @f4(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define void @f4(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the SLGF range.
 define void @f5(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: slgf {{%r[0-5]}}, 524284(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -82,7 +82,7 @@ define void @f5(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
@@ -99,7 +99,7 @@ define void @f6(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the negative aligned SLGF range.
 define void @f7(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: slgf {{%r[0-5]}}, -4(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -115,7 +115,7 @@ define void @f7(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the low end of the SLGF range.
 define void @f8(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: slgf {{%r[0-5]}}, -524288(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define void @f8(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
@@ -149,7 +149,7 @@ define void @f9(i128 *%aptr, i32 *%bsrc) {
 
 ; Check that SLGF allows an index.
 define void @f10(i128 *%aptr, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %a = load i128 *%aptr
diff --git a/test/CodeGen/SystemZ/int-sub-07.ll b/test/CodeGen/SystemZ/int-sub-07.ll
index 9bf5ed90550..5c1f42c1cc9 100644
--- a/test/CodeGen/SystemZ/int-sub-07.ll
+++ b/test/CodeGen/SystemZ/int-sub-07.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the SH range.
 define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned SH range.
 define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sh %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -28,7 +28,7 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 
 ; Check the next halfword up, which should use SHY instead of SH.
 define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: shy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -40,7 +40,7 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned SHY range.
 define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: shy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -53,7 +53,7 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the negative aligned SHY range.
 define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: shy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 
 ; Check the low end of the SHY range.
 define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: shy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -91,7 +91,7 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 
 ; Check that SH allows an index.
 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: sh %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %sub1 = add i64 %src, %index
@@ -118,7 +118,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
 
 ; Check that SHY allows an index.
 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: shy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %sub1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/la-01.ll b/test/CodeGen/SystemZ/la-01.ll
index 1ebe109ee00..31d20412517 100644
--- a/test/CodeGen/SystemZ/la-01.ll
+++ b/test/CodeGen/SystemZ/la-01.ll
@@ -19,7 +19,7 @@ declare void @foo(i32 *)
 
 ; Test a load of a fully-aligned external variable.
 define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl %r2, e4
 ; CHECK-NEXT: br %r14
   ret i32 *@e4
@@ -27,7 +27,7 @@ define i32 *@f1() {
 
 ; Test a load of a fully-aligned local variable.
 define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: larl %r2, d4
 ; CHECK-NEXT: br %r14
   ret i32 *@d4
@@ -35,7 +35,7 @@ define i32 *@f2() {
 
 ; Test a load of a 2-byte-aligned external variable.
 define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: larl %r2, e2
 ; CHECK-NEXT: br %r14
   ret i32 *@e2
@@ -43,7 +43,7 @@ define i32 *@f3() {
 
 ; Test a load of a 2-byte-aligned local variable.
 define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: larl %r2, d2
 ; CHECK-NEXT: br %r14
   ret i32 *@d2
@@ -51,7 +51,7 @@ define i32 *@f4() {
 
 ; Test a load of an unaligned external variable, which must go via the GOT.
 define i32 *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, e1@GOT
 ; CHECK-NEXT: br %r14
   ret i32 *@e1
@@ -59,7 +59,7 @@ define i32 *@f5() {
 
 ; Test a load of an unaligned local variable, which must go via the GOT.
 define i32 *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, d1@GOT
 ; CHECK-NEXT: br %r14
   ret i32 *@d1
@@ -67,7 +67,7 @@ define i32 *@f6() {
 
 ; Test a load of an external function.
 define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: larl %r2, ef
 ; CHECK-NEXT: br %r14
   ret void() *@ef
@@ -75,7 +75,7 @@ define void() *@f7() {
 
 ; Test a load of a local function.
 define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: larl %r2, df
 ; CHECK-NEXT: br %r14
   ret void() *@df
@@ -83,7 +83,7 @@ define void() *@f8() {
 
 ; Test that LARL can be rematerialized.
 define i32 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: larl %r2, d2
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: larl %r2, d2
diff --git a/test/CodeGen/SystemZ/la-02.ll b/test/CodeGen/SystemZ/la-02.ll
index 4c5374a0925..d7362d67e3b 100644
--- a/test/CodeGen/SystemZ/la-02.ll
+++ b/test/CodeGen/SystemZ/la-02.ll
@@ -23,7 +23,7 @@ define hidden void @hf() {
 ; Test loads of external variables.  There is no guarantee that the
 ; variable will be in range of LARL.
 define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgrl %r2, ev@GOT
 ; CHECK: br %r14
   ret i32 *@ev
@@ -31,7 +31,7 @@ define i32 *@f1() {
 
 ; ...likewise locally-defined normal-visibility variables.
 define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgrl %r2, dv@GOT
 ; CHECK: br %r14
   ret i32 *@dv
@@ -39,7 +39,7 @@ define i32 *@f2() {
 
 ; ...likewise protected variables.
 define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgrl %r2, pv@GOT
 ; CHECK: br %r14
   ret i32 *@pv
@@ -47,7 +47,7 @@ define i32 *@f3() {
 
 ; ...likewise hidden variables.
 define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgrl %r2, hv@GOT
 ; CHECK: br %r14
   ret i32 *@hv
@@ -56,7 +56,7 @@ define i32 *@f4() {
 ; Check loads of external functions.  This could use LARL, but we don't have
 ; code to detect that yet.
 define void() *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, ef@GOT
 ; CHECK: br %r14
   ret void() *@ef
@@ -64,7 +64,7 @@ define void() *@f5() {
 
 ; ...likewise locally-defined normal-visibility functions.
 define void() *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, df@GOT
 ; CHECK: br %r14
   ret void() *@df
@@ -72,7 +72,7 @@ define void() *@f6() {
 
 ; ...likewise protected functions.
 define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgrl %r2, pf@GOT
 ; CHECK: br %r14
   ret void() *@pf
@@ -80,7 +80,7 @@ define void() *@f7() {
 
 ; ...likewise hidden functions.
 define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lgrl %r2, hf@GOT
 ; CHECK: br %r14
   ret void() *@hf
diff --git a/test/CodeGen/SystemZ/la-03.ll b/test/CodeGen/SystemZ/la-03.ll
index 9449b2bfbec..1ff3fefde6c 100644
--- a/test/CodeGen/SystemZ/la-03.ll
+++ b/test/CodeGen/SystemZ/la-03.ll
@@ -20,7 +20,7 @@ define hidden void @hf() {
 
 ; Test loads of external variables, which must go via the GOT.
 define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgrl %r2, ev@GOT
 ; CHECK: br %r14
   ret i32 *@ev
@@ -29,7 +29,7 @@ define i32 *@f1() {
 ; Check loads of locally-defined normal-visibility variables, which might
 ; be overridden.  The load must go via the GOT.
 define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgrl %r2, dv@GOT
 ; CHECK: br %r14
   ret i32 *@dv
@@ -38,7 +38,7 @@ define i32 *@f2() {
 ; Check loads of protected variables, which in the small code model
 ; must be in range of LARL.
 define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: larl %r2, pv
 ; CHECK: br %r14
   ret i32 *@pv
@@ -46,7 +46,7 @@ define i32 *@f3() {
 
 ; ...likewise hidden variables.
 define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: larl %r2, hv
 ; CHECK: br %r14
   ret i32 *@hv
@@ -54,7 +54,7 @@ define i32 *@f4() {
 
 ; Like f1, but for functions.
 define void() *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, ef@GOT
 ; CHECK: br %r14
   ret void() *@ef
@@ -62,7 +62,7 @@ define void() *@f5() {
 
 ; Like f2, but for functions.
 define void() *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, df@GOT
 ; CHECK: br %r14
   ret void() *@df
@@ -70,7 +70,7 @@ define void() *@f6() {
 
 ; Like f3, but for functions.
 define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: larl %r2, pf
 ; CHECK: br %r14
   ret void() *@pf
@@ -78,7 +78,7 @@ define void() *@f7() {
 
 ; Like f4, but for functions.
 define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: larl %r2, hf
 ; CHECK: br %r14
   ret void() *@hf
diff --git a/test/CodeGen/SystemZ/la-04.ll b/test/CodeGen/SystemZ/la-04.ll
index 4c3636481e7..4d47308e04b 100644
--- a/test/CodeGen/SystemZ/la-04.ll
+++ b/test/CodeGen/SystemZ/la-04.ll
@@ -4,7 +4,7 @@
 
 ; Do some arbitrary work and return the address of the following label.
 define i8 *@f1(i8 *%addr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvi 0(%r2), 1
 ; CHECK: [[LABEL:\.L.*]]:
 ; CHECK: larl %r2, [[LABEL]]
diff --git a/test/CodeGen/SystemZ/memcpy-01.ll b/test/CodeGen/SystemZ/memcpy-01.ll
index 2985b036d27..7cb58b31cce 100644
--- a/test/CodeGen/SystemZ/memcpy-01.ll
+++ b/test/CodeGen/SystemZ/memcpy-01.ll
@@ -6,7 +6,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8 *nocapture, i8 *nocapture, i32, i32,
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8 *nocapture, i8 *nocapture, i64, i32, i1) nounwind
 
 define void @f1(i8 *%dest, i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK-NOT: %r3
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define void @f1(i8 *%dest, i8 *%src) {
 }
 
 define void @f2(i8 *%dest, i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK-NOT: %r3
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define void @f2(i8 *%dest, i8 *%src) {
 }
 
 define void @f3(i8 *%dest, i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvc 0(1,%r2), 0(%r3)
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 1, i32 1,
@@ -35,7 +35,7 @@ define void @f3(i8 *%dest, i8 *%src) {
 }
 
 define void @f4(i8 *%dest, i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvc 0(1,%r2), 0(%r3)
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1, i32 1,
@@ -44,7 +44,7 @@ define void @f4(i8 *%dest, i8 *%src) {
 }
 
 define void @f5(i8 *%dest, i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvc 0(256,%r2), 0(%r3)
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 256, i32 1,
@@ -53,7 +53,7 @@ define void @f5(i8 *%dest, i8 *%src) {
 }
 
 define void @f6(i8 *%dest, i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvc 0(256,%r2), 0(%r3)
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 256, i32 1,
@@ -64,7 +64,7 @@ define void @f6(i8 *%dest, i8 *%src) {
 ; 257 bytes is too big for a single MVC.  For now expect none, so that
 ; the test fails and gets updated when large copies are implemented.
 define void @f7(i8 *%dest, i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 257, i32 1,
@@ -73,7 +73,7 @@ define void @f7(i8 *%dest, i8 *%src) {
 }
 
 define void @f8(i8 *%dest, i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 257, i32 1,
diff --git a/test/CodeGen/SystemZ/memcpy-02.ll b/test/CodeGen/SystemZ/memcpy-02.ll
index 0b576a713f2..83b2cd816c9 100644
--- a/test/CodeGen/SystemZ/memcpy-02.ll
+++ b/test/CodeGen/SystemZ/memcpy-02.ll
@@ -10,7 +10,7 @@
 
 ; Test the simple i8 case.
 define void @f1(i8 *%ptr1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -21,7 +21,7 @@ define void @f1(i8 *%ptr1) {
 
 ; Test i8 cases where the value is zero-extended to 32 bits.
 define void @f2(i8 *%ptr1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -34,7 +34,7 @@ define void @f2(i8 *%ptr1) {
 
 ; Test i8 cases where the value is zero-extended to 64 bits.
 define void @f3(i8 *%ptr1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -47,7 +47,7 @@ define void @f3(i8 *%ptr1) {
 
 ; Test i8 cases where the value is sign-extended to 32 bits.
 define void @f4(i8 *%ptr1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -60,7 +60,7 @@ define void @f4(i8 *%ptr1) {
 
 ; Test i8 cases where the value is sign-extended to 64 bits.
 define void @f5(i8 *%ptr1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvc 1(1,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i8 *%ptr1, i64 1
@@ -73,7 +73,7 @@ define void @f5(i8 *%ptr1) {
 
 ; Test the simple i16 case.
 define void @f6(i16 *%ptr1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -84,7 +84,7 @@ define void @f6(i16 *%ptr1) {
 
 ; Test i16 cases where the value is zero-extended to 32 bits.
 define void @f7(i16 *%ptr1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -97,7 +97,7 @@ define void @f7(i16 *%ptr1) {
 
 ; Test i16 cases where the value is zero-extended to 64 bits.
 define void @f8(i16 *%ptr1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -110,7 +110,7 @@ define void @f8(i16 *%ptr1) {
 
 ; Test i16 cases where the value is sign-extended to 32 bits.
 define void @f9(i16 *%ptr1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -123,7 +123,7 @@ define void @f9(i16 *%ptr1) {
 
 ; Test i16 cases where the value is sign-extended to 64 bits.
 define void @f10(i16 *%ptr1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mvc 2(2,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i16 *%ptr1, i64 1
@@ -136,7 +136,7 @@ define void @f10(i16 *%ptr1) {
 
 ; Test the simple i32 case.
 define void @f11(i32 *%ptr1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i32 *%ptr1, i64 1
@@ -147,7 +147,7 @@ define void @f11(i32 *%ptr1) {
 
 ; Test i32 cases where the value is zero-extended to 64 bits.
 define void @f12(i32 *%ptr1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i32 *%ptr1, i64 1
@@ -160,7 +160,7 @@ define void @f12(i32 *%ptr1) {
 
 ; Test i32 cases where the value is sign-extended to 64 bits.
 define void @f13(i32 *%ptr1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i32 *%ptr1, i64 1
@@ -173,7 +173,7 @@ define void @f13(i32 *%ptr1) {
 
 ; Test the i64 case.
 define void @f14(i64 *%ptr1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i64 *%ptr1, i64 1
@@ -184,7 +184,7 @@ define void @f14(i64 *%ptr1) {
 
 ; Test the f32 case.
 define void @f15(float *%ptr1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: mvc 4(4,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr float *%ptr1, i64 1
@@ -195,7 +195,7 @@ define void @f15(float *%ptr1) {
 
 ; Test the f64 case.
 define void @f16(double *%ptr1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr double *%ptr1, i64 1
@@ -206,7 +206,7 @@ define void @f16(double *%ptr1) {
 
 ; Test the f128 case.
 define void @f17(fp128 *%ptr1) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: mvc 16(16,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr fp128 *%ptr1, i64 1
@@ -217,7 +217,7 @@ define void @f17(fp128 *%ptr1) {
 
 ; Make sure that we don't use MVC if the load is volatile.
 define void @f18(i64 *%ptr1) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %ptr2 = getelementptr i64 *%ptr1, i64 1
@@ -228,7 +228,7 @@ define void @f18(i64 *%ptr1) {
 
 ; ...likewise the store.
 define void @f19(i64 *%ptr1) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %ptr2 = getelementptr i64 *%ptr1, i64 1
@@ -240,7 +240,7 @@ define void @f19(i64 *%ptr1) {
 ; Test that MVC is used for aligned loads and stores, even if there is
 ; no way of telling whether they alias.
 define void @f20(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: mvc 0(8,%r3), 0(%r2)
 ; CHECK: br %r14
   %val = load i64 *%ptr1
@@ -250,7 +250,7 @@ define void @f20(i64 *%ptr1, i64 *%ptr2) {
 
 ; ...but if the loads aren't aligned, we can't be sure.
 define void @f21(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %val = load i64 *%ptr1, align 2
@@ -260,7 +260,7 @@ define void @f21(i64 *%ptr1, i64 *%ptr2) {
 
 ; Test a case where there is definite overlap.
 define void @f22(i64 %base) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %add = add i64 %base, 1
@@ -273,7 +273,7 @@ define void @f22(i64 %base) {
 
 ; Test that we can use MVC for global addresses for i8.
 define void @f23(i8 *%ptr) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: larl [[REG:%r[0-5]]], g1
 ; CHECK: mvc 0(1,%r2), 0([[REG]])
 ; CHECK: br %r14
@@ -284,7 +284,7 @@ define void @f23(i8 *%ptr) {
 
 ; ...and again with the global on the store.
 define void @f24(i8 *%ptr) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: larl [[REG:%r[0-5]]], g1
 ; CHECK: mvc 0(1,[[REG]]), 0(%r2)
 ; CHECK: br %r14
@@ -295,7 +295,7 @@ define void @f24(i8 *%ptr) {
 
 ; Test that we use LHRL for i16.
 define void @f25(i16 *%ptr) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK: lhrl [[REG:%r[0-5]]], g2
 ; CHECK: sth [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -306,7 +306,7 @@ define void @f25(i16 *%ptr) {
 
 ; ...likewise STHRL.
 define void @f26(i16 *%ptr) {
-; CHECK: f26:
+; CHECK-LABEL: f26:
 ; CHECK: lh [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: sthrl [[REG]], g2
 ; CHECK: br %r14
@@ -317,7 +317,7 @@ define void @f26(i16 *%ptr) {
 
 ; Test that we use LRL for i32.
 define void @f27(i32 *%ptr) {
-; CHECK: f27:
+; CHECK-LABEL: f27:
 ; CHECK: lrl [[REG:%r[0-5]]], g3
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -328,7 +328,7 @@ define void @f27(i32 *%ptr) {
 
 ; ...likewise STRL.
 define void @f28(i32 *%ptr) {
-; CHECK: f28:
+; CHECK-LABEL: f28:
 ; CHECK: l [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: strl [[REG]], g3
 ; CHECK: br %r14
@@ -339,7 +339,7 @@ define void @f28(i32 *%ptr) {
 
 ; Test that we use LGRL for i64.
 define void @f29(i64 *%ptr) {
-; CHECK: f29:
+; CHECK-LABEL: f29:
 ; CHECK: lgrl [[REG:%r[0-5]]], g4
 ; CHECK: stg [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -350,7 +350,7 @@ define void @f29(i64 *%ptr) {
 
 ; ...likewise STGRL.
 define void @f30(i64 *%ptr) {
-; CHECK: f30:
+; CHECK-LABEL: f30:
 ; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: stgrl [[REG]], g4
 ; CHECK: br %r14
@@ -361,7 +361,7 @@ define void @f30(i64 *%ptr) {
 
 ; Test that we can use MVC for global addresses for fp128.
 define void @f31(fp128 *%ptr) {
-; CHECK: f31:
+; CHECK-LABEL: f31:
 ; CHECK: larl [[REG:%r[0-5]]], g5
 ; CHECK: mvc 0(16,%r2), 0([[REG]])
 ; CHECK: br %r14
@@ -372,7 +372,7 @@ define void @f31(fp128 *%ptr) {
 
 ; ...and again with the global on the store.
 define void @f32(fp128 *%ptr) {
-; CHECK: f32:
+; CHECK-LABEL: f32:
 ; CHECK: larl [[REG:%r[0-5]]], g5
 ; CHECK: mvc 0(16,[[REG]]), 0(%r2)
 ; CHECK: br %r14
@@ -383,7 +383,7 @@ define void @f32(fp128 *%ptr) {
 
 ; Test a case where offset disambiguation is enough.
 define void @f33(i64 *%ptr1) {
-; CHECK: f33:
+; CHECK-LABEL: f33:
 ; CHECK: mvc 8(8,%r2), 0(%r2)
 ; CHECK: br %r14
   %ptr2 = getelementptr i64 *%ptr1, i64 1
@@ -394,7 +394,7 @@ define void @f33(i64 *%ptr1) {
 
 ; Test f21 in cases where TBAA tells us there is no alias.
 define void @f34(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f34:
+; CHECK-LABEL: f34:
 ; CHECK: mvc 0(8,%r3), 0(%r2)
 ; CHECK: br %r14
   %val = load i64 *%ptr1, align 2, !tbaa !1
@@ -404,7 +404,7 @@ define void @f34(i64 *%ptr1, i64 *%ptr2) {
 
 ; Test f21 in cases where TBAA is present but doesn't help.
 define void @f35(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f35:
+; CHECK-LABEL: f35:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %val = load i64 *%ptr1, align 2, !tbaa !1
diff --git a/test/CodeGen/SystemZ/memset-01.ll b/test/CodeGen/SystemZ/memset-01.ll
index 1592318b8b8..b272a5bcc69 100644
--- a/test/CodeGen/SystemZ/memset-01.ll
+++ b/test/CodeGen/SystemZ/memset-01.ll
@@ -7,7 +7,7 @@ declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
 
 ; No bytes, i32 version.
 define void @f1(i8 *%dest, i8 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK-NOT: %r3
 ; CHECK: br %r14
@@ -17,7 +17,7 @@ define void @f1(i8 *%dest, i8 %val) {
 
 ; No bytes, i64 version.
 define void @f2(i8 *%dest, i8 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK-NOT: %r3
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i8 *%dest, i8 %val) {
 
 ; 1 byte, i32 version.
 define void @f3(i8 *%dest, i8 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 1, i32 1, i1 false)
@@ -36,7 +36,7 @@ define void @f3(i8 *%dest, i8 %val) {
 
 ; 1 byte, i64 version.
 define void @f4(i8 *%dest, i8 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 1, i32 1, i1 false)
@@ -45,7 +45,7 @@ define void @f4(i8 *%dest, i8 %val) {
 
 ; 2 bytes, i32 version.
 define void @f5(i8 *%dest, i8 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-DAG: stc %r3, 0(%r2)
 ; CHECK-DAG: stc %r3, 1(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f5(i8 *%dest, i8 %val) {
 
 ; 2 bytes, i64 version.
 define void @f6(i8 *%dest, i8 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-DAG: stc %r3, 0(%r2)
 ; CHECK-DAG: stc %r3, 1(%r2)
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define void @f6(i8 *%dest, i8 %val) {
 
 ; 3 bytes, i32 version.
 define void @f7(i8 *%dest, i8 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: mvc 1(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f7(i8 *%dest, i8 %val) {
 
 ; 3 bytes, i64 version.
 define void @f8(i8 *%dest, i8 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: mvc 1(2,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -85,7 +85,7 @@ define void @f8(i8 *%dest, i8 %val) {
 
 ; 257 bytes, i32 version.
 define void @f9(i8 *%dest, i8 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define void @f9(i8 *%dest, i8 %val) {
 
 ; 257 bytes, i64 version.
 define void @f10(i8 *%dest, i8 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define void @f10(i8 *%dest, i8 %val) {
 ; For now expect none, so that the test fails and gets updated when
 ; large copies are implemented.
 define void @f11(i8 *%dest, i8 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 258, i32 1, i1 false)
@@ -116,7 +116,7 @@ define void @f11(i8 *%dest, i8 %val) {
 
 ; 258 bytes, i64 version, with the same comments as above.
 define void @f12(i8 *%dest, i8 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 258, i32 1, i1 false)
diff --git a/test/CodeGen/SystemZ/memset-02.ll b/test/CodeGen/SystemZ/memset-02.ll
index c2c45fb4ae5..b74d907aa9a 100644
--- a/test/CodeGen/SystemZ/memset-02.ll
+++ b/test/CodeGen/SystemZ/memset-02.ll
@@ -7,7 +7,7 @@ declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
 
 ; No bytes, i32 version.
 define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 0, i32 1, i1 false)
@@ -16,7 +16,7 @@ define void @f1(i8 *%dest) {
 
 ; No bytes, i64 version.
 define void @f2(i8 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 0, i32 1, i1 false)
@@ -25,7 +25,7 @@ define void @f2(i8 *%dest) {
 
 ; 1 byte, i32 version.
 define void @f3(i8 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 1, i32 1, i1 false)
@@ -34,7 +34,7 @@ define void @f3(i8 *%dest) {
 
 ; 1 byte, i64 version.
 define void @f4(i8 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 1, i32 1, i1 false)
@@ -43,7 +43,7 @@ define void @f4(i8 *%dest) {
 
 ; 2 bytes, i32 version.
 define void @f5(i8 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhhi 0(%r2), -32640
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 2, i32 1, i1 false)
@@ -52,7 +52,7 @@ define void @f5(i8 *%dest) {
 
 ; 2 bytes, i64 version.
 define void @f6(i8 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvhhi 0(%r2), -32640
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 2, i32 1, i1 false)
@@ -61,7 +61,7 @@ define void @f6(i8 *%dest) {
 
 ; 3 bytes, i32 version.
 define void @f7(i8 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-DAG: mvhhi 0(%r2), -32640
 ; CHECK-DAG: mvi 2(%r2), 128
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define void @f7(i8 *%dest) {
 
 ; 3 bytes, i64 version.
 define void @f8(i8 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-DAG: mvhhi 0(%r2), -32640
 ; CHECK-DAG: mvi 2(%r2), 128
 ; CHECK: br %r14
@@ -81,7 +81,7 @@ define void @f8(i8 *%dest) {
 
 ; 4 bytes, i32 version.
 define void @f9(i8 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: iilf [[REG:%r[0-5]]], 2155905152
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define void @f9(i8 *%dest) {
 
 ; 4 bytes, i64 version.
 define void @f10(i8 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: iilf [[REG:%r[0-5]]], 2155905152
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
@@ -101,7 +101,7 @@ define void @f10(i8 *%dest) {
 
 ; 5 bytes, i32 version.
 define void @f11(i8 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: mvc 1(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -111,7 +111,7 @@ define void @f11(i8 *%dest) {
 
 ; 5 bytes, i64 version.
 define void @f12(i8 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: mvc 1(4,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define void @f12(i8 *%dest) {
 
 ; 257 bytes, i32 version.
 define void @f13(i8 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define void @f13(i8 *%dest) {
 
 ; 257 bytes, i64 version.
 define void @f14(i8 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -143,7 +143,7 @@ define void @f14(i8 *%dest) {
 ; For now expect none, so that the test fails and gets updated when
 ; large copies are implemented.
 define void @f15(i8 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 258, i32 1, i1 false)
@@ -152,7 +152,7 @@ define void @f15(i8 *%dest) {
 
 ; 258 bytes, i64 version, with the same comments as above.
 define void @f16(i8 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 258, i32 1, i1 false)
diff --git a/test/CodeGen/SystemZ/memset-03.ll b/test/CodeGen/SystemZ/memset-03.ll
index b18cca4ec48..1d48f1ad6dc 100644
--- a/test/CodeGen/SystemZ/memset-03.ll
+++ b/test/CodeGen/SystemZ/memset-03.ll
@@ -7,7 +7,7 @@ declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
 
 ; No bytes, i32 version.
 define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 0, i32 1, i1 false)
@@ -16,7 +16,7 @@ define void @f1(i8 *%dest) {
 
 ; No bytes, i64 version.
 define void @f2(i8 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 0, i32 1, i1 false)
@@ -25,7 +25,7 @@ define void @f2(i8 *%dest) {
 
 ; 1 byte, i32 version.
 define void @f3(i8 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 1, i32 1, i1 false)
@@ -34,7 +34,7 @@ define void @f3(i8 *%dest) {
 
 ; 1 byte, i64 version.
 define void @f4(i8 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 1, i32 1, i1 false)
@@ -43,7 +43,7 @@ define void @f4(i8 *%dest) {
 
 ; 2 bytes, i32 version.
 define void @f5(i8 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhhi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 2, i32 1, i1 false)
@@ -52,7 +52,7 @@ define void @f5(i8 *%dest) {
 
 ; 2 bytes, i64 version.
 define void @f6(i8 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvhhi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 2, i32 1, i1 false)
@@ -61,7 +61,7 @@ define void @f6(i8 *%dest) {
 
 ; 3 bytes, i32 version.
 define void @f7(i8 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-DAG: mvhhi 0(%r2), 0
 ; CHECK-DAG: mvi 2(%r2), 0
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define void @f7(i8 *%dest) {
 
 ; 3 bytes, i64 version.
 define void @f8(i8 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-DAG: mvhhi 0(%r2), 0
 ; CHECK-DAG: mvi 2(%r2), 0
 ; CHECK: br %r14
@@ -81,7 +81,7 @@ define void @f8(i8 *%dest) {
 
 ; 4 bytes, i32 version.
 define void @f9(i8 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 4, i32 1, i1 false)
@@ -90,7 +90,7 @@ define void @f9(i8 *%dest) {
 
 ; 4 bytes, i64 version.
 define void @f10(i8 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 4, i32 1, i1 false)
@@ -99,7 +99,7 @@ define void @f10(i8 *%dest) {
 
 ; 5 bytes, i32 version.
 define void @f11(i8 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-DAG: mvhi 0(%r2), 0
 ; CHECK-DAG: mvi 4(%r2), 0
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define void @f11(i8 *%dest) {
 
 ; 5 bytes, i64 version.
 define void @f12(i8 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-DAG: mvhi 0(%r2), 0
 ; CHECK-DAG: mvi 4(%r2), 0
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define void @f12(i8 *%dest) {
 
 ; 6 bytes, i32 version.
 define void @f13(i8 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-DAG: mvhi 0(%r2), 0
 ; CHECK-DAG: mvhhi 4(%r2), 0
 ; CHECK: br %r14
@@ -129,7 +129,7 @@ define void @f13(i8 *%dest) {
 
 ; 6 bytes, i64 version.
 define void @f14(i8 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-DAG: mvhi 0(%r2), 0
 ; CHECK-DAG: mvhhi 4(%r2), 0
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define void @f14(i8 *%dest) {
 
 ; 7 bytes, i32 version.
 define void @f15(i8 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(6,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -149,7 +149,7 @@ define void @f15(i8 *%dest) {
 
 ; 7 bytes, i64 version.
 define void @f16(i8 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(6,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -159,7 +159,7 @@ define void @f16(i8 *%dest) {
 
 ; 8 bytes, i32 version.
 define void @f17(i8 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: mvghi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 8, i32 1, i1 false)
@@ -168,7 +168,7 @@ define void @f17(i8 *%dest) {
 
 ; 8 bytes, i64 version.
 define void @f18(i8 *%dest) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: mvghi 0(%r2), 0
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 8, i32 1, i1 false)
@@ -177,7 +177,7 @@ define void @f18(i8 *%dest) {
 
 ; 9 bytes, i32 version.
 define void @f19(i8 *%dest) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvi 8(%r2), 0
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define void @f19(i8 *%dest) {
 
 ; 9 bytes, i64 version.
 define void @f20(i8 *%dest) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvi 8(%r2), 0
 ; CHECK: br %r14
@@ -197,7 +197,7 @@ define void @f20(i8 *%dest) {
 
 ; 10 bytes, i32 version.
 define void @f21(i8 *%dest) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvhhi 8(%r2), 0
 ; CHECK: br %r14
@@ -207,7 +207,7 @@ define void @f21(i8 *%dest) {
 
 ; 10 bytes, i64 version.
 define void @f22(i8 *%dest) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvhhi 8(%r2), 0
 ; CHECK: br %r14
@@ -217,7 +217,7 @@ define void @f22(i8 *%dest) {
 
 ; 11 bytes, i32 version.
 define void @f23(i8 *%dest) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(10,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -227,7 +227,7 @@ define void @f23(i8 *%dest) {
 
 ; 11 bytes, i64 version.
 define void @f24(i8 *%dest) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(10,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -237,7 +237,7 @@ define void @f24(i8 *%dest) {
 
 ; 12 bytes, i32 version.
 define void @f25(i8 *%dest) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvhi 8(%r2), 0
 ; CHECK: br %r14
@@ -247,7 +247,7 @@ define void @f25(i8 *%dest) {
 
 ; 12 bytes, i64 version.
 define void @f26(i8 *%dest) {
-; CHECK: f26:
+; CHECK-LABEL: f26:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvhi 8(%r2), 0
 ; CHECK: br %r14
@@ -257,7 +257,7 @@ define void @f26(i8 *%dest) {
 
 ; 13 bytes, i32 version.
 define void @f27(i8 *%dest) {
-; CHECK: f27:
+; CHECK-LABEL: f27:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(12,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -267,7 +267,7 @@ define void @f27(i8 *%dest) {
 
 ; 13 bytes, i64 version.
 define void @f28(i8 *%dest) {
-; CHECK: f28:
+; CHECK-LABEL: f28:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(12,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -277,7 +277,7 @@ define void @f28(i8 *%dest) {
 
 ; 14 bytes, i32 version.
 define void @f29(i8 *%dest) {
-; CHECK: f29:
+; CHECK-LABEL: f29:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(13,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -287,7 +287,7 @@ define void @f29(i8 *%dest) {
 
 ; 14 bytes, i64 version.
 define void @f30(i8 *%dest) {
-; CHECK: f30:
+; CHECK-LABEL: f30:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(13,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -297,7 +297,7 @@ define void @f30(i8 *%dest) {
 
 ; 15 bytes, i32 version.
 define void @f31(i8 *%dest) {
-; CHECK: f31:
+; CHECK-LABEL: f31:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(14,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -307,7 +307,7 @@ define void @f31(i8 *%dest) {
 
 ; 15 bytes, i64 version.
 define void @f32(i8 *%dest) {
-; CHECK: f32:
+; CHECK-LABEL: f32:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(14,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -317,7 +317,7 @@ define void @f32(i8 *%dest) {
 
 ; 16 bytes, i32 version.
 define void @f33(i8 *%dest) {
-; CHECK: f33:
+; CHECK-LABEL: f33:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvghi 8(%r2), 0
 ; CHECK: br %r14
@@ -327,7 +327,7 @@ define void @f33(i8 *%dest) {
 
 ; 16 bytes, i64 version.
 define void @f34(i8 *%dest) {
-; CHECK: f34:
+; CHECK-LABEL: f34:
 ; CHECK-DAG: mvghi 0(%r2), 0
 ; CHECK-DAG: mvghi 8(%r2), 0
 ; CHECK: br %r14
@@ -337,7 +337,7 @@ define void @f34(i8 *%dest) {
 
 ; 17 bytes, i32 version.
 define void @f35(i8 *%dest) {
-; CHECK: f35:
+; CHECK-LABEL: f35:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(16,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -347,7 +347,7 @@ define void @f35(i8 *%dest) {
 
 ; 17 bytes, i64 version.
 define void @f36(i8 *%dest) {
-; CHECK: f36:
+; CHECK-LABEL: f36:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(16,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -357,7 +357,7 @@ define void @f36(i8 *%dest) {
 
 ; 257 bytes, i32 version.
 define void @f37(i8 *%dest) {
-; CHECK: f37:
+; CHECK-LABEL: f37:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -367,7 +367,7 @@ define void @f37(i8 *%dest) {
 
 ; 257 bytes, i64 version.
 define void @f38(i8 *%dest) {
-; CHECK: f38:
+; CHECK-LABEL: f38:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -379,7 +379,7 @@ define void @f38(i8 *%dest) {
 ; For now expect none, so that the test fails and gets updated when
 ; large copies are implemented.
 define void @f39(i8 *%dest) {
-; CHECK: f39:
+; CHECK-LABEL: f39:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 258, i32 1, i1 false)
@@ -388,7 +388,7 @@ define void @f39(i8 *%dest) {
 
 ; 258 bytes, i64 version, with the same comments as above.
 define void @f40(i8 *%dest) {
-; CHECK: f40:
+; CHECK-LABEL: f40:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 258, i32 1, i1 false)
diff --git a/test/CodeGen/SystemZ/memset-04.ll b/test/CodeGen/SystemZ/memset-04.ll
index 679e21f8fce..92886921b07 100644
--- a/test/CodeGen/SystemZ/memset-04.ll
+++ b/test/CodeGen/SystemZ/memset-04.ll
@@ -7,7 +7,7 @@ declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
 
 ; No bytes, i32 version.
 define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 0, i32 1, i1 false)
@@ -16,7 +16,7 @@ define void @f1(i8 *%dest) {
 
 ; No bytes, i64 version.
 define void @f2(i8 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 0, i32 1, i1 false)
@@ -25,7 +25,7 @@ define void @f2(i8 *%dest) {
 
 ; 1 byte, i32 version.
 define void @f3(i8 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 1, i32 1, i1 false)
@@ -34,7 +34,7 @@ define void @f3(i8 *%dest) {
 
 ; 1 byte, i64 version.
 define void @f4(i8 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 1, i32 1, i1 false)
@@ -43,7 +43,7 @@ define void @f4(i8 *%dest) {
 
 ; 2 bytes, i32 version.
 define void @f5(i8 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 2, i32 1, i1 false)
@@ -52,7 +52,7 @@ define void @f5(i8 *%dest) {
 
 ; 2 bytes, i64 version.
 define void @f6(i8 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 2, i32 1, i1 false)
@@ -61,7 +61,7 @@ define void @f6(i8 *%dest) {
 
 ; 3 bytes, i32 version.
 define void @f7(i8 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-DAG: mvhhi 0(%r2), -1
 ; CHECK-DAG: mvi 2(%r2), 255
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define void @f7(i8 *%dest) {
 
 ; 3 bytes, i64 version.
 define void @f8(i8 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-DAG: mvhhi 0(%r2), -1
 ; CHECK-DAG: mvi 2(%r2), 255
 ; CHECK: br %r14
@@ -81,7 +81,7 @@ define void @f8(i8 *%dest) {
 
 ; 4 bytes, i32 version.
 define void @f9(i8 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mvhi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 4, i32 1, i1 false)
@@ -90,7 +90,7 @@ define void @f9(i8 *%dest) {
 
 ; 4 bytes, i64 version.
 define void @f10(i8 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mvhi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 4, i32 1, i1 false)
@@ -99,7 +99,7 @@ define void @f10(i8 *%dest) {
 
 ; 5 bytes, i32 version.
 define void @f11(i8 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-DAG: mvhi 0(%r2), -1
 ; CHECK-DAG: mvi 4(%r2), 255
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define void @f11(i8 *%dest) {
 
 ; 5 bytes, i64 version.
 define void @f12(i8 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-DAG: mvhi 0(%r2), -1
 ; CHECK-DAG: mvi 4(%r2), 255
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define void @f12(i8 *%dest) {
 
 ; 6 bytes, i32 version.
 define void @f13(i8 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-DAG: mvhi 0(%r2), -1
 ; CHECK-DAG: mvhhi 4(%r2), -1
 ; CHECK: br %r14
@@ -129,7 +129,7 @@ define void @f13(i8 *%dest) {
 
 ; 6 bytes, i64 version.
 define void @f14(i8 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-DAG: mvhi 0(%r2), -1
 ; CHECK-DAG: mvhhi 4(%r2), -1
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define void @f14(i8 *%dest) {
 
 ; 7 bytes, i32 version.
 define void @f15(i8 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(6,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -149,7 +149,7 @@ define void @f15(i8 *%dest) {
 
 ; 7 bytes, i64 version.
 define void @f16(i8 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(6,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -159,7 +159,7 @@ define void @f16(i8 *%dest) {
 
 ; 8 bytes, i32 version.
 define void @f17(i8 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: mvghi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 8, i32 1, i1 false)
@@ -168,7 +168,7 @@ define void @f17(i8 *%dest) {
 
 ; 8 bytes, i64 version.
 define void @f18(i8 *%dest) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: mvghi 0(%r2), -1
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 8, i32 1, i1 false)
@@ -177,7 +177,7 @@ define void @f18(i8 *%dest) {
 
 ; 9 bytes, i32 version.
 define void @f19(i8 *%dest) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvi 8(%r2), 255
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define void @f19(i8 *%dest) {
 
 ; 9 bytes, i64 version.
 define void @f20(i8 *%dest) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvi 8(%r2), 255
 ; CHECK: br %r14
@@ -197,7 +197,7 @@ define void @f20(i8 *%dest) {
 
 ; 10 bytes, i32 version.
 define void @f21(i8 *%dest) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvhhi 8(%r2), -1
 ; CHECK: br %r14
@@ -207,7 +207,7 @@ define void @f21(i8 *%dest) {
 
 ; 10 bytes, i64 version.
 define void @f22(i8 *%dest) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvhhi 8(%r2), -1
 ; CHECK: br %r14
@@ -217,7 +217,7 @@ define void @f22(i8 *%dest) {
 
 ; 11 bytes, i32 version.
 define void @f23(i8 *%dest) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(10,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -227,7 +227,7 @@ define void @f23(i8 *%dest) {
 
 ; 11 bytes, i64 version.
 define void @f24(i8 *%dest) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(10,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -237,7 +237,7 @@ define void @f24(i8 *%dest) {
 
 ; 12 bytes, i32 version.
 define void @f25(i8 *%dest) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvhi 8(%r2), -1
 ; CHECK: br %r14
@@ -247,7 +247,7 @@ define void @f25(i8 *%dest) {
 
 ; 12 bytes, i64 version.
 define void @f26(i8 *%dest) {
-; CHECK: f26:
+; CHECK-LABEL: f26:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvhi 8(%r2), -1
 ; CHECK: br %r14
@@ -257,7 +257,7 @@ define void @f26(i8 *%dest) {
 
 ; 13 bytes, i32 version.
 define void @f27(i8 *%dest) {
-; CHECK: f27:
+; CHECK-LABEL: f27:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(12,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -267,7 +267,7 @@ define void @f27(i8 *%dest) {
 
 ; 13 bytes, i64 version.
 define void @f28(i8 *%dest) {
-; CHECK: f28:
+; CHECK-LABEL: f28:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(12,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -277,7 +277,7 @@ define void @f28(i8 *%dest) {
 
 ; 14 bytes, i32 version.
 define void @f29(i8 *%dest) {
-; CHECK: f29:
+; CHECK-LABEL: f29:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(13,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -287,7 +287,7 @@ define void @f29(i8 *%dest) {
 
 ; 14 bytes, i64 version.
 define void @f30(i8 *%dest) {
-; CHECK: f30:
+; CHECK-LABEL: f30:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(13,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -297,7 +297,7 @@ define void @f30(i8 *%dest) {
 
 ; 15 bytes, i32 version.
 define void @f31(i8 *%dest) {
-; CHECK: f31:
+; CHECK-LABEL: f31:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(14,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -307,7 +307,7 @@ define void @f31(i8 *%dest) {
 
 ; 15 bytes, i64 version.
 define void @f32(i8 *%dest) {
-; CHECK: f32:
+; CHECK-LABEL: f32:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(14,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -317,7 +317,7 @@ define void @f32(i8 *%dest) {
 
 ; 16 bytes, i32 version.
 define void @f33(i8 *%dest) {
-; CHECK: f33:
+; CHECK-LABEL: f33:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvghi 8(%r2), -1
 ; CHECK: br %r14
@@ -327,7 +327,7 @@ define void @f33(i8 *%dest) {
 
 ; 16 bytes, i64 version.
 define void @f34(i8 *%dest) {
-; CHECK: f34:
+; CHECK-LABEL: f34:
 ; CHECK-DAG: mvghi 0(%r2), -1
 ; CHECK-DAG: mvghi 8(%r2), -1
 ; CHECK: br %r14
@@ -337,7 +337,7 @@ define void @f34(i8 *%dest) {
 
 ; 17 bytes, i32 version.
 define void @f35(i8 *%dest) {
-; CHECK: f35:
+; CHECK-LABEL: f35:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(16,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -347,7 +347,7 @@ define void @f35(i8 *%dest) {
 
 ; 17 bytes, i64 version.
 define void @f36(i8 *%dest) {
-; CHECK: f36:
+; CHECK-LABEL: f36:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(16,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -357,7 +357,7 @@ define void @f36(i8 *%dest) {
 
 ; 257 bytes, i32 version.
 define void @f37(i8 *%dest) {
-; CHECK: f37:
+; CHECK-LABEL: f37:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -367,7 +367,7 @@ define void @f37(i8 *%dest) {
 
 ; 257 bytes, i64 version.
 define void @f38(i8 *%dest) {
-; CHECK: f38:
+; CHECK-LABEL: f38:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: mvc 1(256,%r2), 0(%r2)
 ; CHECK: br %r14
@@ -379,7 +379,7 @@ define void @f38(i8 *%dest) {
 ; For now expect none, so that the test fails and gets updated when
 ; large copies are implemented.
 define void @f39(i8 *%dest) {
-; CHECK: f39:
+; CHECK-LABEL: f39:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 258, i32 1, i1 false)
@@ -388,7 +388,7 @@ define void @f39(i8 *%dest) {
 
 ; 258 bytes, i64 version, with the same comments as above.
 define void @f40(i8 *%dest) {
-; CHECK: f40:
+; CHECK-LABEL: f40:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 258, i32 1, i1 false)
diff --git a/test/CodeGen/SystemZ/or-01.ll b/test/CodeGen/SystemZ/or-01.ll
index ab869c76ebe..ee0a39228d8 100644
--- a/test/CodeGen/SystemZ/or-01.ll
+++ b/test/CodeGen/SystemZ/or-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check OR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: or %r2, %r3
 ; CHECK: br %r14
   %or = or i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the O range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned O range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: o %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use OY instead of O.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned OY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned OY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the OY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that O allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: o %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that OY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: oy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that ORs of spilled values can use O rather than OR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: o %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-02.ll b/test/CodeGen/SystemZ/or-02.ll
index 377a3e604c6..267be2089e4 100644
--- a/test/CodeGen/SystemZ/or-02.ll
+++ b/test/CodeGen/SystemZ/or-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful OILL value.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
   %or = or i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the OILL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oill %r2, 65535
 ; CHECK: br %r14
   %or = or i32 %a, 65535
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; Check the lowest useful OILH range, which is the next value up.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh %r2, 1
 ; CHECK: br %r14
   %or = or i32 %a, 65536
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the lowest useful OILF value, which is the next value up again.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilf %r2, 65537
 ; CHECK: br %r14
   %or = or i32 %a, 65537
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a) {
 
 ; Check the high end of the OILH range.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh %r2, 65535
 ; CHECK: br %r14
   %or = or i32 %a, -65536
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the next value up, which must use OILF instead.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilf %r2, 4294901761
 ; CHECK: br %r14
   %or = or i32 %a, -65535
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a) {
 
 ; Check the highest useful OILF value.
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oilf %r2, 4294967294
 ; CHECK: br %r14
   %or = or i32 %a, -2
diff --git a/test/CodeGen/SystemZ/or-03.ll b/test/CodeGen/SystemZ/or-03.ll
index cf85b0ae7fa..3e373673686 100644
--- a/test/CodeGen/SystemZ/or-03.ll
+++ b/test/CodeGen/SystemZ/or-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check OGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ogr %r2, %r3
 ; CHECK: br %r14
   %or = or i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check OG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned OG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: og %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned OG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: og %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the OG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: og %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that OG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: og %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that ORs of spilled values can use OG rather than OGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: og %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-04.ll b/test/CodeGen/SystemZ/or-04.ll
index a8278423981..87a30d56454 100644
--- a/test/CodeGen/SystemZ/or-04.ll
+++ b/test/CodeGen/SystemZ/or-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful OILL value.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the OILL range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oill %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 65535
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the lowest useful OILH value, which is the next value up.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 65536
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the lowest useful OILF value, which is the next value up again.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilf %r2, 4294901759
 ; CHECK: br %r14
   %or = or i64 %a, 4294901759
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the high end of the OILH range.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 4294901760
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the high end of the OILF range.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilf %r2, 4294967295
 ; CHECK: br %r14
   %or = or i64 %a, 4294967295
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the lowest useful OIHL value, which is the next value up.
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oihl %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 4294967296
@@ -67,7 +67,7 @@ define i64 @f7(i64 %a) {
 
 ; Check the next value up again, which must use two ORs.
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oihl %r2, 1
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the high end of the OILL range.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: oihl %r2, 1
 ; CHECK: oill %r2, 65535
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the next value up, which must use OILH
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: oihl %r2, 1
 ; CHECK: oilh %r2, 1
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define i64 @f10(i64 %a) {
 
 ; Check the next value up again, which must use OILF
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: oihl %r2, 1
 ; CHECK: oilf %r2, 65537
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the high end of the OIHL range.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: oihl %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 281470681743360
@@ -117,7 +117,7 @@ define i64 @f12(i64 %a) {
 ; Check a combination of the high end of the OIHL range and the high end
 ; of the OILF range.
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: oihl %r2, 65535
 ; CHECK: oilf %r2, 4294967295
 ; CHECK: br %r14
@@ -127,7 +127,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the lowest useful OIHH value.
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: oihh %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 281474976710656
@@ -136,7 +136,7 @@ define i64 @f14(i64 %a) {
 
 ; Check the next value up, which needs two ORs.
 define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: oihh %r2, 1
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
@@ -146,7 +146,7 @@ define i64 @f15(i64 %a) {
 
 ; Check the lowest useful OIHF value.
 define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: oihf %r2, 65537
 ; CHECK: br %r14
   %or = or i64 %a, 281479271677952
@@ -155,7 +155,7 @@ define i64 @f16(i64 %a) {
 
 ; Check the high end of the OIHH range.
 define i64 @f17(i64 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: oihh %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 18446462598732840960
@@ -164,7 +164,7 @@ define i64 @f17(i64 %a) {
 
 ; Check the high end of the OIHF range.
 define i64 @f18(i64 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: oihf %r2, 4294967295
 ; CHECK: br %r14
   %or = or i64 %a, -4294967296
@@ -173,7 +173,7 @@ define i64 @f18(i64 %a) {
 
 ; Check the highest useful OR value.
 define i64 @f19(i64 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: oihf %r2, 4294967295
 ; CHECK: oilf %r2, 4294967294
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-05.ll b/test/CodeGen/SystemZ/or-05.ll
index 9b6c10d4b5c..d9058912867 100644
--- a/test/CodeGen/SystemZ/or-05.ll
+++ b/test/CodeGen/SystemZ/or-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful constant, expressed as a signed integer.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a signed integer.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the lowest useful constant, expressed as an unsigned integer.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a unsigned integer.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check the high end of the OI range.
 define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oi 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
 
 ; Check the next byte up, which should use OIY instead of OI.
 define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oiy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
 
 ; Check the high end of the OIY range.
 define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oiy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: oi 0(%r2), 127
 ; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
 
 ; Check the high end of the negative OIY range.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: oiy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
 
 ; Check the low end of the OIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: oiy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -524289
 ; CHECK: oi 0(%r2), 127
 ; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
 
 ; Check that OI does not allow an index
 define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r2, %r3
 ; CHECK: oi 4095(%r2), 127
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
 
 ; Check that OIY does not allow an index
 define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agr %r2, %r3
 ; CHECK: oiy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-06.ll b/test/CodeGen/SystemZ/or-06.ll
index a24a18a191f..0a865d35094 100644
--- a/test/CodeGen/SystemZ/or-06.ll
+++ b/test/CodeGen/SystemZ/or-06.ll
@@ -5,7 +5,7 @@
 
 ; Zero extension to 32 bits, negative constant.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
 
 ; Zero extension to 64 bits, negative constant.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
 
 ; Zero extension to 32 bits, positive constant.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
 
 ; Zero extension to 64 bits, positive constant.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
 
 ; Sign extension to 32 bits, negative constant.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
 
 ; Sign extension to 64 bits, negative constant.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
 
 ; Sign extension to 32 bits, positive constant.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
 
 ; Sign extension to 64 bits, positive constant.
 define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll
index 178fa4f2166..f5aeaf14dbd 100644
--- a/test/CodeGen/SystemZ/risbg-01.ll
+++ b/test/CodeGen/SystemZ/risbg-01.ll
@@ -4,7 +4,7 @@
 
 ; Test an extraction of bit 0 from a right-shifted value.
 define i32 @f1(i32 %foo) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: risbg %r2, %r2, 63, 191, 54
 ; CHECK: br %r14
   %shr = lshr i32 %foo, 10
@@ -14,7 +14,7 @@ define i32 @f1(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f2(i64 %foo) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: risbg %r2, %r2, 63, 191, 54
 ; CHECK: br %r14
   %shr = lshr i64 %foo, 10
@@ -24,7 +24,7 @@ define i64 @f2(i64 %foo) {
 
 ; Test an extraction of other bits from a right-shifted value.
 define i32 @f3(i32 %foo) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: risbg %r2, %r2, 60, 189, 42
 ; CHECK: br %r14
   %shr = lshr i32 %foo, 22
@@ -34,7 +34,7 @@ define i32 @f3(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f4(i64 %foo) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: risbg %r2, %r2, 60, 189, 42
 ; CHECK: br %r14
   %shr = lshr i64 %foo, 22
@@ -45,7 +45,7 @@ define i64 @f4(i64 %foo) {
 ; Test an extraction of most bits from a right-shifted value.
 ; The range should be reduced to exclude the zeroed high bits.
 define i32 @f5(i32 %foo) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: risbg %r2, %r2, 34, 188, 62
 ; CHECK: br %r14
   %shr = lshr i32 %foo, 2
@@ -55,7 +55,7 @@ define i32 @f5(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f6(i64 %foo) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: risbg %r2, %r2, 2, 188, 62
 ; CHECK: br %r14
   %shr = lshr i64 %foo, 2
@@ -66,7 +66,7 @@ define i64 @f6(i64 %foo) {
 ; Try the next value up (mask ....1111001).  The mask itself is suitable
 ; for RISBG, but the shift is still needed.
 define i32 @f7(i32 %foo) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srl %r2, 2
 ; CHECK: risbg %r2, %r2, 63, 188, 0
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i32 @f7(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f8(i64 %foo) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srlg [[REG:%r[0-5]]], %r2, 2
 ; CHECK: risbg %r2, [[REG]], 63, 188, 0
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define i64 @f8(i64 %foo) {
 ; Test an extraction of bits from a left-shifted value.  The range should
 ; be reduced to exclude the zeroed low bits.
 define i32 @f9(i32 %foo) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: risbg %r2, %r2, 56, 189, 2
 ; CHECK: br %r14
   %shr = shl i32 %foo, 2
@@ -99,7 +99,7 @@ define i32 @f9(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f10(i64 %foo) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: risbg %r2, %r2, 56, 189, 2
 ; CHECK: br %r14
   %shr = shl i64 %foo, 2
@@ -110,7 +110,7 @@ define i64 @f10(i64 %foo) {
 ; Try a wrap-around mask (mask ....111100001111).  The mask itself is suitable
 ; for RISBG, but the shift is still needed.
 define i32 @f11(i32 %foo) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sll %r2, 2
 ; CHECK: risbg %r2, %r2, 60, 183, 0
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i32 @f11(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f12(i64 %foo) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: sllg [[REG:%r[0-5]]], %r2, 2
 ; CHECK: risbg %r2, [[REG]], 60, 183, 0
 ; CHECK: br %r14
@@ -134,7 +134,7 @@ define i64 @f12(i64 %foo) {
 ; This is equivalent to the lshr case, because the bits from the
 ; shl are not used.
 define i32 @f13(i32 %foo) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: risbg %r2, %r2, 56, 188, 46
 ; CHECK: br %r14
   %parta = shl i32 %foo, 14
@@ -146,7 +146,7 @@ define i32 @f13(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f14(i64 %foo) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: risbg %r2, %r2, 56, 188, 14
 ; CHECK: br %r14
   %parta = shl i64 %foo, 14
@@ -158,7 +158,7 @@ define i64 @f14(i64 %foo) {
 
 ; Try a case in which only the bits from the shl are used.
 define i32 @f15(i32 %foo) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: risbg %r2, %r2, 47, 177, 14
 ; CHECK: br %r14
   %parta = shl i32 %foo, 14
@@ -170,7 +170,7 @@ define i32 @f15(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f16(i64 %foo) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: risbg %r2, %r2, 47, 177, 14
 ; CHECK: br %r14
   %parta = shl i64 %foo, 14
@@ -184,7 +184,7 @@ define i64 @f16(i64 %foo) {
 ; This needs a separate shift (although RISBLG would be better
 ; if supported).
 define i32 @f17(i32 %foo) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: rll [[REG:%r[0-5]]], %r2, 4
 ; CHECK: risbg %r2, [[REG]], 57, 190, 0
 ; CHECK: br %r14
@@ -197,7 +197,7 @@ define i32 @f17(i32 %foo) {
 
 ; ...and for i64, where RISBG should do the rotate too.
 define i64 @f18(i64 %foo) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: risbg %r2, %r2, 57, 190, 4
 ; CHECK: br %r14
   %parta = shl i64 %foo, 4
@@ -210,7 +210,7 @@ define i64 @f18(i64 %foo) {
 ; Test an arithmetic shift right in which some of the sign bits are kept.
 ; The SRA is still needed.
 define i32 @f19(i32 %foo) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: sra %r2, 28
 ; CHECK: risbg %r2, %r2, 59, 190, 0
 ; CHECK: br %r14
@@ -221,7 +221,7 @@ define i32 @f19(i32 %foo) {
 
 ; ...and again with i64.
 define i64 @f20(i64 %foo) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: srag [[REG:%r[0-5]]], %r2, 60
 ; CHECK: risbg %r2, [[REG]], 59, 190, 0
 ; CHECK: br %r14
@@ -234,7 +234,7 @@ define i64 @f20(i64 %foo) {
 ; Introduce a second use of %shr so that the ashr doesn't decompose to
 ; an lshr.
 define i32 @f21(i32 %foo, i32 *%dest) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: risbg %r2, %r2, 60, 190, 36
 ; CHECK: br %r14
   %shr = ashr i32 %foo, 28
@@ -245,7 +245,7 @@ define i32 @f21(i32 %foo, i32 *%dest) {
 
 ; ...and again with i64.
 define i64 @f22(i64 %foo, i64 *%dest) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: risbg %r2, %r2, 60, 190, 4
 ; CHECK: br %r14
   %shr = ashr i64 %foo, 60
@@ -257,7 +257,7 @@ define i64 @f22(i64 %foo, i64 *%dest) {
 ; Check that we use RISBG for shifted values even if the AND is a
 ; natural zero extension.
 define i64 @f23(i64 %foo) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: risbg %r2, %r2, 56, 191, 62
 ; CHECK: br %r14
   %shr = lshr i64 %foo, 2
diff --git a/test/CodeGen/SystemZ/shift-01.ll b/test/CodeGen/SystemZ/shift-01.ll
index e5a459aaa82..5dab36b379c 100644
--- a/test/CodeGen/SystemZ/shift-01.ll
+++ b/test/CodeGen/SystemZ/shift-01.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SLL range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sll %r2, 1
 ; CHECK: br %r14
   %shift = shl i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined SLL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sll %r2, 31
 ; CHECK: br %r14
   %shift = shl i32 %a, 31
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sll %r2, 32
 ; CHECK: br %r14
   %shift = shl i32 %a, 32
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: sll %r2, -1{{.*}}
 ; CHECK: br %r14
   %sub = sub i32 %amt, 1
@@ -41,7 +41,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sll %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = shl i32 %a, %amt
@@ -50,7 +50,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sll %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -60,7 +60,7 @@ define i32 @f6(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sll %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -72,7 +72,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sll %r2, 4095(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 4095
@@ -82,7 +82,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ahi %r3, 4096
 ; CHECK: sll %r2, 0(%r3)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: sll %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: sll %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-02.ll b/test/CodeGen/SystemZ/shift-02.ll
index 38093a8ff7a..27e73cd3a1f 100644
--- a/test/CodeGen/SystemZ/shift-02.ll
+++ b/test/CodeGen/SystemZ/shift-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRL range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: srl %r2, 1
 ; CHECK: br %r14
   %shift = lshr i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined SRL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: srl %r2, 31
 ; CHECK: br %r14
   %shift = lshr i32 %a, 31
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: srl %r2, 32
 ; CHECK: br %r14
   %shift = lshr i32 %a, 32
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: srl %r2, -1{{.*}}
 ; CHECK: br %r14
   %sub = sub i32 %amt, 1
@@ -41,7 +41,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: srl %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = lshr i32 %a, %amt
@@ -50,7 +50,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: srl %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -60,7 +60,7 @@ define i32 @f6(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srl %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -72,7 +72,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srl %r2, 4095(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 4095
@@ -82,7 +82,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ahi %r3, 4096
 ; CHECK: srl %r2, 0(%r3)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: srl %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: srl %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-03.ll b/test/CodeGen/SystemZ/shift-03.ll
index ca510f3c429..c45ae48b407 100644
--- a/test/CodeGen/SystemZ/shift-03.ll
+++ b/test/CodeGen/SystemZ/shift-03.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRA range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sra %r2, 1
 ; CHECK: br %r14
   %shift = ashr i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined SRA range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sra %r2, 31
 ; CHECK: br %r14
   %shift = ashr i32 %a, 31
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sra %r2, 32
 ; CHECK: br %r14
   %shift = ashr i32 %a, 32
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: sra %r2, -1{{.*}}
 ; CHECK: br %r14
   %sub = sub i32 %amt, 1
@@ -41,7 +41,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sra %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = ashr i32 %a, %amt
@@ -50,7 +50,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sra %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -60,7 +60,7 @@ define i32 @f6(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sra %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -72,7 +72,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sra %r2, 4095(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 4095
@@ -82,7 +82,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ahi %r3, 4096
 ; CHECK: sra %r2, 0(%r3)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: sra %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: sra %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-04.ll b/test/CodeGen/SystemZ/shift-04.ll
index 0146a86ee06..04b39d002c5 100644
--- a/test/CodeGen/SystemZ/shift-04.ll
+++ b/test/CodeGen/SystemZ/shift-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the RLL range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rll %r2, %r2, 1
 ; CHECK: br %r14
   %parta = shl i32 %a, 1
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined RLL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: rll %r2, %r2, 31
 ; CHECK: br %r14
   %parta = shl i32 %a, 31
@@ -26,7 +26,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: rll
 ; CHECK: br %r14
   %parta = shl i32 %a, 32
@@ -37,7 +37,7 @@ define i32 @f3(i32 %a) {
 
 ; Check variable shifts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: rll %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %amtb = sub i32 32, %amt
@@ -49,7 +49,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: rll %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -62,7 +62,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f6(i32 %a, i64 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: rll %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -76,7 +76,7 @@ define i32 @f6(i32 %a, i64 %amt) {
 
 ; ...and again with a different truncation representation.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: rll %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -92,7 +92,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: rll %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 524287
@@ -106,7 +106,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r3, 524288
 ; CHECK: rll %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i32 @f10(i32 %a, i32 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: rll %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %suba = sub i32 %amt, 1
@@ -134,7 +134,7 @@ define i32 @f10(i32 %a, i32 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i32 @f11(i32 %a, i32 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: rll %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %suba = sub i32 %amt, 524288
@@ -148,7 +148,7 @@ define i32 @f11(i32 %a, i32 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i32 @f12(i32 %a, i32 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: afi %r3, -524289
 ; CHECK: rll %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define i32 @f12(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f13(i32 %a, i32 %b, i32 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: rll %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -176,7 +176,7 @@ define i32 @f13(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f14(i32 %a, i32 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: rll %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-05.ll b/test/CodeGen/SystemZ/shift-05.ll
index 8c0ca9381bc..833b2fbae1e 100644
--- a/test/CodeGen/SystemZ/shift-05.ll
+++ b/test/CodeGen/SystemZ/shift-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SLLG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK: br %r14
   %shift = shl i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined SLLG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg %r2, %r2, 63
 ; CHECK: br %r14
   %shift = shl i64 %a, 63
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sllg
 ; CHECK: br %r14
   %shift = shl i64 %a, 64
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = shl i64 %a, %amt
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -61,7 +61,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -73,7 +73,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -84,7 +84,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: sllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sllg %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 1
@@ -106,7 +106,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sllg %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 524288
@@ -117,7 +117,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: sllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -128,7 +128,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: sllg %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: sllg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-06.ll b/test/CodeGen/SystemZ/shift-06.ll
index 5f600b45a88..74cae1213a3 100644
--- a/test/CodeGen/SystemZ/shift-06.ll
+++ b/test/CodeGen/SystemZ/shift-06.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRLG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK: br %r14
   %shift = lshr i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined SRLG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: srlg %r2, %r2, 63
 ; CHECK: br %r14
   %shift = lshr i64 %a, 63
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: srlg
 ; CHECK: br %r14
   %shift = lshr i64 %a, 64
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: srlg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = lshr i64 %a, %amt
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: srlg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: srlg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -61,7 +61,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srlg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -73,7 +73,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srlg %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -84,7 +84,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: srlg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: srlg %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 1
@@ -106,7 +106,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: srlg %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 524288
@@ -117,7 +117,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: srlg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -128,7 +128,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: srlg %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: srlg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-07.ll b/test/CodeGen/SystemZ/shift-07.ll
index ef583e8f3f0..712849df8ad 100644
--- a/test/CodeGen/SystemZ/shift-07.ll
+++ b/test/CodeGen/SystemZ/shift-07.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRAG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: srag %r2, %r2, 1
 ; CHECK: br %r14
   %shift = ashr i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined SRAG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: srag %r2, %r2, 63
 ; CHECK: br %r14
   %shift = ashr i64 %a, 63
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: srag
 ; CHECK: br %r14
   %shift = ashr i64 %a, 64
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: srag %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = ashr i64 %a, %amt
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: srag %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: srag %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -61,7 +61,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srag %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -73,7 +73,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srag %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -84,7 +84,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: srag %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: srag %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 1
@@ -106,7 +106,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: srag %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 524288
@@ -117,7 +117,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: srag %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -128,7 +128,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: srag %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: srag %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-08.ll b/test/CodeGen/SystemZ/shift-08.ll
index 0688a067167..47283b50221 100644
--- a/test/CodeGen/SystemZ/shift-08.ll
+++ b/test/CodeGen/SystemZ/shift-08.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the RLLG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rllg %r2, %r2, 1
 ; CHECK: br %r14
   %parta = shl i64 %a, 1
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined RLLG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: rllg %r2, %r2, 63
 ; CHECK: br %r14
   %parta = shl i64 %a, 63
@@ -26,7 +26,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: rllg
 ; CHECK: br %r14
   %parta = shl i64 %a, 64
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: rllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %amtb = sub i64 64, %amt
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: rllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -62,7 +62,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: rllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -77,7 +77,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: rllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -93,7 +93,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: rllg %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -107,7 +107,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: rllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: rllg %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %suba = sub i64 %amt, 1
@@ -135,7 +135,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: rllg %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %suba = sub i64 %amt, 524288
@@ -149,7 +149,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: rllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -163,7 +163,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: rllg %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -177,7 +177,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: rllg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/spill-01.ll b/test/CodeGen/SystemZ/spill-01.ll
index d48e9827f52..9de89d69b99 100644
--- a/test/CodeGen/SystemZ/spill-01.ll
+++ b/test/CodeGen/SystemZ/spill-01.ll
@@ -28,7 +28,7 @@ declare void @foo()
 
 ; This function shouldn't spill anything
 define void @f1(i32 *%ptr0) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg
 ; CHECK: aghi %r15, -160
 ; CHECK-NOT: %r15
@@ -67,7 +67,7 @@ define void @f1(i32 *%ptr0) {
 ; Test a case where at least one i32 load and at least one i32 store
 ; need spills.
 define void @f2(i32 *%ptr0) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
@@ -109,7 +109,7 @@ define void @f2(i32 *%ptr0) {
 ; Test a case where at least one i64 load and at least one i64 store
 ; need spills.
 define void @f3(i64 *%ptr0) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
@@ -154,7 +154,7 @@ define void @f3(i64 *%ptr0) {
 ; (and are at the time of writing), but it would really be better to use
 ; MVC for all 10.
 define void @f4(float *%ptr0) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
@@ -198,7 +198,7 @@ define void @f4(float *%ptr0) {
 
 ; Similarly for f64.
 define void @f5(double *%ptr0) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
@@ -242,7 +242,7 @@ define void @f5(double *%ptr0) {
 
 ; Repeat f2 with atomic accesses.  We shouldn't use MVC here.
 define void @f6(i32 *%ptr0) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %ptr1 = getelementptr i32 *%ptr0, i64 2
@@ -281,7 +281,7 @@ define void @f6(i32 *%ptr0) {
 
 ; ...likewise volatile accesses.
 define void @f7(i32 *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %ptr1 = getelementptr i32 *%ptr0, i64 2
@@ -320,7 +320,7 @@ define void @f7(i32 *%ptr0) {
 
 ; Check that LRL and STRL are not converted.
 define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %val0 = load i32 *@g0
@@ -352,7 +352,7 @@ define void @f8() {
 
 ; Likewise LGRL and STGRL.
 define void @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: mvc
 ; CHECK: br %r14
   %val0 = load i64 *@h0
@@ -388,7 +388,7 @@ define void @f9() {
 ; [FI0, FI1] -> [FI1, FI2], but applied it in the form FI0 -> FI1 -> FI2,
 ; so that both operands ended up being the same.
 define void @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lgrl [[REG:%r[0-9]+]], h9
 ; CHECK: stg [[REG]], [[VAL9:[0-9]+]](%r15)
 ; CHECK: brasl %r14, foo@PLT
@@ -459,7 +459,7 @@ skip:
 
 ; This used to generate a no-op MVC.  It is very sensitive to spill heuristics.
 define void @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: mvc [[OFFSET:[0-9]+]](8,%r15), [[OFFSET]](%r15)
 ; CHECK: br %r14
 entry:
diff --git a/test/CodeGen/SystemZ/tls-01.ll b/test/CodeGen/SystemZ/tls-01.ll
index 49037ad51c6..16bc8f6e500 100644
--- a/test/CodeGen/SystemZ/tls-01.ll
+++ b/test/CodeGen/SystemZ/tls-01.ll
@@ -11,7 +11,7 @@ define i32 *@foo() {
 ; CHECK-CP: .LCP{{.*}}:
 ; CHECK-CP: .quad x@NTPOFF
 ;
-; CHECK-MAIN: foo:
+; CHECK-MAIN-LABEL: foo:
 ; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
 ; CHECK-MAIN: sllg %r2, [[HIGH]], 32
 ; CHECK-MAIN: ear %r2, %a1
diff --git a/test/CodeGen/SystemZ/unaligned-01.ll b/test/CodeGen/SystemZ/unaligned-01.ll
index be237acd27f..621069d239d 100644
--- a/test/CodeGen/SystemZ/unaligned-01.ll
+++ b/test/CodeGen/SystemZ/unaligned-01.ll
@@ -21,7 +21,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check that unaligned 2-byte accesses are allowed.
 define i16 @f2(i16 *%src, i16 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: sth %r2, 0(%r3)
 ; CHECK: br %r14
@@ -32,7 +32,7 @@ define i16 @f2(i16 *%src, i16 *%dst) {
 
 ; Check that unaligned 4-byte accesses are allowed.
 define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: st %r2, 0(%r4)
@@ -46,7 +46,7 @@ define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) {
 
 ; Check that unaligned 8-byte accesses are allowed.
 define i64 @f4(i64 *%src1, i64 *%src2, i64 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: stg %r2, 0(%r4)
diff --git a/test/CodeGen/SystemZ/xor-01.ll b/test/CodeGen/SystemZ/xor-01.ll
index d0c69a0bac4..f9ba2eb65e7 100644
--- a/test/CodeGen/SystemZ/xor-01.ll
+++ b/test/CodeGen/SystemZ/xor-01.ll
@@ -6,7 +6,7 @@ declare i32 @foo()
 
 ; Check XR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xr %r2, %r3
 ; CHECK: br %r14
   %xor = xor i32 %a, %b
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the X range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned X range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: x %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -36,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use XY instead of X.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -47,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned XY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -59,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned XY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -82,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the XY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: xy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -94,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
@@ -106,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that X allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: x %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -119,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that XY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: xy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -132,7 +132,7 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
 
 ; Check that XORs of spilled values can use X rather than XR.
 define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: x %r2, 16{{[04]}}(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-02.ll b/test/CodeGen/SystemZ/xor-02.ll
index c2b52b9b8e2..7e28e231cfc 100644
--- a/test/CodeGen/SystemZ/xor-02.ll
+++ b/test/CodeGen/SystemZ/xor-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful XILF value.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xilf %r2, 1
 ; CHECK: br %r14
   %xor = xor i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the signed range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xilf %r2, 2147483647
 ; CHECK: br %r14
   %xor = xor i32 %a, 2147483647
@@ -23,7 +23,7 @@ define i32 @f2(i32 %a) {
 ; Check the low end of the signed range, which should be treated
 ; as a positive value.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf %r2, 2147483648
 ; CHECK: br %r14
   %xor = xor i32 %a, -2147483648
@@ -32,7 +32,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the high end of the XILF range.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
   %xor = xor i32 %a, 4294967295
diff --git a/test/CodeGen/SystemZ/xor-03.ll b/test/CodeGen/SystemZ/xor-03.ll
index f4f1b887ef4..2cd428ae7fc 100644
--- a/test/CodeGen/SystemZ/xor-03.ll
+++ b/test/CodeGen/SystemZ/xor-03.ll
@@ -6,7 +6,7 @@ declare i64 @foo()
 
 ; Check XGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xgr %r2, %r3
 ; CHECK: br %r14
   %xor = xor i64 %a, %b
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check XG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -25,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned XG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xg %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned XG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xg %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -60,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the XG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xg %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that XG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: xg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -97,7 +97,7 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
 
 ; Check that XORs of spilled values can use OG rather than OGR.
 define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: brasl %r14, foo@PLT
 ; CHECK: xg %r2, 160(%r15)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-04.ll b/test/CodeGen/SystemZ/xor-04.ll
index cc141d391a8..44f0a4cc39d 100644
--- a/test/CodeGen/SystemZ/xor-04.ll
+++ b/test/CodeGen/SystemZ/xor-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful XILF value.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xilf %r2, 1
 ; CHECK: br %r14
   %xor = xor i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the XILF range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
   %xor = xor i64 %a, 4294967295
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the lowest useful XIHF value, which is one up from the above.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xihf %r2, 1
 ; CHECK: br %r14
   %xor = xor i64 %a, 4294967296
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the next value up again, which needs a combination of XIHF and XILF.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xihf %r2, 1
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
@@ -41,7 +41,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the high end of the XIHF range.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xihf %r2, 4294967295
 ; CHECK: br %r14
   %xor = xor i64 %a, -4294967296
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the next value up, which again must use XIHF and XILF.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xihf %r2, 4294967295
 ; CHECK: xilf %r2, 1
 ; CHECK: br %r14
@@ -60,7 +60,7 @@ define i64 @f6(i64 %a) {
 
 ; Check full bitwise negation
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xihf %r2, 4294967295
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-05.ll b/test/CodeGen/SystemZ/xor-05.ll
index 9ef0d20ca52..fbd5660ad05 100644
--- a/test/CodeGen/SystemZ/xor-05.ll
+++ b/test/CodeGen/SystemZ/xor-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful constant, expressed as a signed integer.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a signed integer.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the lowest useful constant, expressed as an unsigned integer.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a unsigned integer.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check the high end of the XI range.
 define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xi 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
 
 ; Check the next byte up, which should use XIY instead of XI.
 define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xiy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
 
 ; Check the high end of the XIY range.
 define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xiy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: xi 0(%r2), 127
 ; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
 
 ; Check the high end of the negative XIY range.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: xiy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
 
 ; Check the low end of the XIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: xiy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -524289
 ; CHECK: xi 0(%r2), 127
 ; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
 
 ; Check that XI does not allow an index
 define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r2, %r3
 ; CHECK: xi 4095(%r2), 127
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
 
 ; Check that XIY does not allow an index
 define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agr %r2, %r3
 ; CHECK: xiy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-06.ll b/test/CodeGen/SystemZ/xor-06.ll
index 0ffff47c2b5..f39c0fec4e4 100644
--- a/test/CodeGen/SystemZ/xor-06.ll
+++ b/test/CodeGen/SystemZ/xor-06.ll
@@ -5,7 +5,7 @@
 
 ; Zero extension to 32 bits, negative constant.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
 
 ; Zero extension to 64 bits, negative constant.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
 
 ; Zero extension to 32 bits, positive constant.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
 
 ; Zero extension to 64 bits, positive constant.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
 
 ; Sign extension to 32 bits, negative constant.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
 
 ; Sign extension to 64 bits, negative constant.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
 
 ; Sign extension to 32 bits, positive constant.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
 
 ; Sign extension to 64 bits, positive constant.
 define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr