[SystemZ] set 'guessInstructionProperties = 0' and set flags as needed.

This has proven a healthy exercise, as many cases of incorrect instruction
flags were corrected in the process. As part of this, IntrWriteMem was added
to several SystemZ instrinsics.

Furthermore, a bug was exposed in TwoAddress with this change (as incorrect
hasSideEffects flags were removed and instructions could now be sunk), and
the test case for that bugfix (r319646) is included here as
test/CodeGen/SystemZ/twoaddr-sink.ll.

One temporary test regression (one extra copy) which will hopefully go away
in upcoming patches for similar cases:
test/CodeGen/SystemZ/vec-trunc-to-i1.ll

Review: Ulrich Weigand.
https://reviews.llvm.org/D40437

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319756 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 31 insertions, 17 deletions

diff --git a/test/CodeGen/SystemZ/backchain.ll b/test/CodeGen/SystemZ/backchain.ll
index b314bee4228..7c15d296ecd 100644
--- a/test/CodeGen/SystemZ/backchain.ll
+++ b/test/CodeGen/SystemZ/backchain.ll
@@ -44,8 +44,8 @@ define void @f4(i32 %len) "backchain" {
 ; CHECK: aghi %r15, -160
 ; CHECK: stg %r1, 0(%r15)
 ; CHECK: lgr %r11, %r15
-; CHECK: lg [[BC:%r[0-9]+]], 0(%r15)
-; CHECK: lgr [[NEWSP:%r[0-9]+]], %r15
+; CHECK-DAG: lg [[BC:%r[0-9]+]], 0(%r15)
+; CHECK-DAG: lgr [[NEWSP:%r[0-9]+]], %r15
 ; CHECK: lgr %r15, [[NEWSP]]
 ; CHECK: stg [[BC]], 0([[NEWSP]])
   %ign = alloca i8, i32 %len
diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll
index 6a146fab82c..9d86893a403 100644
--- a/test/CodeGen/SystemZ/risbg-01.ll
+++ b/test/CodeGen/SystemZ/risbg-01.ll
@@ -233,9 +233,11 @@ define i64 @f20(i64 %foo) {
 ; Now try an arithmetic right shift in which the sign bits aren't needed.
 ; Introduce a second use of %shr so that the ashr doesn't decompose to
 ; an lshr.
+; NOTE: the extra move to %r2 should not be needed (temporary FAIL)
 define i32 @f21(i32 %foo, i32 *%dest) {
 ; CHECK-LABEL: f21:
-; CHECK: risbg %r2, %r2, 60, 190, 36
+; CHECK: risbg %r0, %r2, 60, 190, 36
+; CHECK: lr %r2, %r0
 ; CHECK: br %r14
   %shr = ashr i32 %foo, 28
   store i32 %shr, i32 *%dest
diff --git a/test/CodeGen/SystemZ/twoaddr-sink.ll b/test/CodeGen/SystemZ/twoaddr-sink.ll
new file mode 100644
index 00000000000..ca00e687a5d
--- /dev/null
+++ b/test/CodeGen/SystemZ/twoaddr-sink.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-integrated-as
+;
+; Check that TwoAddressInstructionPass does not crash after sinking (and
+; revisiting) an instruction that was lowered by TII->convertToThreeAddress()
+; which contains a %noreg operand.
+
+define i32 @f23(i32 %old) {
+  %and1 = and i32 %old, 14
+  %and2 = and i32 %old, 254
+  %res1 = call i32 asm "stepa $1, $2, $3", "=h,r,r,0"(i32 %old, i32 %and1, i32 %and2)
+  %and3 = and i32 %res1, 127
+  %and4 = and i32 %res1, 128
+  %res2 = call i32 asm "stepb $1, $2, $3", "=r,h,h,0"(i32 %res1, i32 %and3, i32 %and4)
+  ret i32 %res2
+}
diff --git a/test/CodeGen/SystemZ/vec-trunc-to-i1.ll b/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
index 73d4c47a840..2901cf0f29a 100644
--- a/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
+++ b/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
@@ -1,26 +1,23 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 ;
 ; Check that a widening truncate to a vector of i1 elements can be handled.
 
-
+; NOTE: REG2 is actually not needed (tempororary FAIL)
 define void @pr32275(<4 x i8> %B15) {
 ; CHECK-LABEL: pr32275:
 ; CHECK:       # %bb.0: # %BB
-; CHECK-NEXT:    vrepif %v0, 1
-; CHECK-NEXT:  .LBB0_1: # %CF34
-; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vlgvb %r0, %v24, 3
+; CHECK-NEXT:    vrepif [[REG0:%v[0-9]]], 1
+; CHECK:         vlgvb %r0, %v24, 3
 ; CHECK-NEXT:    vlgvb %r1, %v24, 1
-; CHECK-NEXT:    vlvgp %v1, %r1, %r0
+; CHECK-NEXT:    vlvgp [[REG1:%v[0-9]]], %r1, %r0
 ; CHECK-NEXT:    vlgvb %r0, %v24, 0
-; CHECK-NEXT:    vlvgf %v1, %r0, 0
-; CHECK-NEXT:    vlgvb %r0, %v24, 2
-; CHECK-NEXT:    vlvgf %v1, %r0, 2
-; CHECK-NEXT:    vn %v1, %v1, %v0
-; CHECK-NEXT:    vlgvf %r0, %v1, 3
-; CHECK-NEXT:    tmll %r0, 1
+; CHECK-DAG:     vlr [[REG2:%v[0-9]]], [[REG1]]
+; CHECK-DAG:     vlvgf [[REG2]], %r0, 0
+; CHECK-DAG:     vlgvb [[REG3:%r[0-9]]], %v24, 2
+; CHECK-NEXT:    vlvgf [[REG2]], [[REG3]], 2
+; CHECK-NEXT:    vn [[REG2]], [[REG2]], [[REG0]]
+; CHECK-NEXT:    vlgvf [[REG4:%r[0-9]]], [[REG2]], 3
+; CHECK-NEXT:    tmll [[REG4]], 1
 ; CHECK-NEXT:    jne .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %CF36
 ; CHECK-NEXT:    br %r14