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authorJonas Paulsson <paulsson@linux.vnet.ibm.com>2017-03-21 10:24:14 +0000
committerJonas Paulsson <paulsson@linux.vnet.ibm.com>2017-03-21 10:24:14 +0000
commit92b0e9b3cb849ab348873242cdb74e8b72b2c74c (patch)
treedbeff2bcf9b4a72b71ac3104dcb06213504f009d /test/CodeGen/SystemZ/vec-trunc-to-i1.ll
parent8b2132abbea2f562fcc51468318d55c736f9cad0 (diff)
[DAGTypeLegalizer] Handle widening truncate to vector of i1.
Previously, PromoteIntRes_TRUNCATE() did not handle the case where the operand needs widening, which resulted in llvm_unreachable(). This patch adds the needed handling, along with a test case. Review: Eli Friedman, Simon Pilgrim. https://reviews.llvm.org/D31077 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298357 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/vec-trunc-to-i1.ll')
-rw-r--r--test/CodeGen/SystemZ/vec-trunc-to-i1.ll37
1 files changed, 37 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/vec-trunc-to-i1.ll b/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
new file mode 100644
index 00000000000..705fe3dbac9
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+;
+; Check that a widening truncate to a vector of i1 elements can be handled.
+
+
+define void @pr32275(<4 x i8> %B15) {
+; CHECK-LABEL: pr32275:
+; CHECK: # BB#0: # %BB
+; CHECK-NEXT: vrepif %v0, 1
+; CHECK-NEXT: .LBB0_1: # %CF34
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: vlgvb %r0, %v24, 3
+; CHECK-NEXT: vlgvb %r1, %v24, 1
+; CHECK-NEXT: vlvgp %v1, %r1, %r0
+; CHECK-NEXT: vlgvb %r0, %v24, 0
+; CHECK-NEXT: vlvgf %v1, %r0, 0
+; CHECK-NEXT: vlgvb %r0, %v24, 2
+; CHECK-NEXT: vlvgf %v1, %r0, 2
+; CHECK-NEXT: vn %v1, %v1, %v0
+; CHECK-NEXT: vlgvf %r0, %v1, 3
+; CHECK-NEXT: tmll %r0, 1
+; CHECK-NEXT: jne .LBB0_1
+; CHECK-NEXT: # BB#2: # %CF36
+; CHECK-NEXT: br %r14
+BB:
+ br label %CF34
+
+CF34:
+ %Tr24 = trunc <4 x i8> %B15 to <4 x i1>
+ %E28 = extractelement <4 x i1> %Tr24, i32 3
+ br i1 %E28, label %CF34, label %CF36
+
+CF36:
+ ret void
+}