[SystemZ] Handle sub-128 vectors

The ABI allows sub-128 vectors to be passed and returned in registers,
with the vector occupying the upper part of a register.  We therefore
want to legalize those types by widening the vector rather than promoting
the elements.

The patch includes some simple tests for sub-128 vectors and also tests
that we can recognize various pack sequences, some of which use sub-128
vectors as temporary results.  One of these forms is based on the pack
sequences generated by llvmpipe when no intrinsics are used.

Signed unpacks are recognized as BUILD_VECTORs whose elements are
individually sign-extended.  Unsigned unpacks can have the equivalent
form with zero extension, but they also occur as shuffles in which some
elements are zero.

Based on a patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236525 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 2 insertions, 2 deletions

diff --git a/test/CodeGen/SystemZ/vec-move-13.ll b/test/CodeGen/SystemZ/vec-move-13.ll
index 4ad8e3f5210..165c3498702 100644
--- a/test/CodeGen/SystemZ/vec-move-13.ll
+++ b/test/CodeGen/SystemZ/vec-move-13.ll
@@ -49,8 +49,8 @@ define <2 x i64> @f4(i64 %val) {
 ; Test v4f32 insertion into 0.
 define <4 x float> @f5(float %val) {
 ; CHECK-LABEL: f5:
-; CHECK: vgbm [[ZERO:%v[0-9]+]], 0
-; CHECK: vmrhf [[REG:%v[0-9]+]], [[ZERO]], %v0
+; CHECK-DAG: vuplhf [[REG:%v[0-9]+]], %v0
+; CHECK-DAG: vgbm [[ZERO:%v[0-9]+]], 0
 ; CHECK: vmrhg %v24, [[ZERO]], [[REG]]
 ; CHECK: br %r14
   %ret = insertelement <4 x float> zeroinitializer, float %val, i32 3