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authorSanjay Patel <spatel@rotateright.com>2016-10-19 16:58:59 +0000
committerSanjay Patel <spatel@rotateright.com>2016-10-19 16:58:59 +0000
commit85745f9561b7f54e75d40b8e35245c4b9e6ecd65 (patch)
tree17f325342764c9f3ce710f189b2c09076b4299dd /test/CodeGen/SystemZ/risbg-01.ll
parent8b3f7e86b154f57cfd2209d9b0c66da36070df2e (diff)
[DAG] optimize negation of bool
Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284611 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/risbg-01.ll')
-rw-r--r--test/CodeGen/SystemZ/risbg-01.ll6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll
index 1c4315343de..6a146fab82c 100644
--- a/test/CodeGen/SystemZ/risbg-01.ll
+++ b/test/CodeGen/SystemZ/risbg-01.ll
@@ -472,9 +472,9 @@ define i64 @f41(i32 %a) {
; when testing whether the shifted-in bits of the shift right were significant.
define i64 @f42(i1 %x) {
; CHECK-LABEL: f42:
-; CHECK: sll %r2, 31
-; CHECK: sra %r2, 31
-; CHECK: llgcr %r2, %r2
+; CHECK: nilf %r2, 1
+; CHECK: lcr %r0, %r2
+; CHECK: llgcr %r2, %r0
; CHECK: br %r14
%ext = sext i1 %x to i8
%ext2 = zext i8 %ext to i64