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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-05-06 16:17:29 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-05-06 16:17:29 +0000 |
commit | b503b49b5105b6aad7d2a015468b84b0f64dfe8e (patch) | |
tree | a60966043fae51838cb2faa08531a7ed078e4fb6 /test/CodeGen/SystemZ/int-conv-07.ll | |
parent | 1d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07 (diff) |
[SystemZ] Add CodeGen test cases
This adds all CodeGen tests for the SystemZ target.
This version of the patch incorporates feedback from a review by
Sean Silva. Thanks to all reviewers!
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/int-conv-07.ll')
-rw-r--r-- | test/CodeGen/SystemZ/int-conv-07.ll | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/int-conv-07.ll b/test/CodeGen/SystemZ/int-conv-07.ll new file mode 100644 index 00000000000..041caa244c8 --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-07.ll @@ -0,0 +1,105 @@ +; Test sign extensions from a halfword to an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: lghr %r2, %r2 +; CHECk: br %r14 + %half = trunc i64 %a to i16 + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; ...and again with an i64. +define i64 @f2(i32 %a) { +; CHECK: f2: +; CHECK: lghr %r2, %r2 +; CHECk: br %r14 + %half = trunc i32 %a to i16 + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check LGH with no displacement. +define i64 @f3(i16 *%src) { +; CHECK: f3: +; CHECK: lgh %r2, 0(%r2) +; CHECK: br %r14 + %half = load i16 *%src + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the high end of the LGH range. +define i64 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: lgh %r2, 524286(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: lgh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the high end of the negative LGH range. +define i64 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: lgh %r2, -2(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the low end of the LGH range. +define i64 @f7(i16 *%src) { +; CHECK: f7: +; CHECK: lgh %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f8(i16 *%src) { +; CHECK: f8: +; CHECK: agfi %r2, -524290 +; CHECK: lgh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check that LGH allows an index. +define i64 @f9(i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: lgh %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} |