diff options
author | James Y Knight <jyknight@google.com> | 2017-05-12 15:59:10 +0000 |
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committer | James Y Knight <jyknight@google.com> | 2017-05-12 15:59:10 +0000 |
commit | c5d0c88a98ffa1050819b274c8a64d31d1882c00 (patch) | |
tree | 038bef8a1b763b371304c60a0553ad131e67036e /test/CodeGen/SPARC | |
parent | 0ee4a484f75647994d16fc2afe6ce88be047ae20 (diff) |
[SPARC] Support 'f' and 'e' inline asm constraints.
Based on patch by Patrick Boettcher and Chris Dewhurst.
Differential Revision: https://reviews.llvm.org/D29116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302911 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SPARC')
-rw-r--r-- | test/CodeGen/SPARC/inlineasm-v9.ll | 30 | ||||
-rw-r--r-- | test/CodeGen/SPARC/inlineasm.ll | 18 |
2 files changed, 48 insertions, 0 deletions
diff --git a/test/CodeGen/SPARC/inlineasm-v9.ll b/test/CodeGen/SPARC/inlineasm-v9.ll new file mode 100644 index 00000000000..9c5424c4622 --- /dev/null +++ b/test/CodeGen/SPARC/inlineasm-v9.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=sparcv9 <%s | FileCheck %s + +;; Ensures that inline-asm accepts and uses 'f' and 'e' register constraints. +; CHECK-LABEL: faddd: +; CHECK: faddd %f0, %f2, %f0 +define double @faddd(double, double) local_unnamed_addr #2 { +entry: + %2 = tail call double asm sideeffect "faddd $1, $2, $0;", "=f,f,e"(double %0, double %1) #7 + ret double %2 +} + +; CHECK-LABEL: faddq: +; CHECK: faddq %f0, %f4, %f0 +define fp128 @faddq(fp128, fp128) local_unnamed_addr #2 { +entry: + %2 = tail call fp128 asm sideeffect "faddq $1, $2, $0;", "=f,f,e"(fp128 %0, fp128 %1) #7 + ret fp128 %2 +} + +;; Ensure that 'e' can indeed go in the high area, and 'f' cannot. +; CHECK-LABEL: faddd_high: +; CHECK: fmovd %f2, %f32 +; CHECK: fmovd %f0, %f2 +; CHECK: faddd %f2, %f32, %f2 +define double @faddd_high(double, double) local_unnamed_addr #2 { +entry: + %2 = tail call double asm sideeffect "faddd $1, $2, $0;", "=f,f,e,~{d0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7}"(double %0, double %1) #7 + ret double %2 +} + diff --git a/test/CodeGen/SPARC/inlineasm.ll b/test/CodeGen/SPARC/inlineasm.ll index af631f0d29f..35a62706c1a 100644 --- a/test/CodeGen/SPARC/inlineasm.ll +++ b/test/CodeGen/SPARC/inlineasm.ll @@ -94,3 +94,21 @@ entry: %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5); ret i64 %0 } + + +;; Ensures that inline-asm accepts and uses 'f' and 'e' register constraints. +; CHECK-LABEL: fadds: +; CHECK: fadds %f0, %f1, %f0 +define float @fadds(float, float) local_unnamed_addr #2 { +entry: + %2 = tail call float asm sideeffect "fadds $1, $2, $0;", "=f,f,e"(float %0, float %1) #7 + ret float %2 +} + +; CHECK-LABEL: faddd: +; CHECK: faddd %f0, %f2, %f0 +define double @faddd(double, double) local_unnamed_addr #2 { +entry: + %2 = tail call double asm sideeffect "faddd $1, $2, $0;", "=f,f,e"(double %0, double %1) #7 + ret double %2 +} |