[RISCV] Enable emission of alias instructions by default

This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.

Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context)

Differential Revision: https://reviews.llvm.org/D41225

Patch by Mario Werner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320797 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 12 deletions

diff --git a/test/CodeGen/RISCV/i32-icmp.ll b/test/CodeGen/RISCV/i32-icmp.ll
index 068ed2078ec..112d31b1242 100644
--- a/test/CodeGen/RISCV/i32-icmp.ll
+++ b/test/CodeGen/RISCV/i32-icmp.ll
@@ -13,11 +13,11 @@ define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s0, 8(sp)
 ; RV32I-NEXT:    addi s0, sp, 16
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    sltiu a0, a0, 1
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp eq i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -31,11 +31,11 @@ define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    sw s0, 8(sp)
 ; RV32I-NEXT:    addi s0, sp, 16
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    sltu a0, zero, a0
+; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp ne i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -52,7 +52,7 @@ define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp ugt i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -70,7 +70,7 @@ define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp uge i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -87,7 +87,7 @@ define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp ult i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -105,7 +105,7 @@ define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp ule i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -122,7 +122,7 @@ define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp sgt i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -140,7 +140,7 @@ define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp sge i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -157,7 +157,7 @@ define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp slt i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -175,7 +175,7 @@ define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    jalr zero, ra, 0
+; RV32I-NEXT:    ret
   %1 = icmp sle i32 %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2