diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-11 12:34:11 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-11 12:34:11 +0000 |
| commit | dcfcbe7bdc35f4d620d1270f7789e4489b8b19af (patch) | |
| tree | 2d59624e2bb643bf74e148db685ccbda730567ac /test/CodeGen/RISCV/calls.ll | |
| parent | 1b5e053f7e8e6c41e6eb2787f2a49ffb59f1d541 (diff) | |
[RISCV] Implement prolog and epilog insertion
As frame pointer elimination isn't implemented until a later patch and we make
extensive use of update_llc_test_checks.py, this changes touches a lot of the
RISC-V tests.
Differential Revision: https://reviews.llvm.org/D39849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320357 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/RISCV/calls.ll')
| -rw-r--r-- | test/CodeGen/RISCV/calls.ll | 38 |
1 files changed, 36 insertions, 2 deletions
diff --git a/test/CodeGen/RISCV/calls.ll b/test/CodeGen/RISCV/calls.ll index cc43e257498..3fba88dc45d 100644 --- a/test/CodeGen/RISCV/calls.ll +++ b/test/CodeGen/RISCV/calls.ll @@ -7,11 +7,16 @@ declare i32 @external_function(i32) define i32 @test_call_external(i32 %a) nounwind { ; RV32I-LABEL: test_call_external: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: lui a1, %hi(external_function) ; RV32I-NEXT: addi a1, a1, %lo(external_function) ; RV32I-NEXT: jalr ra, a1, 0 +; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 %1 = call i32 @external_function(i32 %a) ret i32 %1 @@ -20,7 +25,14 @@ define i32 @test_call_external(i32 %a) nounwind { define i32 @defined_function(i32 %a) nounwind { ; RV32I-LABEL: defined_function: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi a0, a0, 1 +; RV32I-NEXT: lw s0, 8(sp) +; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 %1 = add i32 %a, 1 ret i32 %1 @@ -29,11 +41,16 @@ define i32 @defined_function(i32 %a) nounwind { define i32 @test_call_defined(i32 %a) nounwind { ; RV32I-LABEL: test_call_defined: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: lui a1, %hi(defined_function) ; RV32I-NEXT: addi a1, a1, %lo(defined_function) ; RV32I-NEXT: jalr ra, a1, 0 +; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 %1 = call i32 @defined_function(i32 %a) nounwind ret i32 %1 @@ -42,11 +59,16 @@ define i32 @test_call_defined(i32 %a) nounwind { define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind { ; RV32I-LABEL: test_call_indirect: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi a2, a0, 0 ; RV32I-NEXT: addi a0, a1, 0 ; RV32I-NEXT: jalr ra, a2, 0 +; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 %1 = call i32 %a(i32 %b) ret i32 %1 @@ -58,7 +80,14 @@ define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind { define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: fastcc_function: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: lw s0, 8(sp) +; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 %1 = add i32 %a, %b ret i32 %1 @@ -67,16 +96,21 @@ define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind { define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: test_call_fastcc: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: sw s1, 8(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: sw s1, 4(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi s1, a0, 0 ; RV32I-NEXT: lui a0, %hi(fastcc_function) ; RV32I-NEXT: addi a2, a0, %lo(fastcc_function) ; RV32I-NEXT: addi a0, s1, 0 ; RV32I-NEXT: jalr ra, a2, 0 ; RV32I-NEXT: addi a0, s1, 0 -; RV32I-NEXT: lw s1, 8(sp) +; RV32I-NEXT: lw s1, 4(sp) +; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 %1 = call fastcc i32 @fastcc_function(i32 %a, i32 %b) ret i32 %a |