[CodeGen] Unify MBB reference format in both MIR and debug output

As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665 91177308-0d34-0410-b5e6-96231b3b80d8
author: Francis Visoiu Mistrih <francisvm@yahoo.com> 2017-12-04 17:18:51 +0000
committer: Francis Visoiu Mistrih <francisvm@yahoo.com> 2017-12-04 17:18:51 +0000
commit: ca0df55065b11f2310f55c731b2f990d09ae1c32 (patch)
tree: fff52bf80df56346069e50ec52b17a4e36907e87 /test/CodeGen/PowerPC
parent: 93356784e0e357e3f1f74d565480cc9c25ea4bc9 (diff)
91 files changed, 1778 insertions, 1778 deletions
diff --git a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
index 56f4a4173ef..5b8b8147cce 100644
--- a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
+++ b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
@@ -6,7 +6,7 @@
 
 define i32 @test(i32 %i) {
 ; CHECK-LABEL: test:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 4, 2, .LC0@toc@ha
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    addis 5, 2, .LC1@toc@ha
diff --git a/test/CodeGen/PowerPC/addegluecrash.ll b/test/CodeGen/PowerPC/addegluecrash.ll
index f17b6dce9a9..642960f8490 100644
--- a/test/CodeGen/PowerPC/addegluecrash.ll
+++ b/test/CodeGen/PowerPC/addegluecrash.ll
@@ -5,7 +5,7 @@ target triple = "powerpc64le-unknown-linux-gnu"
 
 define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) {
 ; CHECK-LABEL: bn_mul_comba8:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ld 6, 0(4)
 ; CHECK-NEXT:    ld 7, 0(5)
 ; CHECK-NEXT:    mulhdu 8, 7, 6
diff --git a/test/CodeGen/PowerPC/andc.ll b/test/CodeGen/PowerPC/andc.ll
index df47bfc1e38..9bfbda2bbd7 100644
--- a/test/CodeGen/PowerPC/andc.ll
+++ b/test/CodeGen/PowerPC/andc.ll
@@ -3,7 +3,7 @@
 
 define i1 @and_cmp1(i32 %x, i32 %y) {
 ; CHECK-LABEL: and_cmp1:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andc 3, 4, 3
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
@@ -15,7 +15,7 @@ define i1 @and_cmp1(i32 %x, i32 %y) {
 
 define i1 @and_cmp_const(i32 %x) {
 ; CHECK-LABEL: and_cmp_const:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 43
 ; CHECK-NEXT:    andc 3, 4, 3
 ; CHECK-NEXT:    cntlzw 3, 3
@@ -28,7 +28,7 @@ define i1 @and_cmp_const(i32 %x) {
 
 define i1 @foo(i32 %i) {
 ; CHECK-LABEL: foo:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, 4660
 ; CHECK-NEXT:    ori 4, 4, 22136
 ; CHECK-NEXT:    andc 3, 4, 3
@@ -42,7 +42,7 @@ define i1 @foo(i32 %i) {
 
 define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) {
 ; CHECK-LABEL: hidden_not_v4i32:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, 6
 ; CHECK-NEXT:    xxlandc 34, 35, 34
 ; CHECK-NEXT:    blr
diff --git a/test/CodeGen/PowerPC/atomics-constant.ll b/test/CodeGen/PowerPC/atomics-constant.ll
index 77825c608a3..559cd9eb656 100644
--- a/test/CodeGen/PowerPC/atomics-constant.ll
+++ b/test/CodeGen/PowerPC/atomics-constant.ll
@@ -7,7 +7,7 @@ target triple = "powerpc64le-unknown-linux-gnu"
 
 define i64 @foo() {
 ; CHECK-LABEL: foo:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
diff --git a/test/CodeGen/PowerPC/atomics-regression.ll b/test/CodeGen/PowerPC/atomics-regression.ll
index c8fb1e74e73..7079f6dd52e 100644
--- a/test/CodeGen/PowerPC/atomics-regression.ll
+++ b/test/CodeGen/PowerPC/atomics-regression.ll
@@ -3,7 +3,7 @@
 
 define i8 @test0(i8* %ptr) {
 ; PPC64LE-LABEL: test0:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lbz 3, 0(3)
 ; PPC64LE-NEXT:    blr
   %val = load atomic i8, i8* %ptr unordered, align 1
@@ -12,7 +12,7 @@ define i8 @test0(i8* %ptr) {
 
 define i8 @test1(i8* %ptr) {
 ; PPC64LE-LABEL: test1:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lbz 3, 0(3)
 ; PPC64LE-NEXT:    blr
   %val = load atomic i8, i8* %ptr monotonic, align 1
@@ -21,7 +21,7 @@ define i8 @test1(i8* %ptr) {
 
 define i8 @test2(i8* %ptr) {
 ; PPC64LE-LABEL: test2:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lbz 3, 0(3)
 ; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
@@ -33,7 +33,7 @@ define i8 @test2(i8* %ptr) {
 
 define i8 @test3(i8* %ptr) {
 ; PPC64LE-LABEL: test3:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    lbz 3, 0(3)
@@ -47,7 +47,7 @@ define i8 @test3(i8* %ptr) {
 
 define i16 @test4(i16* %ptr) {
 ; PPC64LE-LABEL: test4:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lhz 3, 0(3)
 ; PPC64LE-NEXT:    blr
   %val = load atomic i16, i16* %ptr unordered, align 2
@@ -56,7 +56,7 @@ define i16 @test4(i16* %ptr) {
 
 define i16 @test5(i16* %ptr) {
 ; PPC64LE-LABEL: test5:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lhz 3, 0(3)
 ; PPC64LE-NEXT:    blr
   %val = load atomic i16, i16* %ptr monotonic, align 2
@@ -65,7 +65,7 @@ define i16 @test5(i16* %ptr) {
 
 define i16 @test6(i16* %ptr) {
 ; PPC64LE-LABEL: test6:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lhz 3, 0(3)
 ; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
@@ -77,7 +77,7 @@ define i16 @test6(i16* %ptr) {
 
 define i16 @test7(i16* %ptr) {
 ; PPC64LE-LABEL: test7:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    lhz 3, 0(3)
@@ -91,7 +91,7 @@ define i16 @test7(i16* %ptr) {
 
 define i32 @test8(i32* %ptr) {
 ; PPC64LE-LABEL: test8:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwz 3, 0(3)
 ; PPC64LE-NEXT:    blr
   %val = load atomic i32, i32* %ptr unordered, align 4
@@ -100,7 +100,7 @@ define i32 @test8(i32* %ptr) {
 
 define i32 @test9(i32* %ptr) {
 ; PPC64LE-LABEL: test9:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwz 3, 0(3)
 ; PPC64LE-NEXT:    blr
   %val = load atomic i32, i32* %ptr monotonic, align 4
@@ -109,7 +109,7 @@ define i32 @test9(i32* %ptr) {
 
 define i32 @test10(i32* %ptr) {
 ; PPC64LE-LABEL: test10:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwz 3, 0(3)
 ; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
@@ -121,7 +121,7 @@ define i32 @test10(i32* %ptr) {
 
 define i32 @test11(i32* %ptr) {
 ; PPC64LE-LABEL: test11:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    lwz 3, 0(3)
@@ -135,7 +135,7 @@ define i32 @test11(i32* %ptr) {
 
 define i64 @test12(i64* %ptr) {
 ; PPC64LE-LABEL: test12:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    ld 3, 0(3)
 ; PPC64LE-NEXT:    blr
   %val = load atomic i64, i64* %ptr unordered, align 8
@@ -144,7 +144,7 @@ define i64 @test12(i64* %ptr) {
 
 define i64 @test13(i64* %ptr) {
 ; PPC64LE-LABEL: test13:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    ld 3, 0(3)
 ; PPC64LE-NEXT:    blr
   %val = load atomic i64, i64* %ptr monotonic, align 8
@@ -153,7 +153,7 @@ define i64 @test13(i64* %ptr) {
 
 define i64 @test14(i64* %ptr) {
 ; PPC64LE-LABEL: test14:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    ld 3, 0(3)
 ; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
@@ -165,7 +165,7 @@ define i64 @test14(i64* %ptr) {
 
 define i64 @test15(i64* %ptr) {
 ; PPC64LE-LABEL: test15:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    ld 3, 0(3)
@@ -179,7 +179,7 @@ define i64 @test15(i64* %ptr) {
 
 define void @test16(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test16:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    stb 4, 0(3)
 ; PPC64LE-NEXT:    blr
   store atomic i8 %val, i8* %ptr unordered, align 1
@@ -188,7 +188,7 @@ define void @test16(i8* %ptr, i8 %val) {
 
 define void @test17(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test17:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    stb 4, 0(3)
 ; PPC64LE-NEXT:    blr
   store atomic i8 %val, i8* %ptr monotonic, align 1
@@ -197,7 +197,7 @@ define void @test17(i8* %ptr, i8 %val) {
 
 define void @test18(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test18:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    stb 4, 0(3)
 ; PPC64LE-NEXT:    blr
@@ -207,7 +207,7 @@ define void @test18(i8* %ptr, i8 %val) {
 
 define void @test19(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test19:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    stb 4, 0(3)
 ; PPC64LE-NEXT:    blr
@@ -217,7 +217,7 @@ define void @test19(i8* %ptr, i8 %val) {
 
 define void @test20(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test20:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sth 4, 0(3)
 ; PPC64LE-NEXT:    blr
   store atomic i16 %val, i16* %ptr unordered, align 2
@@ -226,7 +226,7 @@ define void @test20(i16* %ptr, i16 %val) {
 
 define void @test21(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test21:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sth 4, 0(3)
 ; PPC64LE-NEXT:    blr
   store atomic i16 %val, i16* %ptr monotonic, align 2
@@ -235,7 +235,7 @@ define void @test21(i16* %ptr, i16 %val) {
 
 define void @test22(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test22:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    sth 4, 0(3)
 ; PPC64LE-NEXT:    blr
@@ -245,7 +245,7 @@ define void @test22(i16* %ptr, i16 %val) {
 
 define void @test23(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test23:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    sth 4, 0(3)
 ; PPC64LE-NEXT:    blr
@@ -255,7 +255,7 @@ define void @test23(i16* %ptr, i16 %val) {
 
 define void @test24(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test24:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    stw 4, 0(3)
 ; PPC64LE-NEXT:    blr
   store atomic i32 %val, i32* %ptr unordered, align 4
@@ -264,7 +264,7 @@ define void @test24(i32* %ptr, i32 %val) {
 
 define void @test25(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test25:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    stw 4, 0(3)
 ; PPC64LE-NEXT:    blr
   store atomic i32 %val, i32* %ptr monotonic, align 4
@@ -273,7 +273,7 @@ define void @test25(i32* %ptr, i32 %val) {
 
 define void @test26(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test26:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    stw 4, 0(3)
 ; PPC64LE-NEXT:    blr
@@ -283,7 +283,7 @@ define void @test26(i32* %ptr, i32 %val) {
 
 define void @test27(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test27:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    stw 4, 0(3)
 ; PPC64LE-NEXT:    blr
@@ -293,7 +293,7 @@ define void @test27(i32* %ptr, i32 %val) {
 
 define void @test28(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test28:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    std 4, 0(3)
 ; PPC64LE-NEXT:    blr
   store atomic i64 %val, i64* %ptr unordered, align 8
@@ -302,7 +302,7 @@ define void @test28(i64* %ptr, i64 %val) {
 
 define void @test29(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test29:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    std 4, 0(3)
 ; PPC64LE-NEXT:    blr
   store atomic i64 %val, i64* %ptr monotonic, align 8
@@ -311,7 +311,7 @@ define void @test29(i64* %ptr, i64 %val) {
 
 define void @test30(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test30:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    std 4, 0(3)
 ; PPC64LE-NEXT:    blr
@@ -321,7 +321,7 @@ define void @test30(i64* %ptr, i64 %val) {
 
 define void @test31(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test31:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    std 4, 0(3)
 ; PPC64LE-NEXT:    blr
@@ -331,7 +331,7 @@ define void @test31(i64* %ptr, i64 %val) {
 
 define void @test32() {
 ; PPC64LE-LABEL: test32:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   fence acquire
@@ -340,7 +340,7 @@ define void @test32() {
 
 define void @test33() {
 ; PPC64LE-LABEL: test33:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   fence release
@@ -349,7 +349,7 @@ define void @test33() {
 
 define void @test34() {
 ; PPC64LE-LABEL: test34:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   fence acq_rel
@@ -358,7 +358,7 @@ define void @test34() {
 
 define void @test35() {
 ; PPC64LE-LABEL: test35:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    blr
   fence seq_cst
@@ -367,7 +367,7 @@ define void @test35() {
 
 define void @test36() {
 ; PPC64LE-LABEL: test36:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   fence syncscope("singlethread") acquire
@@ -376,7 +376,7 @@ define void @test36() {
 
 define void @test37() {
 ; PPC64LE-LABEL: test37:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   fence syncscope("singlethread") release
@@ -385,7 +385,7 @@ define void @test37() {
 
 define void @test38() {
 ; PPC64LE-LABEL: test38:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   fence syncscope("singlethread") acq_rel
@@ -394,7 +394,7 @@ define void @test38() {
 
 define void @test39() {
 ; PPC64LE-LABEL: test39:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    blr
   fence syncscope("singlethread") seq_cst
@@ -403,7 +403,7 @@ define void @test39() {
 
 define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test40:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    b .LBB40_2
 ; PPC64LE-NEXT:    .p2align 5
 ; PPC64LE-NEXT:  .LBB40_1:
@@ -413,7 +413,7 @@ define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB40_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
@@ -422,15 +422,15 @@ define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test41:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB41_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB41_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB41_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB41_4:
@@ -443,15 +443,15 @@ define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test42:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB42_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB42_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB42_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB42_4:
@@ -464,7 +464,7 @@ define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test43:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB43_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -475,7 +475,7 @@ define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB43_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
@@ -484,7 +484,7 @@ define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test44:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB44_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -495,7 +495,7 @@ define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB44_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
@@ -504,16 +504,16 @@ define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test45:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB45_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB45_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB45_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB45_4:
@@ -526,16 +526,16 @@ define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test46:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB46_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB46_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB46_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB46_4:
@@ -548,16 +548,16 @@ define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test47:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB47_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB47_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB47_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB47_4:
@@ -570,16 +570,16 @@ define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test48:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB48_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB48_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB48_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB48_4:
@@ -592,16 +592,16 @@ define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test49:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB49_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB49_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB49_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB49_4:
@@ -614,7 +614,7 @@ define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test50:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    b .LBB50_2
 ; PPC64LE-NEXT:    .p2align 5
 ; PPC64LE-NEXT:  .LBB50_1:
@@ -624,7 +624,7 @@ define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB50_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
@@ -633,15 +633,15 @@ define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test51:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB51_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB51_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB51_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB51_4:
@@ -654,15 +654,15 @@ define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test52:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB52_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB52_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB52_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB52_4:
@@ -675,7 +675,7 @@ define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test53:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB53_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -686,7 +686,7 @@ define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB53_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
@@ -695,7 +695,7 @@ define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test54:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB54_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -706,7 +706,7 @@ define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB54_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
@@ -715,16 +715,16 @@ define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test55:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB55_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB55_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB55_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB55_4:
@@ -737,16 +737,16 @@ define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test56:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB56_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB56_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB56_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB56_4:
@@ -759,16 +759,16 @@ define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test57:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB57_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB57_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB57_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB57_4:
@@ -781,16 +781,16 @@ define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test58:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB58_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB58_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB58_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB58_4:
@@ -803,16 +803,16 @@ define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test59:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB59_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB59_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB59_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB59_4:
@@ -825,7 +825,7 @@ define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test60(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test60:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    b .LBB60_2
 ; PPC64LE-NEXT:    .p2align 5
 ; PPC64LE-NEXT:  .LBB60_1:
@@ -835,7 +835,7 @@ define void @test60(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB60_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
@@ -844,15 +844,15 @@ define void @test60(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test61(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test61:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB61_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB61_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB61_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB61_4:
@@ -865,15 +865,15 @@ define void @test61(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test62(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test62:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB62_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB62_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB62_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB62_4:
@@ -886,7 +886,7 @@ define void @test62(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test63(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test63:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB63_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -897,7 +897,7 @@ define void @test63(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB63_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
@@ -906,7 +906,7 @@ define void @test63(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test64(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test64:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB64_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -917,7 +917,7 @@ define void @test64(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB64_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
@@ -926,16 +926,16 @@ define void @test64(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test65(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test65:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB65_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB65_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB65_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB65_4:
@@ -948,16 +948,16 @@ define void @test65(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test66(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test66:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB66_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB66_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB66_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB66_4:
@@ -970,16 +970,16 @@ define void @test66(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test67(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test67:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB67_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB67_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB67_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB67_4:
@@ -992,16 +992,16 @@ define void @test67(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test68(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test68:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB68_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB68_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB68_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB68_4:
@@ -1014,16 +1014,16 @@ define void @test68(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test69(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test69:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB69_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB69_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB69_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB69_4:
@@ -1036,7 +1036,7 @@ define void @test69(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test70(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test70:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    b .LBB70_2
 ; PPC64LE-NEXT:    .p2align 5
 ; PPC64LE-NEXT:  .LBB70_1:
@@ -1046,7 +1046,7 @@ define void @test70(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB70_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
@@ -1055,15 +1055,15 @@ define void @test70(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test71(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test71:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB71_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB71_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB71_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB71_4:
@@ -1076,15 +1076,15 @@ define void @test71(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test72(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test72:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB72_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB72_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB72_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB72_4:
@@ -1097,7 +1097,7 @@ define void @test72(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test73(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test73:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB73_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1108,7 +1108,7 @@ define void @test73(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB73_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
@@ -1117,7 +1117,7 @@ define void @test73(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test74(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test74:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB74_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1128,7 +1128,7 @@ define void @test74(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB74_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
@@ -1137,16 +1137,16 @@ define void @test74(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test75(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test75:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB75_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB75_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB75_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB75_4:
@@ -1159,16 +1159,16 @@ define void @test75(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test76(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test76:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB76_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB76_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB76_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB76_4:
@@ -1181,16 +1181,16 @@ define void @test76(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test77(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test77:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB77_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB77_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB77_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB77_4:
@@ -1203,16 +1203,16 @@ define void @test77(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test78(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test78:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB78_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB78_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB78_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB78_4:
@@ -1225,16 +1225,16 @@ define void @test78(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test79(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test79:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB79_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB79_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB79_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB79_4:
@@ -1247,7 +1247,7 @@ define void @test79(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test80:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    b .LBB80_2
 ; PPC64LE-NEXT:    .p2align 5
 ; PPC64LE-NEXT:  .LBB80_1:
@@ -1257,7 +1257,7 @@ define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB80_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic
@@ -1266,15 +1266,15 @@ define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test81:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB81_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB81_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB81_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB81_4:
@@ -1287,15 +1287,15 @@ define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test82:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB82_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB82_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB82_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB82_4:
@@ -1308,7 +1308,7 @@ define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test83:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB83_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1319,7 +1319,7 @@ define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB83_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic
@@ -1328,7 +1328,7 @@ define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test84:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB84_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1339,7 +1339,7 @@ define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB84_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire
@@ -1348,16 +1348,16 @@ define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test85:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB85_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB85_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB85_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB85_4:
@@ -1370,16 +1370,16 @@ define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test86:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB86_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB86_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB86_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB86_4:
@@ -1392,16 +1392,16 @@ define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test87:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB87_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB87_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB87_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB87_4:
@@ -1414,16 +1414,16 @@ define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test88:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB88_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB88_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB88_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB88_4:
@@ -1436,16 +1436,16 @@ define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test89:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB89_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB89_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB89_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB89_4:
@@ -1458,7 +1458,7 @@ define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
 
 define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test90:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    b .LBB90_2
 ; PPC64LE-NEXT:    .p2align 5
 ; PPC64LE-NEXT:  .LBB90_1:
@@ -1468,7 +1468,7 @@ define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB90_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic
@@ -1477,15 +1477,15 @@ define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test91:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB91_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB91_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB91_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB91_4:
@@ -1498,15 +1498,15 @@ define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test92:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB92_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB92_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB92_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB92_4:
@@ -1519,7 +1519,7 @@ define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test93:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB93_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1530,7 +1530,7 @@ define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB93_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic
@@ -1539,7 +1539,7 @@ define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test94:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB94_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1550,7 +1550,7 @@ define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB94_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire
@@ -1559,16 +1559,16 @@ define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test95:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB95_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB95_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB95_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB95_4:
@@ -1581,16 +1581,16 @@ define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test96:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB96_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB96_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB96_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB96_4:
@@ -1603,16 +1603,16 @@ define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test97:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB97_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB97_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB97_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB97_4:
@@ -1625,16 +1625,16 @@ define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test98:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB98_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB98_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB98_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB98_4:
@@ -1647,16 +1647,16 @@ define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test99:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB99_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB99_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB99_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB99_4:
@@ -1669,7 +1669,7 @@ define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
 
 define void @test100(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test100:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    b .LBB100_2
 ; PPC64LE-NEXT:    .p2align 5
 ; PPC64LE-NEXT:  .LBB100_1:
@@ -1679,7 +1679,7 @@ define void @test100(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB100_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic
@@ -1688,15 +1688,15 @@ define void @test100(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test101(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test101:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB101_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB101_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB101_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB101_4:
@@ -1709,15 +1709,15 @@ define void @test101(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test102(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test102:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB102_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB102_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB102_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB102_4:
@@ -1730,7 +1730,7 @@ define void @test102(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test103(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test103:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB103_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1741,7 +1741,7 @@ define void @test103(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB103_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic
@@ -1750,7 +1750,7 @@ define void @test103(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test104(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test104:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB104_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1761,7 +1761,7 @@ define void @test104(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB104_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire
@@ -1770,16 +1770,16 @@ define void @test104(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test105(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test105:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB105_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB105_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB105_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB105_4:
@@ -1792,16 +1792,16 @@ define void @test105(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test106(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test106:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB106_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB106_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB106_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB106_4:
@@ -1814,16 +1814,16 @@ define void @test106(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test107(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test107:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB107_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB107_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB107_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB107_4:
@@ -1836,16 +1836,16 @@ define void @test107(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test108(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test108:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB108_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB108_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB108_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB108_4:
@@ -1858,16 +1858,16 @@ define void @test108(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test109(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test109:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB109_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB109_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB109_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB109_4:
@@ -1880,7 +1880,7 @@ define void @test109(i32* %ptr, i32 %cmp, i32 %val) {
 
 define void @test110(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test110:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    b .LBB110_2
 ; PPC64LE-NEXT:    .p2align 5
 ; PPC64LE-NEXT:  .LBB110_1:
@@ -1890,7 +1890,7 @@ define void @test110(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB110_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic
@@ -1899,15 +1899,15 @@ define void @test110(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test111(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test111:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB111_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB111_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB111_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB111_4:
@@ -1920,15 +1920,15 @@ define void @test111(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test112(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test112:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB112_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB112_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB112_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB112_4:
@@ -1941,7 +1941,7 @@ define void @test112(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test113(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test113:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB113_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1952,7 +1952,7 @@ define void @test113(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB113_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic
@@ -1961,7 +1961,7 @@ define void @test113(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test114(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test114:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    b .LBB114_2
 ; PPC64LE-NEXT:    .p2align 5
@@ -1972,7 +1972,7 @@ define void @test114(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    beq 0, .LBB114_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire
@@ -1981,16 +1981,16 @@ define void @test114(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test115(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test115:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB115_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB115_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB115_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB115_4:
@@ -2003,16 +2003,16 @@ define void @test115(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test116(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test116:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB116_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB116_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB116_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB116_4:
@@ -2025,16 +2025,16 @@ define void @test116(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test117(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test117:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB117_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB117_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB117_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB117_4:
@@ -2047,16 +2047,16 @@ define void @test117(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test118(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test118:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB118_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB118_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB118_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB118_4:
@@ -2069,16 +2069,16 @@ define void @test118(i64* %ptr, i64 %cmp, i64 %val) {
 
 define void @test119(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test119:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB119_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 6
 ; PPC64LE-NEXT:    bne 0, .LBB119_4
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB119_1
-; PPC64LE-NEXT:  # BB#3:
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
 ; PPC64LE-NEXT:  .LBB119_4:
@@ -2091,12 +2091,12 @@ define void @test119(i64* %ptr, i64 %cmp, i64 %val) {
 
 define i8 @test120(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test120:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB120_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB120_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i8* %ptr, i8 %val monotonic
@@ -2105,13 +2105,13 @@ define i8 @test120(i8* %ptr, i8 %val) {
 
 define i8 @test121(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test121:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB121_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB121_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i8* %ptr, i8 %val acquire
@@ -2120,13 +2120,13 @@ define i8 @test121(i8* %ptr, i8 %val) {
 
 define i8 @test122(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test122:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB122_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB122_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i8* %ptr, i8 %val release
@@ -2135,13 +2135,13 @@ define i8 @test122(i8* %ptr, i8 %val) {
 
 define i8 @test123(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test123:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB123_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB123_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2151,13 +2151,13 @@ define i8 @test123(i8* %ptr, i8 %val) {
 
 define i8 @test124(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test124:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB124_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB124_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2167,12 +2167,12 @@ define i8 @test124(i8* %ptr, i8 %val) {
 
 define i16 @test125(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test125:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB125_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB125_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i16* %ptr, i16 %val monotonic
@@ -2181,13 +2181,13 @@ define i16 @test125(i16* %ptr, i16 %val) {
 
 define i16 @test126(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test126:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB126_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB126_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i16* %ptr, i16 %val acquire
@@ -2196,13 +2196,13 @@ define i16 @test126(i16* %ptr, i16 %val) {
 
 define i16 @test127(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test127:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB127_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB127_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i16* %ptr, i16 %val release
@@ -2211,13 +2211,13 @@ define i16 @test127(i16* %ptr, i16 %val) {
 
 define i16 @test128(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test128:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB128_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB128_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2227,13 +2227,13 @@ define i16 @test128(i16* %ptr, i16 %val) {
 
 define i16 @test129(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test129:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB129_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB129_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2243,12 +2243,12 @@ define i16 @test129(i16* %ptr, i16 %val) {
 
 define i32 @test130(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test130:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB130_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB130_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i32* %ptr, i32 %val monotonic
@@ -2257,13 +2257,13 @@ define i32 @test130(i32* %ptr, i32 %val) {
 
 define i32 @test131(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test131:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB131_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB131_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i32* %ptr, i32 %val acquire
@@ -2272,13 +2272,13 @@ define i32 @test131(i32* %ptr, i32 %val) {
 
 define i32 @test132(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test132:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB132_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB132_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i32* %ptr, i32 %val release
@@ -2287,13 +2287,13 @@ define i32 @test132(i32* %ptr, i32 %val) {
 
 define i32 @test133(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test133:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB133_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB133_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2303,13 +2303,13 @@ define i32 @test133(i32* %ptr, i32 %val) {
 
 define i32 @test134(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test134:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB134_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB134_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2319,12 +2319,12 @@ define i32 @test134(i32* %ptr, i32 %val) {
 
 define i64 @test135(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test135:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB135_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB135_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i64* %ptr, i64 %val monotonic
@@ -2333,13 +2333,13 @@ define i64 @test135(i64* %ptr, i64 %val) {
 
 define i64 @test136(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test136:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB136_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB136_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i64* %ptr, i64 %val acquire
@@ -2348,13 +2348,13 @@ define i64 @test136(i64* %ptr, i64 %val) {
 
 define i64 @test137(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test137:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB137_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB137_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i64* %ptr, i64 %val release
@@ -2363,13 +2363,13 @@ define i64 @test137(i64* %ptr, i64 %val) {
 
 define i64 @test138(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test138:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB138_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB138_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2379,13 +2379,13 @@ define i64 @test138(i64* %ptr, i64 %val) {
 
 define i64 @test139(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test139:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB139_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB139_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2395,13 +2395,13 @@ define i64 @test139(i64* %ptr, i64 %val) {
 
 define i8 @test140(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test140:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB140_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB140_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i8* %ptr, i8 %val monotonic
@@ -2410,14 +2410,14 @@ define i8 @test140(i8* %ptr, i8 %val) {
 
 define i8 @test141(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test141:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB141_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB141_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i8* %ptr, i8 %val acquire
@@ -2426,14 +2426,14 @@ define i8 @test141(i8* %ptr, i8 %val) {
 
 define i8 @test142(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test142:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB142_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB142_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i8* %ptr, i8 %val release
@@ -2442,14 +2442,14 @@ define i8 @test142(i8* %ptr, i8 %val) {
 
 define i8 @test143(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test143:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB143_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB143_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2459,14 +2459,14 @@ define i8 @test143(i8* %ptr, i8 %val) {
 
 define i8 @test144(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test144:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB144_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB144_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2476,13 +2476,13 @@ define i8 @test144(i8* %ptr, i8 %val) {
 
 define i16 @test145(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test145:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB145_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB145_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i16* %ptr, i16 %val monotonic
@@ -2491,14 +2491,14 @@ define i16 @test145(i16* %ptr, i16 %val) {
 
 define i16 @test146(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test146:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB146_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB146_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i16* %ptr, i16 %val acquire
@@ -2507,14 +2507,14 @@ define i16 @test146(i16* %ptr, i16 %val) {
 
 define i16 @test147(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test147:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB147_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB147_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i16* %ptr, i16 %val release
@@ -2523,14 +2523,14 @@ define i16 @test147(i16* %ptr, i16 %val) {
 
 define i16 @test148(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test148:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB148_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB148_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2540,14 +2540,14 @@ define i16 @test148(i16* %ptr, i16 %val) {
 
 define i16 @test149(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test149:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB149_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB149_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2557,13 +2557,13 @@ define i16 @test149(i16* %ptr, i16 %val) {
 
 define i32 @test150(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test150:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB150_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB150_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i32* %ptr, i32 %val monotonic
@@ -2572,14 +2572,14 @@ define i32 @test150(i32* %ptr, i32 %val) {
 
 define i32 @test151(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test151:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB151_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB151_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i32* %ptr, i32 %val acquire
@@ -2588,14 +2588,14 @@ define i32 @test151(i32* %ptr, i32 %val) {
 
 define i32 @test152(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test152:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB152_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB152_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i32* %ptr, i32 %val release
@@ -2604,14 +2604,14 @@ define i32 @test152(i32* %ptr, i32 %val) {
 
 define i32 @test153(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test153:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB153_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB153_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2621,14 +2621,14 @@ define i32 @test153(i32* %ptr, i32 %val) {
 
 define i32 @test154(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test154:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB154_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB154_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2638,13 +2638,13 @@ define i32 @test154(i32* %ptr, i32 %val) {
 
 define i64 @test155(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test155:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB155_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB155_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i64* %ptr, i64 %val monotonic
@@ -2653,14 +2653,14 @@ define i64 @test155(i64* %ptr, i64 %val) {
 
 define i64 @test156(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test156:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB156_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB156_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i64* %ptr, i64 %val acquire
@@ -2669,14 +2669,14 @@ define i64 @test156(i64* %ptr, i64 %val) {
 
 define i64 @test157(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test157:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB157_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB157_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i64* %ptr, i64 %val release
@@ -2685,14 +2685,14 @@ define i64 @test157(i64* %ptr, i64 %val) {
 
 define i64 @test158(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test158:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB158_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB158_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2702,14 +2702,14 @@ define i64 @test158(i64* %ptr, i64 %val) {
 
 define i64 @test159(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test159:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB159_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB159_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2719,13 +2719,13 @@ define i64 @test159(i64* %ptr, i64 %val) {
 
 define i8 @test160(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test160:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB160_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB160_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val monotonic
@@ -2734,14 +2734,14 @@ define i8 @test160(i8* %ptr, i8 %val) {
 
 define i8 @test161(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test161:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB161_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB161_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val acquire
@@ -2750,14 +2750,14 @@ define i8 @test161(i8* %ptr, i8 %val) {
 
 define i8 @test162(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test162:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB162_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB162_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val release
@@ -2766,14 +2766,14 @@ define i8 @test162(i8* %ptr, i8 %val) {
 
 define i8 @test163(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test163:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB163_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB163_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2783,14 +2783,14 @@ define i8 @test163(i8* %ptr, i8 %val) {
 
 define i8 @test164(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test164:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB164_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB164_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2800,13 +2800,13 @@ define i8 @test164(i8* %ptr, i8 %val) {
 
 define i16 @test165(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test165:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB165_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB165_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val monotonic
@@ -2815,14 +2815,14 @@ define i16 @test165(i16* %ptr, i16 %val) {
 
 define i16 @test166(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test166:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB166_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB166_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val acquire
@@ -2831,14 +2831,14 @@ define i16 @test166(i16* %ptr, i16 %val) {
 
 define i16 @test167(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test167:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB167_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB167_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val release
@@ -2847,14 +2847,14 @@ define i16 @test167(i16* %ptr, i16 %val) {
 
 define i16 @test168(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test168:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB168_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB168_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2864,14 +2864,14 @@ define i16 @test168(i16* %ptr, i16 %val) {
 
 define i16 @test169(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test169:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB169_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB169_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2881,13 +2881,13 @@ define i16 @test169(i16* %ptr, i16 %val) {
 
 define i32 @test170(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test170:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB170_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB170_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val monotonic
@@ -2896,14 +2896,14 @@ define i32 @test170(i32* %ptr, i32 %val) {
 
 define i32 @test171(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test171:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB171_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB171_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val acquire
@@ -2912,14 +2912,14 @@ define i32 @test171(i32* %ptr, i32 %val) {
 
 define i32 @test172(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test172:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB172_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB172_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val release
@@ -2928,14 +2928,14 @@ define i32 @test172(i32* %ptr, i32 %val) {
 
 define i32 @test173(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test173:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB173_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB173_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2945,14 +2945,14 @@ define i32 @test173(i32* %ptr, i32 %val) {
 
 define i32 @test174(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test174:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB174_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB174_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -2962,13 +2962,13 @@ define i32 @test174(i32* %ptr, i32 %val) {
 
 define i64 @test175(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test175:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB175_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB175_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i64* %ptr, i64 %val monotonic
@@ -2977,14 +2977,14 @@ define i64 @test175(i64* %ptr, i64 %val) {
 
 define i64 @test176(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test176:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB176_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB176_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i64* %ptr, i64 %val acquire
@@ -2993,14 +2993,14 @@ define i64 @test176(i64* %ptr, i64 %val) {
 
 define i64 @test177(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test177:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB177_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB177_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i64* %ptr, i64 %val release
@@ -3009,14 +3009,14 @@ define i64 @test177(i64* %ptr, i64 %val) {
 
 define i64 @test178(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test178:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB178_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB178_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3026,14 +3026,14 @@ define i64 @test178(i64* %ptr, i64 %val) {
 
 define i64 @test179(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test179:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB179_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB179_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3043,13 +3043,13 @@ define i64 @test179(i64* %ptr, i64 %val) {
 
 define i8 @test180(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test180:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB180_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB180_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i8* %ptr, i8 %val monotonic
@@ -3058,14 +3058,14 @@ define i8 @test180(i8* %ptr, i8 %val) {
 
 define i8 @test181(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test181:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB181_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB181_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i8* %ptr, i8 %val acquire
@@ -3074,14 +3074,14 @@ define i8 @test181(i8* %ptr, i8 %val) {
 
 define i8 @test182(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test182:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB182_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB182_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i8* %ptr, i8 %val release
@@ -3090,14 +3090,14 @@ define i8 @test182(i8* %ptr, i8 %val) {
 
 define i8 @test183(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test183:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB183_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB183_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3107,14 +3107,14 @@ define i8 @test183(i8* %ptr, i8 %val) {
 
 define i8 @test184(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test184:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB184_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB184_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3124,13 +3124,13 @@ define i8 @test184(i8* %ptr, i8 %val) {
 
 define i16 @test185(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test185:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB185_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB185_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i16* %ptr, i16 %val monotonic
@@ -3139,14 +3139,14 @@ define i16 @test185(i16* %ptr, i16 %val) {
 
 define i16 @test186(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test186:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB186_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB186_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i16* %ptr, i16 %val acquire
@@ -3155,14 +3155,14 @@ define i16 @test186(i16* %ptr, i16 %val) {
 
 define i16 @test187(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test187:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB187_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB187_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i16* %ptr, i16 %val release
@@ -3171,14 +3171,14 @@ define i16 @test187(i16* %ptr, i16 %val) {
 
 define i16 @test188(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test188:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB188_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB188_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3188,14 +3188,14 @@ define i16 @test188(i16* %ptr, i16 %val) {
 
 define i16 @test189(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test189:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB189_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB189_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3205,13 +3205,13 @@ define i16 @test189(i16* %ptr, i16 %val) {
 
 define i32 @test190(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test190:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB190_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB190_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i32* %ptr, i32 %val monotonic
@@ -3220,14 +3220,14 @@ define i32 @test190(i32* %ptr, i32 %val) {
 
 define i32 @test191(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test191:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB191_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB191_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i32* %ptr, i32 %val acquire
@@ -3236,14 +3236,14 @@ define i32 @test191(i32* %ptr, i32 %val) {
 
 define i32 @test192(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test192:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB192_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB192_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i32* %ptr, i32 %val release
@@ -3252,14 +3252,14 @@ define i32 @test192(i32* %ptr, i32 %val) {
 
 define i32 @test193(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test193:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB193_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB193_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3269,14 +3269,14 @@ define i32 @test193(i32* %ptr, i32 %val) {
 
 define i32 @test194(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test194:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB194_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB194_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3286,13 +3286,13 @@ define i32 @test194(i32* %ptr, i32 %val) {
 
 define i64 @test195(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test195:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB195_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB195_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i64* %ptr, i64 %val monotonic
@@ -3301,14 +3301,14 @@ define i64 @test195(i64* %ptr, i64 %val) {
 
 define i64 @test196(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test196:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB196_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB196_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i64* %ptr, i64 %val acquire
@@ -3317,14 +3317,14 @@ define i64 @test196(i64* %ptr, i64 %val) {
 
 define i64 @test197(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test197:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB197_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB197_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i64* %ptr, i64 %val release
@@ -3333,14 +3333,14 @@ define i64 @test197(i64* %ptr, i64 %val) {
 
 define i64 @test198(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test198:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB198_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB198_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3350,14 +3350,14 @@ define i64 @test198(i64* %ptr, i64 %val) {
 
 define i64 @test199(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test199:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB199_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB199_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3367,13 +3367,13 @@ define i64 @test199(i64* %ptr, i64 %val) {
 
 define i8 @test200(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test200:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB200_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB200_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i8* %ptr, i8 %val monotonic
@@ -3382,14 +3382,14 @@ define i8 @test200(i8* %ptr, i8 %val) {
 
 define i8 @test201(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test201:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB201_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB201_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i8* %ptr, i8 %val acquire
@@ -3398,14 +3398,14 @@ define i8 @test201(i8* %ptr, i8 %val) {
 
 define i8 @test202(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test202:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB202_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB202_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i8* %ptr, i8 %val release
@@ -3414,14 +3414,14 @@ define i8 @test202(i8* %ptr, i8 %val) {
 
 define i8 @test203(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test203:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB203_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB203_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3431,14 +3431,14 @@ define i8 @test203(i8* %ptr, i8 %val) {
 
 define i8 @test204(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test204:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB204_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB204_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3448,13 +3448,13 @@ define i8 @test204(i8* %ptr, i8 %val) {
 
 define i16 @test205(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test205:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB205_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB205_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i16* %ptr, i16 %val monotonic
@@ -3463,14 +3463,14 @@ define i16 @test205(i16* %ptr, i16 %val) {
 
 define i16 @test206(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test206:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB206_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB206_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i16* %ptr, i16 %val acquire
@@ -3479,14 +3479,14 @@ define i16 @test206(i16* %ptr, i16 %val) {
 
 define i16 @test207(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test207:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB207_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB207_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i16* %ptr, i16 %val release
@@ -3495,14 +3495,14 @@ define i16 @test207(i16* %ptr, i16 %val) {
 
 define i16 @test208(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test208:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB208_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB208_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3512,14 +3512,14 @@ define i16 @test208(i16* %ptr, i16 %val) {
 
 define i16 @test209(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test209:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB209_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB209_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3529,13 +3529,13 @@ define i16 @test209(i16* %ptr, i16 %val) {
 
 define i32 @test210(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test210:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB210_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB210_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i32* %ptr, i32 %val monotonic
@@ -3544,14 +3544,14 @@ define i32 @test210(i32* %ptr, i32 %val) {
 
 define i32 @test211(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test211:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB211_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB211_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i32* %ptr, i32 %val acquire
@@ -3560,14 +3560,14 @@ define i32 @test211(i32* %ptr, i32 %val) {
 
 define i32 @test212(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test212:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB212_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB212_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i32* %ptr, i32 %val release
@@ -3576,14 +3576,14 @@ define i32 @test212(i32* %ptr, i32 %val) {
 
 define i32 @test213(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test213:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB213_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB213_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3593,14 +3593,14 @@ define i32 @test213(i32* %ptr, i32 %val) {
 
 define i32 @test214(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test214:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB214_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB214_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3610,13 +3610,13 @@ define i32 @test214(i32* %ptr, i32 %val) {
 
 define i64 @test215(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test215:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB215_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB215_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i64* %ptr, i64 %val monotonic
@@ -3625,14 +3625,14 @@ define i64 @test215(i64* %ptr, i64 %val) {
 
 define i64 @test216(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test216:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB216_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB216_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i64* %ptr, i64 %val acquire
@@ -3641,14 +3641,14 @@ define i64 @test216(i64* %ptr, i64 %val) {
 
 define i64 @test217(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test217:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB217_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB217_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i64* %ptr, i64 %val release
@@ -3657,14 +3657,14 @@ define i64 @test217(i64* %ptr, i64 %val) {
 
 define i64 @test218(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test218:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB218_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB218_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3674,14 +3674,14 @@ define i64 @test218(i64* %ptr, i64 %val) {
 
 define i64 @test219(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test219:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB219_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB219_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3691,13 +3691,13 @@ define i64 @test219(i64* %ptr, i64 %val) {
 
 define i8 @test220(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test220:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB220_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB220_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i8* %ptr, i8 %val monotonic
@@ -3706,14 +3706,14 @@ define i8 @test220(i8* %ptr, i8 %val) {
 
 define i8 @test221(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test221:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB221_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB221_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i8* %ptr, i8 %val acquire
@@ -3722,14 +3722,14 @@ define i8 @test221(i8* %ptr, i8 %val) {
 
 define i8 @test222(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test222:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB222_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB222_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i8* %ptr, i8 %val release
@@ -3738,14 +3738,14 @@ define i8 @test222(i8* %ptr, i8 %val) {
 
 define i8 @test223(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test223:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB223_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB223_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3755,14 +3755,14 @@ define i8 @test223(i8* %ptr, i8 %val) {
 
 define i8 @test224(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test224:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB224_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB224_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3772,13 +3772,13 @@ define i8 @test224(i8* %ptr, i8 %val) {
 
 define i16 @test225(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test225:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB225_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB225_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i16* %ptr, i16 %val monotonic
@@ -3787,14 +3787,14 @@ define i16 @test225(i16* %ptr, i16 %val) {
 
 define i16 @test226(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test226:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB226_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB226_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i16* %ptr, i16 %val acquire
@@ -3803,14 +3803,14 @@ define i16 @test226(i16* %ptr, i16 %val) {
 
 define i16 @test227(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test227:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB227_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB227_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i16* %ptr, i16 %val release
@@ -3819,14 +3819,14 @@ define i16 @test227(i16* %ptr, i16 %val) {
 
 define i16 @test228(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test228:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB228_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB228_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3836,14 +3836,14 @@ define i16 @test228(i16* %ptr, i16 %val) {
 
 define i16 @test229(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test229:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB229_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB229_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3853,13 +3853,13 @@ define i16 @test229(i16* %ptr, i16 %val) {
 
 define i32 @test230(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test230:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB230_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB230_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i32* %ptr, i32 %val monotonic
@@ -3868,14 +3868,14 @@ define i32 @test230(i32* %ptr, i32 %val) {
 
 define i32 @test231(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test231:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB231_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB231_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i32* %ptr, i32 %val acquire
@@ -3884,14 +3884,14 @@ define i32 @test231(i32* %ptr, i32 %val) {
 
 define i32 @test232(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test232:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB232_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB232_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i32* %ptr, i32 %val release
@@ -3900,14 +3900,14 @@ define i32 @test232(i32* %ptr, i32 %val) {
 
 define i32 @test233(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test233:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB233_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB233_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3917,14 +3917,14 @@ define i32 @test233(i32* %ptr, i32 %val) {
 
 define i32 @test234(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test234:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB234_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB234_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3934,13 +3934,13 @@ define i32 @test234(i32* %ptr, i32 %val) {
 
 define i64 @test235(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test235:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB235_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB235_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i64* %ptr, i64 %val monotonic
@@ -3949,14 +3949,14 @@ define i64 @test235(i64* %ptr, i64 %val) {
 
 define i64 @test236(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test236:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB236_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB236_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i64* %ptr, i64 %val acquire
@@ -3965,14 +3965,14 @@ define i64 @test236(i64* %ptr, i64 %val) {
 
 define i64 @test237(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test237:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB237_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB237_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i64* %ptr, i64 %val release
@@ -3981,14 +3981,14 @@ define i64 @test237(i64* %ptr, i64 %val) {
 
 define i64 @test238(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test238:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB238_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB238_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -3998,14 +3998,14 @@ define i64 @test238(i64* %ptr, i64 %val) {
 
 define i64 @test239(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test239:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB239_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB239_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -4015,13 +4015,13 @@ define i64 @test239(i64* %ptr, i64 %val) {
 
 define i8 @test240(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test240:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB240_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB240_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i8* %ptr, i8 %val monotonic
@@ -4030,14 +4030,14 @@ define i8 @test240(i8* %ptr, i8 %val) {
 
 define i8 @test241(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test241:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB241_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB241_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i8* %ptr, i8 %val acquire
@@ -4046,14 +4046,14 @@ define i8 @test241(i8* %ptr, i8 %val) {
 
 define i8 @test242(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test242:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB242_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB242_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i8* %ptr, i8 %val release
@@ -4062,14 +4062,14 @@ define i8 @test242(i8* %ptr, i8 %val) {
 
 define i8 @test243(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test243:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB243_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB243_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -4079,14 +4079,14 @@ define i8 @test243(i8* %ptr, i8 %val) {
 
 define i8 @test244(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test244:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB244_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB244_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -4096,13 +4096,13 @@ define i8 @test244(i8* %ptr, i8 %val) {
 
 define i16 @test245(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test245:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB245_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB245_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i16* %ptr, i16 %val monotonic
@@ -4111,14 +4111,14 @@ define i16 @test245(i16* %ptr, i16 %val) {
 
 define i16 @test246(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test246:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB246_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB246_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i16* %ptr, i16 %val acquire
@@ -4127,14 +4127,14 @@ define i16 @test246(i16* %ptr, i16 %val) {
 
 define i16 @test247(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test247:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB247_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB247_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i16* %ptr, i16 %val release
@@ -4143,14 +4143,14 @@ define i16 @test247(i16* %ptr, i16 %val) {
 
 define i16 @test248(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test248:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB248_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB248_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -4160,14 +4160,14 @@ define i16 @test248(i16* %ptr, i16 %val) {
 
 define i16 @test249(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test249:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB249_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB249_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -4177,13 +4177,13 @@ define i16 @test249(i16* %ptr, i16 %val) {
 
 define i32 @test250(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test250:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB250_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB250_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i32* %ptr, i32 %val monotonic
@@ -4192,14 +4192,14 @@ define i32 @test250(i32* %ptr, i32 %val) {
 
 define i32 @test251(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test251:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB251_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB251_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i32* %ptr, i32 %val acquire
@@ -4208,14 +4208,14 @@ define i32 @test251(i32* %ptr, i32 %val) {
 
 define i32 @test252(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test252:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB252_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB252_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i32* %ptr, i32 %val release
@@ -4224,14 +4224,14 @@ define i32 @test252(i32* %ptr, i32 %val) {
 
 define i32 @test253(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test253:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB253_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB253_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -4241,14 +4241,14 @@ define i32 @test253(i32* %ptr, i32 %val) {
 
 define i32 @test254(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test254:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB254_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB254_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -4258,13 +4258,13 @@ define i32 @test254(i32* %ptr, i32 %val) {
 
 define i64 @test255(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test255:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB255_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB255_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i64* %ptr, i64 %val monotonic
@@ -4273,14 +4273,14 @@ define i64 @test255(i64* %ptr, i64 %val) {
 
 define i64 @test256(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test256:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB256_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB256_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i64* %ptr, i64 %val acquire
@@ -4289,14 +4289,14 @@ define i64 @test256(i64* %ptr, i64 %val) {
 
 define i64 @test257(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test257:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB257_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB257_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i64* %ptr, i64 %val release
@@ -4305,14 +4305,14 @@ define i64 @test257(i64* %ptr, i64 %val) {
 
 define i64 @test258(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test258:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB258_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB258_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -4322,14 +4322,14 @@ define i64 @test258(i64* %ptr, i64 %val) {
 
 define i64 @test259(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test259:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB259_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB259_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -4339,13 +4339,13 @@ define i64 @test259(i64* %ptr, i64 %val) {
 
 define i8 @test260(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test260:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB260_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB260_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB260_1
 ; PPC64LE-NEXT:  .LBB260_3:
@@ -4357,14 +4357,14 @@ define i8 @test260(i8* %ptr, i8 %val) {
 
 define i8 @test261(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test261:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB261_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    extsb 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB261_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB261_1
 ; PPC64LE-NEXT:  .LBB261_3:
@@ -4376,14 +4376,14 @@ define i8 @test261(i8* %ptr, i8 %val) {
 
 define i8 @test262(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test262:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB262_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB262_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB262_1
 ; PPC64LE-NEXT:  .LBB262_3:
@@ -4395,14 +4395,14 @@ define i8 @test262(i8* %ptr, i8 %val) {
 
 define i8 @test263(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test263:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB263_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB263_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB263_1
 ; PPC64LE-NEXT:  .LBB263_3:
@@ -4415,14 +4415,14 @@ define i8 @test263(i8* %ptr, i8 %val) {
 
 define i8 @test264(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test264:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB264_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB264_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB264_1
 ; PPC64LE-NEXT:  .LBB264_3:
@@ -4435,13 +4435,13 @@ define i8 @test264(i8* %ptr, i8 %val) {
 
 define i16 @test265(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test265:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB265_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB265_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB265_1
 ; PPC64LE-NEXT:  .LBB265_3:
@@ -4453,14 +4453,14 @@ define i16 @test265(i16* %ptr, i16 %val) {
 
 define i16 @test266(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test266:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB266_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    extsh 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB266_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB266_1
 ; PPC64LE-NEXT:  .LBB266_3:
@@ -4472,14 +4472,14 @@ define i16 @test266(i16* %ptr, i16 %val) {
 
 define i16 @test267(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test267:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB267_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB267_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB267_1
 ; PPC64LE-NEXT:  .LBB267_3:
@@ -4491,14 +4491,14 @@ define i16 @test267(i16* %ptr, i16 %val) {
 
 define i16 @test268(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test268:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB268_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB268_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB268_1
 ; PPC64LE-NEXT:  .LBB268_3:
@@ -4511,14 +4511,14 @@ define i16 @test268(i16* %ptr, i16 %val) {
 
 define i16 @test269(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test269:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB269_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB269_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB269_1
 ; PPC64LE-NEXT:  .LBB269_3:
@@ -4531,12 +4531,12 @@ define i16 @test269(i16* %ptr, i16 %val) {
 
 define i32 @test270(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test270:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB270_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB270_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB270_1
 ; PPC64LE-NEXT:  .LBB270_3:
@@ -4548,13 +4548,13 @@ define i32 @test270(i32* %ptr, i32 %val) {
 
 define i32 @test271(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test271:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB271_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB271_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB271_1
 ; PPC64LE-NEXT:  .LBB271_3:
@@ -4566,13 +4566,13 @@ define i32 @test271(i32* %ptr, i32 %val) {
 
 define i32 @test272(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test272:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB272_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB272_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB272_1
 ; PPC64LE-NEXT:  .LBB272_3:
@@ -4584,13 +4584,13 @@ define i32 @test272(i32* %ptr, i32 %val) {
 
 define i32 @test273(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test273:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB273_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB273_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB273_1
 ; PPC64LE-NEXT:  .LBB273_3:
@@ -4603,13 +4603,13 @@ define i32 @test273(i32* %ptr, i32 %val) {
 
 define i32 @test274(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test274:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB274_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB274_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB274_1
 ; PPC64LE-NEXT:  .LBB274_3:
@@ -4622,12 +4622,12 @@ define i32 @test274(i32* %ptr, i32 %val) {
 
 define i64 @test275(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test275:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB275_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB275_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB275_1
 ; PPC64LE-NEXT:  .LBB275_3:
@@ -4639,13 +4639,13 @@ define i64 @test275(i64* %ptr, i64 %val) {
 
 define i64 @test276(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test276:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB276_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpd 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB276_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB276_1
 ; PPC64LE-NEXT:  .LBB276_3:
@@ -4657,13 +4657,13 @@ define i64 @test276(i64* %ptr, i64 %val) {
 
 define i64 @test277(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test277:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB277_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB277_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB277_1
 ; PPC64LE-NEXT:  .LBB277_3:
@@ -4675,13 +4675,13 @@ define i64 @test277(i64* %ptr, i64 %val) {
 
 define i64 @test278(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test278:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB278_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB278_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB278_1
 ; PPC64LE-NEXT:  .LBB278_3:
@@ -4694,13 +4694,13 @@ define i64 @test278(i64* %ptr, i64 %val) {
 
 define i64 @test279(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test279:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB279_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB279_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB279_1
 ; PPC64LE-NEXT:  .LBB279_3:
@@ -4713,13 +4713,13 @@ define i64 @test279(i64* %ptr, i64 %val) {
 
 define i8 @test280(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test280:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB280_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB280_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB280_1
 ; PPC64LE-NEXT:  .LBB280_3:
@@ -4731,14 +4731,14 @@ define i8 @test280(i8* %ptr, i8 %val) {
 
 define i8 @test281(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test281:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB281_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    extsb 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB281_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB281_1
 ; PPC64LE-NEXT:  .LBB281_3:
@@ -4750,14 +4750,14 @@ define i8 @test281(i8* %ptr, i8 %val) {
 
 define i8 @test282(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test282:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB282_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB282_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB282_1
 ; PPC64LE-NEXT:  .LBB282_3:
@@ -4769,14 +4769,14 @@ define i8 @test282(i8* %ptr, i8 %val) {
 
 define i8 @test283(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test283:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB283_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB283_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB283_1
 ; PPC64LE-NEXT:  .LBB283_3:
@@ -4789,14 +4789,14 @@ define i8 @test283(i8* %ptr, i8 %val) {
 
 define i8 @test284(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test284:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB284_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB284_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB284_1
 ; PPC64LE-NEXT:  .LBB284_3:
@@ -4809,13 +4809,13 @@ define i8 @test284(i8* %ptr, i8 %val) {
 
 define i16 @test285(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test285:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB285_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB285_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB285_1
 ; PPC64LE-NEXT:  .LBB285_3:
@@ -4827,14 +4827,14 @@ define i16 @test285(i16* %ptr, i16 %val) {
 
 define i16 @test286(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test286:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB286_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    extsh 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB286_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB286_1
 ; PPC64LE-NEXT:  .LBB286_3:
@@ -4846,14 +4846,14 @@ define i16 @test286(i16* %ptr, i16 %val) {
 
 define i16 @test287(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test287:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB287_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB287_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB287_1
 ; PPC64LE-NEXT:  .LBB287_3:
@@ -4865,14 +4865,14 @@ define i16 @test287(i16* %ptr, i16 %val) {
 
 define i16 @test288(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test288:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB288_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB288_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB288_1
 ; PPC64LE-NEXT:  .LBB288_3:
@@ -4885,14 +4885,14 @@ define i16 @test288(i16* %ptr, i16 %val) {
 
 define i16 @test289(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test289:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB289_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB289_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB289_1
 ; PPC64LE-NEXT:  .LBB289_3:
@@ -4905,12 +4905,12 @@ define i16 @test289(i16* %ptr, i16 %val) {
 
 define i32 @test290(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test290:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB290_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB290_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB290_1
 ; PPC64LE-NEXT:  .LBB290_3:
@@ -4922,13 +4922,13 @@ define i32 @test290(i32* %ptr, i32 %val) {
 
 define i32 @test291(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test291:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB291_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB291_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB291_1
 ; PPC64LE-NEXT:  .LBB291_3:
@@ -4940,13 +4940,13 @@ define i32 @test291(i32* %ptr, i32 %val) {
 
 define i32 @test292(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test292:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB292_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB292_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB292_1
 ; PPC64LE-NEXT:  .LBB292_3:
@@ -4958,13 +4958,13 @@ define i32 @test292(i32* %ptr, i32 %val) {
 
 define i32 @test293(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test293:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB293_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB293_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB293_1
 ; PPC64LE-NEXT:  .LBB293_3:
@@ -4977,13 +4977,13 @@ define i32 @test293(i32* %ptr, i32 %val) {
 
 define i32 @test294(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test294:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB294_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB294_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB294_1
 ; PPC64LE-NEXT:  .LBB294_3:
@@ -4996,12 +4996,12 @@ define i32 @test294(i32* %ptr, i32 %val) {
 
 define i64 @test295(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test295:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB295_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB295_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB295_1
 ; PPC64LE-NEXT:  .LBB295_3:
@@ -5013,13 +5013,13 @@ define i64 @test295(i64* %ptr, i64 %val) {
 
 define i64 @test296(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test296:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB296_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpd 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB296_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB296_1
 ; PPC64LE-NEXT:  .LBB296_3:
@@ -5031,13 +5031,13 @@ define i64 @test296(i64* %ptr, i64 %val) {
 
 define i64 @test297(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test297:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB297_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB297_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB297_1
 ; PPC64LE-NEXT:  .LBB297_3:
@@ -5049,13 +5049,13 @@ define i64 @test297(i64* %ptr, i64 %val) {
 
 define i64 @test298(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test298:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB298_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB298_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB298_1
 ; PPC64LE-NEXT:  .LBB298_3:
@@ -5068,13 +5068,13 @@ define i64 @test298(i64* %ptr, i64 %val) {
 
 define i64 @test299(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test299:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB299_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB299_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB299_1
 ; PPC64LE-NEXT:  .LBB299_3:
@@ -5087,12 +5087,12 @@ define i64 @test299(i64* %ptr, i64 %val) {
 
 define i8 @test300(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test300:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB300_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB300_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB300_1
 ; PPC64LE-NEXT:  .LBB300_3:
@@ -5104,13 +5104,13 @@ define i8 @test300(i8* %ptr, i8 %val) {
 
 define i8 @test301(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test301:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB301_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB301_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB301_1
 ; PPC64LE-NEXT:  .LBB301_3:
@@ -5122,13 +5122,13 @@ define i8 @test301(i8* %ptr, i8 %val) {
 
 define i8 @test302(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test302:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB302_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB302_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB302_1
 ; PPC64LE-NEXT:  .LBB302_3:
@@ -5140,13 +5140,13 @@ define i8 @test302(i8* %ptr, i8 %val) {
 
 define i8 @test303(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test303:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB303_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB303_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB303_1
 ; PPC64LE-NEXT:  .LBB303_3:
@@ -5159,13 +5159,13 @@ define i8 @test303(i8* %ptr, i8 %val) {
 
 define i8 @test304(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test304:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB304_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB304_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB304_1
 ; PPC64LE-NEXT:  .LBB304_3:
@@ -5178,12 +5178,12 @@ define i8 @test304(i8* %ptr, i8 %val) {
 
 define i16 @test305(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test305:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB305_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB305_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB305_1
 ; PPC64LE-NEXT:  .LBB305_3:
@@ -5195,13 +5195,13 @@ define i16 @test305(i16* %ptr, i16 %val) {
 
 define i16 @test306(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test306:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB306_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB306_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB306_1
 ; PPC64LE-NEXT:  .LBB306_3:
@@ -5213,13 +5213,13 @@ define i16 @test306(i16* %ptr, i16 %val) {
 
 define i16 @test307(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test307:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB307_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB307_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB307_1
 ; PPC64LE-NEXT:  .LBB307_3:
@@ -5231,13 +5231,13 @@ define i16 @test307(i16* %ptr, i16 %val) {
 
 define i16 @test308(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test308:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB308_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB308_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB308_1
 ; PPC64LE-NEXT:  .LBB308_3:
@@ -5250,13 +5250,13 @@ define i16 @test308(i16* %ptr, i16 %val) {
 
 define i16 @test309(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test309:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB309_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB309_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB309_1
 ; PPC64LE-NEXT:  .LBB309_3:
@@ -5269,12 +5269,12 @@ define i16 @test309(i16* %ptr, i16 %val) {
 
 define i32 @test310(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test310:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB310_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB310_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB310_1
 ; PPC64LE-NEXT:  .LBB310_3:
@@ -5286,13 +5286,13 @@ define i32 @test310(i32* %ptr, i32 %val) {
 
 define i32 @test311(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test311:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB311_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB311_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB311_1
 ; PPC64LE-NEXT:  .LBB311_3:
@@ -5304,13 +5304,13 @@ define i32 @test311(i32* %ptr, i32 %val) {
 
 define i32 @test312(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test312:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB312_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB312_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB312_1
 ; PPC64LE-NEXT:  .LBB312_3:
@@ -5322,13 +5322,13 @@ define i32 @test312(i32* %ptr, i32 %val) {
 
 define i32 @test313(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test313:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB313_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB313_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB313_1
 ; PPC64LE-NEXT:  .LBB313_3:
@@ -5341,13 +5341,13 @@ define i32 @test313(i32* %ptr, i32 %val) {
 
 define i32 @test314(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test314:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB314_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB314_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB314_1
 ; PPC64LE-NEXT:  .LBB314_3:
@@ -5360,12 +5360,12 @@ define i32 @test314(i32* %ptr, i32 %val) {
 
 define i64 @test315(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test315:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB315_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB315_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB315_1
 ; PPC64LE-NEXT:  .LBB315_3:
@@ -5377,13 +5377,13 @@ define i64 @test315(i64* %ptr, i64 %val) {
 
 define i64 @test316(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test316:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB316_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpld 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB316_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB316_1
 ; PPC64LE-NEXT:  .LBB316_3:
@@ -5395,13 +5395,13 @@ define i64 @test316(i64* %ptr, i64 %val) {
 
 define i64 @test317(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test317:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB317_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB317_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB317_1
 ; PPC64LE-NEXT:  .LBB317_3:
@@ -5413,13 +5413,13 @@ define i64 @test317(i64* %ptr, i64 %val) {
 
 define i64 @test318(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test318:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB318_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB318_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB318_1
 ; PPC64LE-NEXT:  .LBB318_3:
@@ -5432,13 +5432,13 @@ define i64 @test318(i64* %ptr, i64 %val) {
 
 define i64 @test319(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test319:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB319_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB319_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB319_1
 ; PPC64LE-NEXT:  .LBB319_3:
@@ -5451,12 +5451,12 @@ define i64 @test319(i64* %ptr, i64 %val) {
 
 define i8 @test320(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test320:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB320_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB320_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB320_1
 ; PPC64LE-NEXT:  .LBB320_3:
@@ -5468,13 +5468,13 @@ define i8 @test320(i8* %ptr, i8 %val) {
 
 define i8 @test321(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test321:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB321_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB321_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB321_1
 ; PPC64LE-NEXT:  .LBB321_3:
@@ -5486,13 +5486,13 @@ define i8 @test321(i8* %ptr, i8 %val) {
 
 define i8 @test322(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test322:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB322_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB322_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB322_1
 ; PPC64LE-NEXT:  .LBB322_3:
@@ -5504,13 +5504,13 @@ define i8 @test322(i8* %ptr, i8 %val) {
 
 define i8 @test323(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test323:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB323_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB323_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB323_1
 ; PPC64LE-NEXT:  .LBB323_3:
@@ -5523,13 +5523,13 @@ define i8 @test323(i8* %ptr, i8 %val) {
 
 define i8 @test324(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test324:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB324_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB324_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB324_1
 ; PPC64LE-NEXT:  .LBB324_3:
@@ -5542,12 +5542,12 @@ define i8 @test324(i8* %ptr, i8 %val) {
 
 define i16 @test325(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test325:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB325_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB325_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB325_1
 ; PPC64LE-NEXT:  .LBB325_3:
@@ -5559,13 +5559,13 @@ define i16 @test325(i16* %ptr, i16 %val) {
 
 define i16 @test326(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test326:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB326_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB326_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB326_1
 ; PPC64LE-NEXT:  .LBB326_3:
@@ -5577,13 +5577,13 @@ define i16 @test326(i16* %ptr, i16 %val) {
 
 define i16 @test327(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test327:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB327_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB327_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB327_1
 ; PPC64LE-NEXT:  .LBB327_3:
@@ -5595,13 +5595,13 @@ define i16 @test327(i16* %ptr, i16 %val) {
 
 define i16 @test328(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test328:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB328_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB328_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB328_1
 ; PPC64LE-NEXT:  .LBB328_3:
@@ -5614,13 +5614,13 @@ define i16 @test328(i16* %ptr, i16 %val) {
 
 define i16 @test329(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test329:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB329_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB329_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB329_1
 ; PPC64LE-NEXT:  .LBB329_3:
@@ -5633,12 +5633,12 @@ define i16 @test329(i16* %ptr, i16 %val) {
 
 define i32 @test330(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test330:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB330_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB330_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB330_1
 ; PPC64LE-NEXT:  .LBB330_3:
@@ -5650,13 +5650,13 @@ define i32 @test330(i32* %ptr, i32 %val) {
 
 define i32 @test331(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test331:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB331_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB331_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB331_1
 ; PPC64LE-NEXT:  .LBB331_3:
@@ -5668,13 +5668,13 @@ define i32 @test331(i32* %ptr, i32 %val) {
 
 define i32 @test332(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test332:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB332_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB332_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB332_1
 ; PPC64LE-NEXT:  .LBB332_3:
@@ -5686,13 +5686,13 @@ define i32 @test332(i32* %ptr, i32 %val) {
 
 define i32 @test333(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test333:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB333_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB333_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB333_1
 ; PPC64LE-NEXT:  .LBB333_3:
@@ -5705,13 +5705,13 @@ define i32 @test333(i32* %ptr, i32 %val) {
 
 define i32 @test334(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test334:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB334_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB334_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB334_1
 ; PPC64LE-NEXT:  .LBB334_3:
@@ -5724,12 +5724,12 @@ define i32 @test334(i32* %ptr, i32 %val) {
 
 define i64 @test335(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test335:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB335_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB335_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB335_1
 ; PPC64LE-NEXT:  .LBB335_3:
@@ -5741,13 +5741,13 @@ define i64 @test335(i64* %ptr, i64 %val) {
 
 define i64 @test336(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test336:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB336_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpld 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB336_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB336_1
 ; PPC64LE-NEXT:  .LBB336_3:
@@ -5759,13 +5759,13 @@ define i64 @test336(i64* %ptr, i64 %val) {
 
 define i64 @test337(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test337:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB337_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB337_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB337_1
 ; PPC64LE-NEXT:  .LBB337_3:
@@ -5777,13 +5777,13 @@ define i64 @test337(i64* %ptr, i64 %val) {
 
 define i64 @test338(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test338:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB338_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB338_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB338_1
 ; PPC64LE-NEXT:  .LBB338_3:
@@ -5796,13 +5796,13 @@ define i64 @test338(i64* %ptr, i64 %val) {
 
 define i64 @test339(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test339:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB339_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB339_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB339_1
 ; PPC64LE-NEXT:  .LBB339_3:
@@ -5815,12 +5815,12 @@ define i64 @test339(i64* %ptr, i64 %val) {
 
 define i8 @test340(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test340:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB340_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB340_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") monotonic
@@ -5829,13 +5829,13 @@ define i8 @test340(i8* %ptr, i8 %val) {
 
 define i8 @test341(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test341:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB341_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB341_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") acquire
@@ -5844,13 +5844,13 @@ define i8 @test341(i8* %ptr, i8 %val) {
 
 define i8 @test342(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test342:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB342_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB342_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") release
@@ -5859,13 +5859,13 @@ define i8 @test342(i8* %ptr, i8 %val) {
 
 define i8 @test343(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test343:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB343_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB343_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -5875,13 +5875,13 @@ define i8 @test343(i8* %ptr, i8 %val) {
 
 define i8 @test344(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test344:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB344_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB344_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -5891,12 +5891,12 @@ define i8 @test344(i8* %ptr, i8 %val) {
 
 define i16 @test345(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test345:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB345_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB345_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") monotonic
@@ -5905,13 +5905,13 @@ define i16 @test345(i16* %ptr, i16 %val) {
 
 define i16 @test346(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test346:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB346_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB346_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") acquire
@@ -5920,13 +5920,13 @@ define i16 @test346(i16* %ptr, i16 %val) {
 
 define i16 @test347(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test347:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB347_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB347_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") release
@@ -5935,13 +5935,13 @@ define i16 @test347(i16* %ptr, i16 %val) {
 
 define i16 @test348(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test348:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB348_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB348_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -5951,13 +5951,13 @@ define i16 @test348(i16* %ptr, i16 %val) {
 
 define i16 @test349(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test349:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB349_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB349_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -5967,12 +5967,12 @@ define i16 @test349(i16* %ptr, i16 %val) {
 
 define i32 @test350(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test350:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB350_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB350_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") monotonic
@@ -5981,13 +5981,13 @@ define i32 @test350(i32* %ptr, i32 %val) {
 
 define i32 @test351(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test351:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB351_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB351_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") acquire
@@ -5996,13 +5996,13 @@ define i32 @test351(i32* %ptr, i32 %val) {
 
 define i32 @test352(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test352:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB352_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB352_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") release
@@ -6011,13 +6011,13 @@ define i32 @test352(i32* %ptr, i32 %val) {
 
 define i32 @test353(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test353:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB353_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB353_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6027,13 +6027,13 @@ define i32 @test353(i32* %ptr, i32 %val) {
 
 define i32 @test354(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test354:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB354_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB354_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6043,12 +6043,12 @@ define i32 @test354(i32* %ptr, i32 %val) {
 
 define i64 @test355(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test355:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB355_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB355_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") monotonic
@@ -6057,13 +6057,13 @@ define i64 @test355(i64* %ptr, i64 %val) {
 
 define i64 @test356(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test356:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB356_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB356_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") acquire
@@ -6072,13 +6072,13 @@ define i64 @test356(i64* %ptr, i64 %val) {
 
 define i64 @test357(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test357:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB357_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB357_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") release
@@ -6087,13 +6087,13 @@ define i64 @test357(i64* %ptr, i64 %val) {
 
 define i64 @test358(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test358:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB358_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB358_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6103,13 +6103,13 @@ define i64 @test358(i64* %ptr, i64 %val) {
 
 define i64 @test359(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test359:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB359_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB359_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6119,13 +6119,13 @@ define i64 @test359(i64* %ptr, i64 %val) {
 
 define i8 @test360(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test360:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB360_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB360_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") monotonic
@@ -6134,14 +6134,14 @@ define i8 @test360(i8* %ptr, i8 %val) {
 
 define i8 @test361(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test361:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB361_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB361_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") acquire
@@ -6150,14 +6150,14 @@ define i8 @test361(i8* %ptr, i8 %val) {
 
 define i8 @test362(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test362:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB362_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB362_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") release
@@ -6166,14 +6166,14 @@ define i8 @test362(i8* %ptr, i8 %val) {
 
 define i8 @test363(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test363:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB363_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB363_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6183,14 +6183,14 @@ define i8 @test363(i8* %ptr, i8 %val) {
 
 define i8 @test364(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test364:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB364_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB364_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6200,13 +6200,13 @@ define i8 @test364(i8* %ptr, i8 %val) {
 
 define i16 @test365(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test365:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB365_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB365_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") monotonic
@@ -6215,14 +6215,14 @@ define i16 @test365(i16* %ptr, i16 %val) {
 
 define i16 @test366(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test366:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB366_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB366_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") acquire
@@ -6231,14 +6231,14 @@ define i16 @test366(i16* %ptr, i16 %val) {
 
 define i16 @test367(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test367:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB367_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB367_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") release
@@ -6247,14 +6247,14 @@ define i16 @test367(i16* %ptr, i16 %val) {
 
 define i16 @test368(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test368:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB368_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB368_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6264,14 +6264,14 @@ define i16 @test368(i16* %ptr, i16 %val) {
 
 define i16 @test369(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test369:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB369_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB369_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6281,13 +6281,13 @@ define i16 @test369(i16* %ptr, i16 %val) {
 
 define i32 @test370(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test370:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB370_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB370_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") monotonic
@@ -6296,14 +6296,14 @@ define i32 @test370(i32* %ptr, i32 %val) {
 
 define i32 @test371(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test371:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB371_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB371_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") acquire
@@ -6312,14 +6312,14 @@ define i32 @test371(i32* %ptr, i32 %val) {
 
 define i32 @test372(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test372:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB372_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB372_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") release
@@ -6328,14 +6328,14 @@ define i32 @test372(i32* %ptr, i32 %val) {
 
 define i32 @test373(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test373:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB373_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB373_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6345,14 +6345,14 @@ define i32 @test373(i32* %ptr, i32 %val) {
 
 define i32 @test374(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test374:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB374_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB374_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6362,13 +6362,13 @@ define i32 @test374(i32* %ptr, i32 %val) {
 
 define i64 @test375(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test375:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB375_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB375_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") monotonic
@@ -6377,14 +6377,14 @@ define i64 @test375(i64* %ptr, i64 %val) {
 
 define i64 @test376(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test376:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB376_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    add 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB376_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") acquire
@@ -6393,14 +6393,14 @@ define i64 @test376(i64* %ptr, i64 %val) {
 
 define i64 @test377(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test377:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB377_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB377_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") release
@@ -6409,14 +6409,14 @@ define i64 @test377(i64* %ptr, i64 %val) {
 
 define i64 @test378(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test378:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB378_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB378_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6426,14 +6426,14 @@ define i64 @test378(i64* %ptr, i64 %val) {
 
 define i64 @test379(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test379:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB379_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    add 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB379_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6443,13 +6443,13 @@ define i64 @test379(i64* %ptr, i64 %val) {
 
 define i8 @test380(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test380:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB380_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB380_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") monotonic
@@ -6458,14 +6458,14 @@ define i8 @test380(i8* %ptr, i8 %val) {
 
 define i8 @test381(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test381:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB381_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB381_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acquire
@@ -6474,14 +6474,14 @@ define i8 @test381(i8* %ptr, i8 %val) {
 
 define i8 @test382(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test382:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB382_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB382_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") release
@@ -6490,14 +6490,14 @@ define i8 @test382(i8* %ptr, i8 %val) {
 
 define i8 @test383(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test383:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB383_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB383_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6507,14 +6507,14 @@ define i8 @test383(i8* %ptr, i8 %val) {
 
 define i8 @test384(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test384:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB384_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB384_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6524,13 +6524,13 @@ define i8 @test384(i8* %ptr, i8 %val) {
 
 define i16 @test385(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test385:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB385_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB385_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") monotonic
@@ -6539,14 +6539,14 @@ define i16 @test385(i16* %ptr, i16 %val) {
 
 define i16 @test386(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test386:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB386_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB386_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acquire
@@ -6555,14 +6555,14 @@ define i16 @test386(i16* %ptr, i16 %val) {
 
 define i16 @test387(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test387:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB387_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB387_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") release
@@ -6571,14 +6571,14 @@ define i16 @test387(i16* %ptr, i16 %val) {
 
 define i16 @test388(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test388:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB388_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB388_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6588,14 +6588,14 @@ define i16 @test388(i16* %ptr, i16 %val) {
 
 define i16 @test389(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test389:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB389_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB389_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6605,13 +6605,13 @@ define i16 @test389(i16* %ptr, i16 %val) {
 
 define i32 @test390(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test390:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB390_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB390_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") monotonic
@@ -6620,14 +6620,14 @@ define i32 @test390(i32* %ptr, i32 %val) {
 
 define i32 @test391(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test391:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB391_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    subf 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB391_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acquire
@@ -6636,14 +6636,14 @@ define i32 @test391(i32* %ptr, i32 %val) {
 
 define i32 @test392(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test392:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB392_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB392_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") release
@@ -6652,14 +6652,14 @@ define i32 @test392(i32* %ptr, i32 %val) {
 
 define i32 @test393(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test393:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB393_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB393_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6669,14 +6669,14 @@ define i32 @test393(i32* %ptr, i32 %val) {
 
 define i32 @test394(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test394:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB394_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    subf 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB394_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6686,13 +6686,13 @@ define i32 @test394(i32* %ptr, i32 %val) {
 
 define i64 @test395(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test395:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB395_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB395_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") monotonic
@@ -6701,14 +6701,14 @@ define i64 @test395(i64* %ptr, i64 %val) {
 
 define i64 @test396(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test396:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB396_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB396_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") acquire
@@ -6717,14 +6717,14 @@ define i64 @test396(i64* %ptr, i64 %val) {
 
 define i64 @test397(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test397:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB397_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB397_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") release
@@ -6733,14 +6733,14 @@ define i64 @test397(i64* %ptr, i64 %val) {
 
 define i64 @test398(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test398:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB398_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB398_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6750,14 +6750,14 @@ define i64 @test398(i64* %ptr, i64 %val) {
 
 define i64 @test399(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test399:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB399_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB399_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6767,13 +6767,13 @@ define i64 @test399(i64* %ptr, i64 %val) {
 
 define i8 @test400(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test400:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB400_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB400_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") monotonic
@@ -6782,14 +6782,14 @@ define i8 @test400(i8* %ptr, i8 %val) {
 
 define i8 @test401(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test401:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB401_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB401_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") acquire
@@ -6798,14 +6798,14 @@ define i8 @test401(i8* %ptr, i8 %val) {
 
 define i8 @test402(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test402:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB402_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB402_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") release
@@ -6814,14 +6814,14 @@ define i8 @test402(i8* %ptr, i8 %val) {
 
 define i8 @test403(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test403:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB403_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB403_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6831,14 +6831,14 @@ define i8 @test403(i8* %ptr, i8 %val) {
 
 define i8 @test404(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test404:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB404_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB404_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6848,13 +6848,13 @@ define i8 @test404(i8* %ptr, i8 %val) {
 
 define i16 @test405(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test405:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB405_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB405_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") monotonic
@@ -6863,14 +6863,14 @@ define i16 @test405(i16* %ptr, i16 %val) {
 
 define i16 @test406(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test406:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB406_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB406_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") acquire
@@ -6879,14 +6879,14 @@ define i16 @test406(i16* %ptr, i16 %val) {
 
 define i16 @test407(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test407:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB407_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB407_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") release
@@ -6895,14 +6895,14 @@ define i16 @test407(i16* %ptr, i16 %val) {
 
 define i16 @test408(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test408:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB408_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB408_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6912,14 +6912,14 @@ define i16 @test408(i16* %ptr, i16 %val) {
 
 define i16 @test409(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test409:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB409_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB409_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6929,13 +6929,13 @@ define i16 @test409(i16* %ptr, i16 %val) {
 
 define i32 @test410(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test410:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB410_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB410_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") monotonic
@@ -6944,14 +6944,14 @@ define i32 @test410(i32* %ptr, i32 %val) {
 
 define i32 @test411(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test411:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB411_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB411_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") acquire
@@ -6960,14 +6960,14 @@ define i32 @test411(i32* %ptr, i32 %val) {
 
 define i32 @test412(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test412:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB412_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB412_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") release
@@ -6976,14 +6976,14 @@ define i32 @test412(i32* %ptr, i32 %val) {
 
 define i32 @test413(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test413:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB413_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB413_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -6993,14 +6993,14 @@ define i32 @test413(i32* %ptr, i32 %val) {
 
 define i32 @test414(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test414:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB414_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB414_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7010,13 +7010,13 @@ define i32 @test414(i32* %ptr, i32 %val) {
 
 define i64 @test415(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test415:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB415_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB415_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") monotonic
@@ -7025,14 +7025,14 @@ define i64 @test415(i64* %ptr, i64 %val) {
 
 define i64 @test416(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test416:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB416_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    and 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB416_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") acquire
@@ -7041,14 +7041,14 @@ define i64 @test416(i64* %ptr, i64 %val) {
 
 define i64 @test417(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test417:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB417_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB417_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") release
@@ -7057,14 +7057,14 @@ define i64 @test417(i64* %ptr, i64 %val) {
 
 define i64 @test418(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test418:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB418_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB418_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7074,14 +7074,14 @@ define i64 @test418(i64* %ptr, i64 %val) {
 
 define i64 @test419(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test419:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB419_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    and 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB419_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7091,13 +7091,13 @@ define i64 @test419(i64* %ptr, i64 %val) {
 
 define i8 @test420(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test420:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB420_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB420_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") monotonic
@@ -7106,14 +7106,14 @@ define i8 @test420(i8* %ptr, i8 %val) {
 
 define i8 @test421(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test421:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB421_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB421_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") acquire
@@ -7122,14 +7122,14 @@ define i8 @test421(i8* %ptr, i8 %val) {
 
 define i8 @test422(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test422:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB422_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB422_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") release
@@ -7138,14 +7138,14 @@ define i8 @test422(i8* %ptr, i8 %val) {
 
 define i8 @test423(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test423:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB423_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB423_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7155,14 +7155,14 @@ define i8 @test423(i8* %ptr, i8 %val) {
 
 define i8 @test424(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test424:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB424_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB424_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7172,13 +7172,13 @@ define i8 @test424(i8* %ptr, i8 %val) {
 
 define i16 @test425(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test425:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB425_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB425_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") monotonic
@@ -7187,14 +7187,14 @@ define i16 @test425(i16* %ptr, i16 %val) {
 
 define i16 @test426(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test426:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB426_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB426_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") acquire
@@ -7203,14 +7203,14 @@ define i16 @test426(i16* %ptr, i16 %val) {
 
 define i16 @test427(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test427:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB427_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB427_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") release
@@ -7219,14 +7219,14 @@ define i16 @test427(i16* %ptr, i16 %val) {
 
 define i16 @test428(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test428:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB428_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB428_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7236,14 +7236,14 @@ define i16 @test428(i16* %ptr, i16 %val) {
 
 define i16 @test429(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test429:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB429_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB429_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7253,13 +7253,13 @@ define i16 @test429(i16* %ptr, i16 %val) {
 
 define i32 @test430(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test430:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB430_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB430_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") monotonic
@@ -7268,14 +7268,14 @@ define i32 @test430(i32* %ptr, i32 %val) {
 
 define i32 @test431(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test431:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB431_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB431_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") acquire
@@ -7284,14 +7284,14 @@ define i32 @test431(i32* %ptr, i32 %val) {
 
 define i32 @test432(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test432:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB432_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB432_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") release
@@ -7300,14 +7300,14 @@ define i32 @test432(i32* %ptr, i32 %val) {
 
 define i32 @test433(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test433:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB433_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB433_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7317,14 +7317,14 @@ define i32 @test433(i32* %ptr, i32 %val) {
 
 define i32 @test434(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test434:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB434_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB434_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7334,13 +7334,13 @@ define i32 @test434(i32* %ptr, i32 %val) {
 
 define i64 @test435(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test435:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB435_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB435_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") monotonic
@@ -7349,14 +7349,14 @@ define i64 @test435(i64* %ptr, i64 %val) {
 
 define i64 @test436(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test436:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB436_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    nand 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB436_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") acquire
@@ -7365,14 +7365,14 @@ define i64 @test436(i64* %ptr, i64 %val) {
 
 define i64 @test437(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test437:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB437_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB437_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") release
@@ -7381,14 +7381,14 @@ define i64 @test437(i64* %ptr, i64 %val) {
 
 define i64 @test438(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test438:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB438_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB438_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7398,14 +7398,14 @@ define i64 @test438(i64* %ptr, i64 %val) {
 
 define i64 @test439(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test439:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB439_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    nand 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB439_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7415,13 +7415,13 @@ define i64 @test439(i64* %ptr, i64 %val) {
 
 define i8 @test440(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test440:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB440_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB440_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") monotonic
@@ -7430,14 +7430,14 @@ define i8 @test440(i8* %ptr, i8 %val) {
 
 define i8 @test441(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test441:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB441_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB441_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") acquire
@@ -7446,14 +7446,14 @@ define i8 @test441(i8* %ptr, i8 %val) {
 
 define i8 @test442(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test442:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB442_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB442_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") release
@@ -7462,14 +7462,14 @@ define i8 @test442(i8* %ptr, i8 %val) {
 
 define i8 @test443(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test443:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB443_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB443_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7479,14 +7479,14 @@ define i8 @test443(i8* %ptr, i8 %val) {
 
 define i8 @test444(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test444:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB444_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB444_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7496,13 +7496,13 @@ define i8 @test444(i8* %ptr, i8 %val) {
 
 define i16 @test445(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test445:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB445_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB445_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") monotonic
@@ -7511,14 +7511,14 @@ define i16 @test445(i16* %ptr, i16 %val) {
 
 define i16 @test446(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test446:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB446_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB446_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") acquire
@@ -7527,14 +7527,14 @@ define i16 @test446(i16* %ptr, i16 %val) {
 
 define i16 @test447(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test447:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB447_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB447_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") release
@@ -7543,14 +7543,14 @@ define i16 @test447(i16* %ptr, i16 %val) {
 
 define i16 @test448(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test448:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB448_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB448_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7560,14 +7560,14 @@ define i16 @test448(i16* %ptr, i16 %val) {
 
 define i16 @test449(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test449:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB449_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB449_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7577,13 +7577,13 @@ define i16 @test449(i16* %ptr, i16 %val) {
 
 define i32 @test450(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test450:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB450_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB450_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") monotonic
@@ -7592,14 +7592,14 @@ define i32 @test450(i32* %ptr, i32 %val) {
 
 define i32 @test451(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test451:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB451_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB451_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") acquire
@@ -7608,14 +7608,14 @@ define i32 @test451(i32* %ptr, i32 %val) {
 
 define i32 @test452(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test452:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB452_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB452_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") release
@@ -7624,14 +7624,14 @@ define i32 @test452(i32* %ptr, i32 %val) {
 
 define i32 @test453(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test453:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB453_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB453_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7641,14 +7641,14 @@ define i32 @test453(i32* %ptr, i32 %val) {
 
 define i32 @test454(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test454:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB454_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB454_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7658,13 +7658,13 @@ define i32 @test454(i32* %ptr, i32 %val) {
 
 define i64 @test455(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test455:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB455_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB455_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") monotonic
@@ -7673,14 +7673,14 @@ define i64 @test455(i64* %ptr, i64 %val) {
 
 define i64 @test456(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test456:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB456_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    or 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB456_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") acquire
@@ -7689,14 +7689,14 @@ define i64 @test456(i64* %ptr, i64 %val) {
 
 define i64 @test457(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test457:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB457_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB457_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") release
@@ -7705,14 +7705,14 @@ define i64 @test457(i64* %ptr, i64 %val) {
 
 define i64 @test458(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test458:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB458_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB458_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7722,14 +7722,14 @@ define i64 @test458(i64* %ptr, i64 %val) {
 
 define i64 @test459(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test459:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB459_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    or 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB459_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7739,13 +7739,13 @@ define i64 @test459(i64* %ptr, i64 %val) {
 
 define i8 @test460(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test460:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB460_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB460_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") monotonic
@@ -7754,14 +7754,14 @@ define i8 @test460(i8* %ptr, i8 %val) {
 
 define i8 @test461(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test461:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB461_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB461_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") acquire
@@ -7770,14 +7770,14 @@ define i8 @test461(i8* %ptr, i8 %val) {
 
 define i8 @test462(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test462:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB462_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB462_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") release
@@ -7786,14 +7786,14 @@ define i8 @test462(i8* %ptr, i8 %val) {
 
 define i8 @test463(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test463:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB463_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB463_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7803,14 +7803,14 @@ define i8 @test463(i8* %ptr, i8 %val) {
 
 define i8 @test464(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test464:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB464_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB464_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7820,13 +7820,13 @@ define i8 @test464(i8* %ptr, i8 %val) {
 
 define i16 @test465(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test465:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB465_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB465_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") monotonic
@@ -7835,14 +7835,14 @@ define i16 @test465(i16* %ptr, i16 %val) {
 
 define i16 @test466(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test466:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB466_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB466_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") acquire
@@ -7851,14 +7851,14 @@ define i16 @test466(i16* %ptr, i16 %val) {
 
 define i16 @test467(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test467:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB467_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB467_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") release
@@ -7867,14 +7867,14 @@ define i16 @test467(i16* %ptr, i16 %val) {
 
 define i16 @test468(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test468:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB468_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB468_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7884,14 +7884,14 @@ define i16 @test468(i16* %ptr, i16 %val) {
 
 define i16 @test469(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test469:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB469_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB469_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7901,13 +7901,13 @@ define i16 @test469(i16* %ptr, i16 %val) {
 
 define i32 @test470(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test470:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB470_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB470_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") monotonic
@@ -7916,14 +7916,14 @@ define i32 @test470(i32* %ptr, i32 %val) {
 
 define i32 @test471(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test471:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB471_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB471_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") acquire
@@ -7932,14 +7932,14 @@ define i32 @test471(i32* %ptr, i32 %val) {
 
 define i32 @test472(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test472:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB472_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB472_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") release
@@ -7948,14 +7948,14 @@ define i32 @test472(i32* %ptr, i32 %val) {
 
 define i32 @test473(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test473:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB473_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB473_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7965,14 +7965,14 @@ define i32 @test473(i32* %ptr, i32 %val) {
 
 define i32 @test474(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test474:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB474_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB474_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -7982,13 +7982,13 @@ define i32 @test474(i32* %ptr, i32 %val) {
 
 define i64 @test475(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test475:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB475_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB475_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") monotonic
@@ -7997,14 +7997,14 @@ define i64 @test475(i64* %ptr, i64 %val) {
 
 define i64 @test476(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test476:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB476_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    xor 6, 4, 3
 ; PPC64LE-NEXT:    stdcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB476_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") acquire
@@ -8013,14 +8013,14 @@ define i64 @test476(i64* %ptr, i64 %val) {
 
 define i64 @test477(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test477:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB477_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB477_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") release
@@ -8029,14 +8029,14 @@ define i64 @test477(i64* %ptr, i64 %val) {
 
 define i64 @test478(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test478:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB478_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB478_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -8046,14 +8046,14 @@ define i64 @test478(i64* %ptr, i64 %val) {
 
 define i64 @test479(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test479:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB479_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    xor 6, 4, 5
 ; PPC64LE-NEXT:    stdcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB479_1
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
@@ -8063,13 +8063,13 @@ define i64 @test479(i64* %ptr, i64 %val) {
 
 define i8 @test480(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test480:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB480_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB480_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB480_1
 ; PPC64LE-NEXT:  .LBB480_3:
@@ -8081,14 +8081,14 @@ define i8 @test480(i8* %ptr, i8 %val) {
 
 define i8 @test481(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test481:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB481_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    extsb 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB481_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB481_1
 ; PPC64LE-NEXT:  .LBB481_3:
@@ -8100,14 +8100,14 @@ define i8 @test481(i8* %ptr, i8 %val) {
 
 define i8 @test482(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test482:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB482_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB482_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB482_1
 ; PPC64LE-NEXT:  .LBB482_3:
@@ -8119,14 +8119,14 @@ define i8 @test482(i8* %ptr, i8 %val) {
 
 define i8 @test483(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test483:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB483_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB483_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB483_1
 ; PPC64LE-NEXT:  .LBB483_3:
@@ -8139,14 +8139,14 @@ define i8 @test483(i8* %ptr, i8 %val) {
 
 define i8 @test484(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test484:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB484_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB484_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB484_1
 ; PPC64LE-NEXT:  .LBB484_3:
@@ -8159,13 +8159,13 @@ define i8 @test484(i8* %ptr, i8 %val) {
 
 define i16 @test485(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test485:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB485_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB485_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB485_1
 ; PPC64LE-NEXT:  .LBB485_3:
@@ -8177,14 +8177,14 @@ define i16 @test485(i16* %ptr, i16 %val) {
 
 define i16 @test486(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test486:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB486_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    extsh 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB486_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB486_1
 ; PPC64LE-NEXT:  .LBB486_3:
@@ -8196,14 +8196,14 @@ define i16 @test486(i16* %ptr, i16 %val) {
 
 define i16 @test487(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test487:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB487_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB487_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB487_1
 ; PPC64LE-NEXT:  .LBB487_3:
@@ -8215,14 +8215,14 @@ define i16 @test487(i16* %ptr, i16 %val) {
 
 define i16 @test488(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test488:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB488_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB488_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB488_1
 ; PPC64LE-NEXT:  .LBB488_3:
@@ -8235,14 +8235,14 @@ define i16 @test488(i16* %ptr, i16 %val) {
 
 define i16 @test489(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test489:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB489_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    ble 0, .LBB489_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB489_1
 ; PPC64LE-NEXT:  .LBB489_3:
@@ -8255,12 +8255,12 @@ define i16 @test489(i16* %ptr, i16 %val) {
 
 define i32 @test490(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test490:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB490_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB490_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB490_1
 ; PPC64LE-NEXT:  .LBB490_3:
@@ -8272,13 +8272,13 @@ define i32 @test490(i32* %ptr, i32 %val) {
 
 define i32 @test491(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test491:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB491_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB491_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB491_1
 ; PPC64LE-NEXT:  .LBB491_3:
@@ -8290,13 +8290,13 @@ define i32 @test491(i32* %ptr, i32 %val) {
 
 define i32 @test492(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test492:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB492_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB492_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB492_1
 ; PPC64LE-NEXT:  .LBB492_3:
@@ -8308,13 +8308,13 @@ define i32 @test492(i32* %ptr, i32 %val) {
 
 define i32 @test493(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test493:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB493_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB493_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB493_1
 ; PPC64LE-NEXT:  .LBB493_3:
@@ -8327,13 +8327,13 @@ define i32 @test493(i32* %ptr, i32 %val) {
 
 define i32 @test494(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test494:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB494_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB494_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB494_1
 ; PPC64LE-NEXT:  .LBB494_3:
@@ -8346,12 +8346,12 @@ define i32 @test494(i32* %ptr, i32 %val) {
 
 define i64 @test495(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test495:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB495_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB495_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB495_1
 ; PPC64LE-NEXT:  .LBB495_3:
@@ -8363,13 +8363,13 @@ define i64 @test495(i64* %ptr, i64 %val) {
 
 define i64 @test496(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test496:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB496_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpd 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB496_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB496_1
 ; PPC64LE-NEXT:  .LBB496_3:
@@ -8381,13 +8381,13 @@ define i64 @test496(i64* %ptr, i64 %val) {
 
 define i64 @test497(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test497:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB497_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB497_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB497_1
 ; PPC64LE-NEXT:  .LBB497_3:
@@ -8399,13 +8399,13 @@ define i64 @test497(i64* %ptr, i64 %val) {
 
 define i64 @test498(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test498:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB498_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB498_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB498_1
 ; PPC64LE-NEXT:  .LBB498_3:
@@ -8418,13 +8418,13 @@ define i64 @test498(i64* %ptr, i64 %val) {
 
 define i64 @test499(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test499:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB499_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB499_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB499_1
 ; PPC64LE-NEXT:  .LBB499_3:
@@ -8437,13 +8437,13 @@ define i64 @test499(i64* %ptr, i64 %val) {
 
 define i8 @test500(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test500:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB500_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB500_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB500_1
 ; PPC64LE-NEXT:  .LBB500_3:
@@ -8455,14 +8455,14 @@ define i8 @test500(i8* %ptr, i8 %val) {
 
 define i8 @test501(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test501:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB501_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    extsb 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB501_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB501_1
 ; PPC64LE-NEXT:  .LBB501_3:
@@ -8474,14 +8474,14 @@ define i8 @test501(i8* %ptr, i8 %val) {
 
 define i8 @test502(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test502:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB502_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB502_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB502_1
 ; PPC64LE-NEXT:  .LBB502_3:
@@ -8493,14 +8493,14 @@ define i8 @test502(i8* %ptr, i8 %val) {
 
 define i8 @test503(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test503:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB503_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB503_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB503_1
 ; PPC64LE-NEXT:  .LBB503_3:
@@ -8513,14 +8513,14 @@ define i8 @test503(i8* %ptr, i8 %val) {
 
 define i8 @test504(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test504:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB504_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB504_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB504_1
 ; PPC64LE-NEXT:  .LBB504_3:
@@ -8533,13 +8533,13 @@ define i8 @test504(i8* %ptr, i8 %val) {
 
 define i16 @test505(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test505:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB505_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB505_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB505_1
 ; PPC64LE-NEXT:  .LBB505_3:
@@ -8551,14 +8551,14 @@ define i16 @test505(i16* %ptr, i16 %val) {
 
 define i16 @test506(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test506:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB506_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    extsh 6, 3
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB506_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB506_1
 ; PPC64LE-NEXT:  .LBB506_3:
@@ -8570,14 +8570,14 @@ define i16 @test506(i16* %ptr, i16 %val) {
 
 define i16 @test507(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test507:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB507_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB507_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB507_1
 ; PPC64LE-NEXT:  .LBB507_3:
@@ -8589,14 +8589,14 @@ define i16 @test507(i16* %ptr, i16 %val) {
 
 define i16 @test508(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test508:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB508_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB508_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB508_1
 ; PPC64LE-NEXT:  .LBB508_3:
@@ -8609,14 +8609,14 @@ define i16 @test508(i16* %ptr, i16 %val) {
 
 define i16 @test509(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test509:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB509_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 5
 ; PPC64LE-NEXT:    cmpw 4, 6
 ; PPC64LE-NEXT:    bge 0, .LBB509_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB509_1
 ; PPC64LE-NEXT:  .LBB509_3:
@@ -8629,12 +8629,12 @@ define i16 @test509(i16* %ptr, i16 %val) {
 
 define i32 @test510(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test510:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB510_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB510_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB510_1
 ; PPC64LE-NEXT:  .LBB510_3:
@@ -8646,13 +8646,13 @@ define i32 @test510(i32* %ptr, i32 %val) {
 
 define i32 @test511(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test511:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB511_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB511_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB511_1
 ; PPC64LE-NEXT:  .LBB511_3:
@@ -8664,13 +8664,13 @@ define i32 @test511(i32* %ptr, i32 %val) {
 
 define i32 @test512(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test512:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB512_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB512_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB512_1
 ; PPC64LE-NEXT:  .LBB512_3:
@@ -8682,13 +8682,13 @@ define i32 @test512(i32* %ptr, i32 %val) {
 
 define i32 @test513(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test513:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB513_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB513_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB513_1
 ; PPC64LE-NEXT:  .LBB513_3:
@@ -8701,13 +8701,13 @@ define i32 @test513(i32* %ptr, i32 %val) {
 
 define i32 @test514(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test514:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB514_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB514_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB514_1
 ; PPC64LE-NEXT:  .LBB514_3:
@@ -8720,12 +8720,12 @@ define i32 @test514(i32* %ptr, i32 %val) {
 
 define i64 @test515(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test515:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB515_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB515_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB515_1
 ; PPC64LE-NEXT:  .LBB515_3:
@@ -8737,13 +8737,13 @@ define i64 @test515(i64* %ptr, i64 %val) {
 
 define i64 @test516(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test516:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB516_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpd 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB516_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB516_1
 ; PPC64LE-NEXT:  .LBB516_3:
@@ -8755,13 +8755,13 @@ define i64 @test516(i64* %ptr, i64 %val) {
 
 define i64 @test517(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test517:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB517_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB517_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB517_1
 ; PPC64LE-NEXT:  .LBB517_3:
@@ -8773,13 +8773,13 @@ define i64 @test517(i64* %ptr, i64 %val) {
 
 define i64 @test518(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test518:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB518_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB518_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB518_1
 ; PPC64LE-NEXT:  .LBB518_3:
@@ -8792,13 +8792,13 @@ define i64 @test518(i64* %ptr, i64 %val) {
 
 define i64 @test519(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test519:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB519_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpd 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB519_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB519_1
 ; PPC64LE-NEXT:  .LBB519_3:
@@ -8811,12 +8811,12 @@ define i64 @test519(i64* %ptr, i64 %val) {
 
 define i8 @test520(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test520:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB520_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB520_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB520_1
 ; PPC64LE-NEXT:  .LBB520_3:
@@ -8828,13 +8828,13 @@ define i8 @test520(i8* %ptr, i8 %val) {
 
 define i8 @test521(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test521:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB521_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB521_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB521_1
 ; PPC64LE-NEXT:  .LBB521_3:
@@ -8846,13 +8846,13 @@ define i8 @test521(i8* %ptr, i8 %val) {
 
 define i8 @test522(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test522:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB522_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB522_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB522_1
 ; PPC64LE-NEXT:  .LBB522_3:
@@ -8864,13 +8864,13 @@ define i8 @test522(i8* %ptr, i8 %val) {
 
 define i8 @test523(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test523:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB523_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB523_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB523_1
 ; PPC64LE-NEXT:  .LBB523_3:
@@ -8883,13 +8883,13 @@ define i8 @test523(i8* %ptr, i8 %val) {
 
 define i8 @test524(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test524:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB524_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB524_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB524_1
 ; PPC64LE-NEXT:  .LBB524_3:
@@ -8902,12 +8902,12 @@ define i8 @test524(i8* %ptr, i8 %val) {
 
 define i16 @test525(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test525:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB525_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB525_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB525_1
 ; PPC64LE-NEXT:  .LBB525_3:
@@ -8919,13 +8919,13 @@ define i16 @test525(i16* %ptr, i16 %val) {
 
 define i16 @test526(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test526:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB526_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB526_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB526_1
 ; PPC64LE-NEXT:  .LBB526_3:
@@ -8937,13 +8937,13 @@ define i16 @test526(i16* %ptr, i16 %val) {
 
 define i16 @test527(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test527:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB527_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB527_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB527_1
 ; PPC64LE-NEXT:  .LBB527_3:
@@ -8955,13 +8955,13 @@ define i16 @test527(i16* %ptr, i16 %val) {
 
 define i16 @test528(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test528:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB528_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB528_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB528_1
 ; PPC64LE-NEXT:  .LBB528_3:
@@ -8974,13 +8974,13 @@ define i16 @test528(i16* %ptr, i16 %val) {
 
 define i16 @test529(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test529:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB529_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB529_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB529_1
 ; PPC64LE-NEXT:  .LBB529_3:
@@ -8993,12 +8993,12 @@ define i16 @test529(i16* %ptr, i16 %val) {
 
 define i32 @test530(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test530:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB530_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB530_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB530_1
 ; PPC64LE-NEXT:  .LBB530_3:
@@ -9010,13 +9010,13 @@ define i32 @test530(i32* %ptr, i32 %val) {
 
 define i32 @test531(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test531:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB531_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB531_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB531_1
 ; PPC64LE-NEXT:  .LBB531_3:
@@ -9028,13 +9028,13 @@ define i32 @test531(i32* %ptr, i32 %val) {
 
 define i32 @test532(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test532:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB532_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB532_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB532_1
 ; PPC64LE-NEXT:  .LBB532_3:
@@ -9046,13 +9046,13 @@ define i32 @test532(i32* %ptr, i32 %val) {
 
 define i32 @test533(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test533:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB533_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB533_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB533_1
 ; PPC64LE-NEXT:  .LBB533_3:
@@ -9065,13 +9065,13 @@ define i32 @test533(i32* %ptr, i32 %val) {
 
 define i32 @test534(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test534:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB534_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB534_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB534_1
 ; PPC64LE-NEXT:  .LBB534_3:
@@ -9084,12 +9084,12 @@ define i32 @test534(i32* %ptr, i32 %val) {
 
 define i64 @test535(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test535:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB535_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB535_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB535_1
 ; PPC64LE-NEXT:  .LBB535_3:
@@ -9101,13 +9101,13 @@ define i64 @test535(i64* %ptr, i64 %val) {
 
 define i64 @test536(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test536:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB536_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpld 4, 3
 ; PPC64LE-NEXT:    ble 0, .LBB536_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB536_1
 ; PPC64LE-NEXT:  .LBB536_3:
@@ -9119,13 +9119,13 @@ define i64 @test536(i64* %ptr, i64 %val) {
 
 define i64 @test537(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test537:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB537_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB537_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB537_1
 ; PPC64LE-NEXT:  .LBB537_3:
@@ -9137,13 +9137,13 @@ define i64 @test537(i64* %ptr, i64 %val) {
 
 define i64 @test538(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test538:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB538_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB538_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB538_1
 ; PPC64LE-NEXT:  .LBB538_3:
@@ -9156,13 +9156,13 @@ define i64 @test538(i64* %ptr, i64 %val) {
 
 define i64 @test539(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test539:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB539_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    ble 0, .LBB539_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB539_1
 ; PPC64LE-NEXT:  .LBB539_3:
@@ -9175,12 +9175,12 @@ define i64 @test539(i64* %ptr, i64 %val) {
 
 define i8 @test540(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test540:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB540_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB540_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB540_1
 ; PPC64LE-NEXT:  .LBB540_3:
@@ -9192,13 +9192,13 @@ define i8 @test540(i8* %ptr, i8 %val) {
 
 define i8 @test541(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test541:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB541_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB541_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB541_1
 ; PPC64LE-NEXT:  .LBB541_3:
@@ -9210,13 +9210,13 @@ define i8 @test541(i8* %ptr, i8 %val) {
 
 define i8 @test542(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test542:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB542_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB542_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB542_1
 ; PPC64LE-NEXT:  .LBB542_3:
@@ -9228,13 +9228,13 @@ define i8 @test542(i8* %ptr, i8 %val) {
 
 define i8 @test543(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test543:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB543_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB543_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB543_1
 ; PPC64LE-NEXT:  .LBB543_3:
@@ -9247,13 +9247,13 @@ define i8 @test543(i8* %ptr, i8 %val) {
 
 define i8 @test544(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test544:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB544_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB544_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB544_1
 ; PPC64LE-NEXT:  .LBB544_3:
@@ -9266,12 +9266,12 @@ define i8 @test544(i8* %ptr, i8 %val) {
 
 define i16 @test545(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test545:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB545_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB545_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB545_1
 ; PPC64LE-NEXT:  .LBB545_3:
@@ -9283,13 +9283,13 @@ define i16 @test545(i16* %ptr, i16 %val) {
 
 define i16 @test546(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test546:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB546_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB546_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB546_1
 ; PPC64LE-NEXT:  .LBB546_3:
@@ -9301,13 +9301,13 @@ define i16 @test546(i16* %ptr, i16 %val) {
 
 define i16 @test547(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test547:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB547_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB547_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB547_1
 ; PPC64LE-NEXT:  .LBB547_3:
@@ -9319,13 +9319,13 @@ define i16 @test547(i16* %ptr, i16 %val) {
 
 define i16 @test548(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test548:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB548_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB548_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB548_1
 ; PPC64LE-NEXT:  .LBB548_3:
@@ -9338,13 +9338,13 @@ define i16 @test548(i16* %ptr, i16 %val) {
 
 define i16 @test549(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test549:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB549_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB549_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB549_1
 ; PPC64LE-NEXT:  .LBB549_3:
@@ -9357,12 +9357,12 @@ define i16 @test549(i16* %ptr, i16 %val) {
 
 define i32 @test550(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test550:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB550_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB550_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB550_1
 ; PPC64LE-NEXT:  .LBB550_3:
@@ -9374,13 +9374,13 @@ define i32 @test550(i32* %ptr, i32 %val) {
 
 define i32 @test551(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test551:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB551_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
 ; PPC64LE-NEXT:    cmplw 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB551_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB551_1
 ; PPC64LE-NEXT:  .LBB551_3:
@@ -9392,13 +9392,13 @@ define i32 @test551(i32* %ptr, i32 %val) {
 
 define i32 @test552(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test552:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB552_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB552_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB552_1
 ; PPC64LE-NEXT:  .LBB552_3:
@@ -9410,13 +9410,13 @@ define i32 @test552(i32* %ptr, i32 %val) {
 
 define i32 @test553(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test553:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB553_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB553_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB553_1
 ; PPC64LE-NEXT:  .LBB553_3:
@@ -9429,13 +9429,13 @@ define i32 @test553(i32* %ptr, i32 %val) {
 
 define i32 @test554(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test554:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB554_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
 ; PPC64LE-NEXT:    cmplw 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB554_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB554_1
 ; PPC64LE-NEXT:  .LBB554_3:
@@ -9448,12 +9448,12 @@ define i32 @test554(i32* %ptr, i32 %val) {
 
 define i64 @test555(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test555:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB555_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB555_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB555_1
 ; PPC64LE-NEXT:  .LBB555_3:
@@ -9465,13 +9465,13 @@ define i64 @test555(i64* %ptr, i64 %val) {
 
 define i64 @test556(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test556:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB556_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
 ; PPC64LE-NEXT:    cmpld 4, 3
 ; PPC64LE-NEXT:    bge 0, .LBB556_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB556_1
 ; PPC64LE-NEXT:  .LBB556_3:
@@ -9483,13 +9483,13 @@ define i64 @test556(i64* %ptr, i64 %val) {
 
 define i64 @test557(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test557:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB557_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB557_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB557_1
 ; PPC64LE-NEXT:  .LBB557_3:
@@ -9501,13 +9501,13 @@ define i64 @test557(i64* %ptr, i64 %val) {
 
 define i64 @test558(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test558:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB558_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB558_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB558_1
 ; PPC64LE-NEXT:  .LBB558_3:
@@ -9520,13 +9520,13 @@ define i64 @test558(i64* %ptr, i64 %val) {
 
 define i64 @test559(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test559:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB559_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
 ; PPC64LE-NEXT:    cmpld 4, 5
 ; PPC64LE-NEXT:    bge 0, .LBB559_3
-; PPC64LE-NEXT:  # BB#2:
+; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB559_1
 ; PPC64LE-NEXT:  .LBB559_3:
@@ -9540,7 +9540,7 @@ define i64 @test559(i64* %ptr, i64 %val) {
 ; The second load should never be scheduled before isync.
 define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) {
 ; PPC64LE-LABEL: test_ordering0:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwz 4, 0(3)
 ; PPC64LE-NEXT:    cmpd 7, 4, 4
 ; PPC64LE-NEXT:    bne- 7, .+4
@@ -9557,7 +9557,7 @@ define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) {
 ; The second store should never be scheduled before isync.
 define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) {
 ; PPC64LE-LABEL: test_ordering1:
-; PPC64LE:       # BB#0:
+; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwz 3, 0(3)
 ; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
diff --git a/test/CodeGen/PowerPC/branch_coalesce.ll b/test/CodeGen/PowerPC/branch_coalesce.ll
index 007eef27b2d..a57dec111bc 100644
--- a/test/CodeGen/PowerPC/branch_coalesce.ll
+++ b/test/CodeGen/PowerPC/branch_coalesce.ll
@@ -23,10 +23,10 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
 ; CHECK: blr
 
 ; CHECK-NOCOALESCE-LABEL: testBranchCoal:
-; CHECK-NOCOALESCE:       # BB#0: # %entry
+; CHECK-NOCOALESCE:       # %bb.0: # %entry
 ; CHECK-NOCOALESCE-NEXT:    cmplwi 0, 6, 0
 ; CHECK-NOCOALESCE-NEXT:    bne 0, .LBB0_5
-; CHECK-NOCOALESCE-NEXT:  # BB#1: # %entry
+; CHECK-NOCOALESCE-NEXT:  # %bb.1: # %entry
 ; CHECK-NOCOALESCE-NEXT:    bne 0, .LBB0_6
 ; CHECK-NOCOALESCE-NEXT:  .LBB0_2: # %entry
 ; CHECK-NOCOALESCE-NEXT:    beq 0, .LBB0_4
diff --git a/test/CodeGen/PowerPC/fabs.ll b/test/CodeGen/PowerPC/fabs.ll
index c8cbd00b4dc..369803af979 100644
--- a/test/CodeGen/PowerPC/fabs.ll
+++ b/test/CodeGen/PowerPC/fabs.ll
@@ -2,7 +2,7 @@
 
 define double @fabs(double %f) {
 ; CHECK-LABEL: fabs:
-; CHECK:       ; BB#0:
+; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    fabs f1, f1
 ; CHECK-NEXT:    blr
 ;
@@ -12,7 +12,7 @@ define double @fabs(double %f) {
 
 define float @bitcast_fabs(float %x) {
 ; CHECK-LABEL: bitcast_fabs:
-; CHECK:       ; BB#0:
+; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    stfs f1, -8(r1)
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    nop
diff --git a/test/CodeGen/PowerPC/fma-aggr-FMF.ll b/test/CodeGen/PowerPC/fma-aggr-FMF.ll
index 8e97115bd1f..e861c9df37a 100644
--- a/test/CodeGen/PowerPC/fma-aggr-FMF.ll
+++ b/test/CodeGen/PowerPC/fma-aggr-FMF.ll
@@ -3,7 +3,7 @@
 
 define float @can_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) {
 ; CHECK-LABEL: can_fma_with_fewer_uses:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsmulsp 0, 1, 2
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    xsmaddasp 1, 3, 4
@@ -21,7 +21,7 @@ define float @can_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4
 ; around beside the fma.
 define float @no_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) {
 ; CHECK-LABEL: no_fma_with_fewer_uses:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsmulsp 0, 3, 4
 ; CHECK-NEXT:    xsmulsp 13, 1, 2
 ; CHECK-NEXT:    xsmaddasp 0, 1, 2
diff --git a/test/CodeGen/PowerPC/fp64-to-int16.ll b/test/CodeGen/PowerPC/fp64-to-int16.ll
index 0c5274d9426..360a9866518 100644
--- a/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ b/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64le--linux-gnu"
 
 define i1 @Test(double %a) {
 ; CHECK-LABEL: Test:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws 1, 1
 ; CHECK-NEXT:    mfvsrwz 3, 1
 ; CHECK-NEXT:    xori 3, 3, 65534
diff --git a/test/CodeGen/PowerPC/hello-reloc.s b/test/CodeGen/PowerPC/hello-reloc.s
index bbf1e7cacbd..66bc9a84f5c 100644
--- a/test/CodeGen/PowerPC/hello-reloc.s
+++ b/test/CodeGen/PowerPC/hello-reloc.s
@@ -11,7 +11,7 @@
 	.globl	_main
 	.align	4
 _main:                                  ; @main
-; BB#0:                                 ; %entry
+; %bb.0:                                ; %entry
 	mflr r0
 	stw r31, -4(r1)
 	stw r0, 8(r1)
diff --git a/test/CodeGen/PowerPC/licm-remat.ll b/test/CodeGen/PowerPC/licm-remat.ll
index cbd1af62b84..393c56bcb86 100644
--- a/test/CodeGen/PowerPC/licm-remat.ll
+++ b/test/CodeGen/PowerPC/licm-remat.ll
@@ -18,7 +18,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture r
 
 define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) {
 ; CHECK-LABEL: ZN6snappyDecompressor_:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:       addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
 ; CHECK-DAG:   addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l
 ; CHECK-DAG:   addis 4, 2, _ZN6snappy8internalL10char_tableE@toc@ha
diff --git a/test/CodeGen/PowerPC/licm-tocReg.ll b/test/CodeGen/PowerPC/licm-tocReg.ll
index 824d554991a..efbec9091a5 100644
--- a/test/CodeGen/PowerPC/licm-tocReg.ll
+++ b/test/CodeGen/PowerPC/licm-tocReg.ll
@@ -64,7 +64,7 @@
 
 define signext i32 @test(i32 (i32)* nocapture %FP) local_unnamed_addr #0 {
 ; CHECK-LABEL: test:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 6, 2, .LC0@toc@ha
 ; CHECK-NEXT:    addis 4, 2, .LC1@toc@ha
 ; CHECK-NEXT:    ld 5, .LC1@toc@l(4)
diff --git a/test/CodeGen/PowerPC/logic-ops-on-compares.ll b/test/CodeGen/PowerPC/logic-ops-on-compares.ll
index e448afd03ea..b1b26f0ab76 100644
--- a/test/CodeGen/PowerPC/logic-ops-on-compares.ll
+++ b/test/CodeGen/PowerPC/logic-ops-on-compares.ll
@@ -43,11 +43,11 @@ return:                                           ; preds = %if.end, %if.then
 
 define void @neg_truncate_i32_eq(i32 *%ptr) {
 ; CHECK-LABEL: neg_truncate_i32_eq:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz r3, 0(r3)
 ; CHECK-NEXT:    rldicl. r3, r3, 0, 63
 ; CHECK-NEXT:    bclr 12, eq, 0
-; CHECK-NEXT:  # BB#1: # %if.end29.thread136
+; CHECK-NEXT:  # %bb.1: # %if.end29.thread136
 entry:
   %0 = load i32, i32* %ptr, align 4
   %rem17127 = and i32 %0, 1
@@ -101,11 +101,11 @@ return:                                           ; preds = %if.end, %if.then
 
 define void @neg_truncate_i64_eq(i64 *%ptr) {
 ; CHECK-LABEL: neg_truncate_i64_eq:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    rldicl. r3, r3, 0, 63
 ; CHECK-NEXT:    bclr 12, eq, 0
-; CHECK-NEXT:  # BB#1: # %if.end29.thread136
+; CHECK-NEXT:  # %bb.1: # %if.end29.thread136
 entry:
   %0 = load i64, i64* %ptr, align 4
   %rem17127 = and i64 %0, 1
@@ -161,11 +161,11 @@ return:                                           ; preds = %if.end, %if.then
 
 define void @neg_truncate_i64_ne(i64 *%ptr) {
 ; CHECK-LABEL: neg_truncate_i64_ne:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    andi. r3, r3, 1
 ; CHECK-NEXT:    bclr 12, gt, 0
-; CHECK-NEXT:  # BB#1: # %if.end29.thread136
+; CHECK-NEXT:  # %bb.1: # %if.end29.thread136
 entry:
   %0 = load i64, i64* %ptr, align 4
   %rem17127 = and i64 %0, 1
diff --git a/test/CodeGen/PowerPC/machine-combiner.ll b/test/CodeGen/PowerPC/machine-combiner.ll
index e026017710e..c7337e3637e 100644
--- a/test/CodeGen/PowerPC/machine-combiner.ll
+++ b/test/CodeGen/PowerPC/machine-combiner.ll
@@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-LABEL: reassociate_adds1:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK:       fadds [[REG0:[0-9]+]], 1, 2
 ; CHECK:       fadds [[REG1:[0-9]+]], 3, 4
 ; CHECK:       fadds 1, [[REG0]], [[REG1]]
@@ -22,7 +22,7 @@ define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) {
 
 define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-LABEL: reassociate_adds2:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK:       fadds [[REG0:[0-9]+]], 1, 2
 ; CHECK:       fadds [[REG1:[0-9]+]], 3, 4
 ; CHECK:       fadds 1, [[REG0]], [[REG1]]
@@ -36,7 +36,7 @@ define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) {
 
 define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-LABEL: reassociate_adds3:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK:       fadds [[REG0:[0-9]+]], 1, 2
 ; CHECK:       fadds [[REG1:[0-9]+]], 3, 4
 ; CHECK:       fadds 1, [[REG0]], [[REG1]]
@@ -50,7 +50,7 @@ define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {
 
 define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-LABEL: reassociate_adds4:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK:       fadds [[REG0:[0-9]+]], 1, 2
 ; CHECK:       fadds [[REG1:[0-9]+]], 3, 4
 ; CHECK:       fadds 1, [[REG0]], [[REG1]]
@@ -67,7 +67,7 @@ define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
 
 define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {
 ; CHECK-LABEL: reassociate_adds5:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK:       fadds [[REG12:[0-9]+]], 5, 6
 ; CHECK:       fadds [[REG0:[0-9]+]], 1, 2
 ; CHECK:       fadds [[REG11:[0-9]+]], 3, 4
@@ -91,7 +91,7 @@ define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, floa
 
 define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-LABEL: vector_reassociate_adds1:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-QPX:       qvfadds [[REG0:[0-9]+]], 1, 2
 ; CHECK-QPX:       qvfadds [[REG1:[0-9]+]], 3, 4
 ; CHECK-QPX:       qvfadds 1, [[REG0]], [[REG1]]
@@ -108,7 +108,7 @@ define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <
 
 define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-LABEL: vector_reassociate_adds2:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-QPX:       qvfadds [[REG0:[0-9]+]], 1, 2
 ; CHECK-QPX:       qvfadds [[REG1:[0-9]+]], 3, 4
 ; CHECK-QPX:       qvfadds 1, [[REG0]], [[REG1]]
@@ -125,7 +125,7 @@ define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <
 
 define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-LABEL: vector_reassociate_adds3:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-QPX:       qvfadds [[REG0:[0-9]+]], 1, 2
 ; CHECK-QPX:       qvfadds [[REG1:[0-9]+]], 3, 4
 ; CHECK-QPX:       qvfadds 1, [[REG0]], [[REG1]]
@@ -142,7 +142,7 @@ define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <
 
 define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-LABEL: vector_reassociate_adds4:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-QPX:       qvfadds [[REG0:[0-9]+]], 1, 2
 ; CHECK-QPX:       qvfadds [[REG1:[0-9]+]], 3, 4
 ; CHECK-QPX:       qvfadds 1, [[REG0]], [[REG1]]
diff --git a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
index e91b9acaee0..3bfc0de1b87 100644
--- a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
+++ b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -17,7 +17,7 @@ declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_add
 ; Check 4 bytes - requires 1 load for each param.
 define signext i32 @zeroEqualityTest02(i8* %x, i8* %y) {
 ; CHECK-LABEL: zeroEqualityTest02:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lwz 3, 0(3)
 ; CHECK-NEXT:    lwz 4, 0(4)
 ; CHECK-NEXT:    xor 3, 3, 4
@@ -34,12 +34,12 @@ define signext i32 @zeroEqualityTest02(i8* %x, i8* %y) {
 ; Check 16 bytes - requires 2 loads for each param (or use vectors?).
 define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) {
 ; CHECK-LABEL: zeroEqualityTest01:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ld 5, 0(3)
 ; CHECK-NEXT:    ld 6, 0(4)
 ; CHECK-NEXT:    cmpld 5, 6
 ; CHECK-NEXT:    bne 0, .LBB1_2
-; CHECK-NEXT:  # BB#1: # %loadbb1
+; CHECK-NEXT:  # %bb.1: # %loadbb1
 ; CHECK-NEXT:    ld 3, 8(3)
 ; CHECK-NEXT:    ld 4, 8(4)
 ; CHECK-NEXT:    cmpld 3, 4
@@ -59,17 +59,17 @@ define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) {
 ; Check 7 bytes - requires 3 loads for each param.
 define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) {
 ; CHECK-LABEL: zeroEqualityTest03:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lwz 5, 0(3)
 ; CHECK-NEXT:    lwz 6, 0(4)
 ; CHECK-NEXT:    cmplw 5, 6
 ; CHECK-NEXT:    bne 0, .LBB2_3
-; CHECK-NEXT:  # BB#1: # %loadbb1
+; CHECK-NEXT:  # %bb.1: # %loadbb1
 ; CHECK-NEXT:    lhz 5, 4(3)
 ; CHECK-NEXT:    lhz 6, 4(4)
 ; CHECK-NEXT:    cmplw 5, 6
 ; CHECK-NEXT:    bne 0, .LBB2_3
-; CHECK-NEXT:  # BB#2: # %loadbb2
+; CHECK-NEXT:  # %bb.2: # %loadbb2
 ; CHECK-NEXT:    lbz 3, 6(3)
 ; CHECK-NEXT:    lbz 4, 6(4)
 ; CHECK-NEXT:    cmplw 3, 4
@@ -89,7 +89,7 @@ define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) {
 ; Validate with > 0
 define signext i32 @zeroEqualityTest04() {
 ; CHECK-LABEL: zeroEqualityTest04:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LzeroEqualityTest02.buffer1@toc@ha
 ; CHECK-NEXT:    addis 4, 2, .LzeroEqualityTest02.buffer2@toc@ha
 ; CHECK-NEXT:    addi 6, 3, .LzeroEqualityTest02.buffer1@toc@l
@@ -98,7 +98,7 @@ define signext i32 @zeroEqualityTest04() {
 ; CHECK-NEXT:    ldbrx 4, 0, 5
 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    bne 0, .LBB3_2
-; CHECK-NEXT:  # BB#1: # %loadbb1
+; CHECK-NEXT:  # %bb.1: # %loadbb1
 ; CHECK-NEXT:    li 4, 8
 ; CHECK-NEXT:    ldbrx 3, 6, 4
 ; CHECK-NEXT:    ldbrx 4, 5, 4
@@ -125,7 +125,7 @@ define signext i32 @zeroEqualityTest04() {
 ; Validate with < 0
 define signext i32 @zeroEqualityTest05() {
 ; CHECK-LABEL: zeroEqualityTest05:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis 3, 2, .LzeroEqualityTest03.buffer1@toc@ha
 ; CHECK-NEXT:    addis 4, 2, .LzeroEqualityTest03.buffer2@toc@ha
 ; CHECK-NEXT:    addi 6, 3, .LzeroEqualityTest03.buffer1@toc@l
@@ -134,7 +134,7 @@ define signext i32 @zeroEqualityTest05() {
 ; CHECK-NEXT:    ldbrx 4, 0, 5
 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    bne 0, .LBB4_2
-; CHECK-NEXT:  # BB#1: # %loadbb1
+; CHECK-NEXT:  # %bb.1: # %loadbb1
 ; CHECK-NEXT:    li 4, 8
 ; CHECK-NEXT:    ldbrx 3, 6, 4
 ; CHECK-NEXT:    ldbrx 4, 5, 4
@@ -160,7 +160,7 @@ define signext i32 @zeroEqualityTest05() {
 ; Validate with memcmp()?:
 define signext i32 @equalityFoldTwoConstants() {
 ; CHECK-LABEL: equalityFoldTwoConstants:
-; CHECK:       # BB#0: # %endblock
+; CHECK:       # %bb.0: # %endblock
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16)
@@ -171,13 +171,13 @@ define signext i32 @equalityFoldTwoConstants() {
 
 define signext i32 @equalityFoldOneConstant(i8* %X) {
 ; CHECK-LABEL: equalityFoldOneConstant:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    ld 4, 0(3)
 ; CHECK-NEXT:    sldi 5, 5, 32
 ; CHECK-NEXT:    cmpld 4, 5
 ; CHECK-NEXT:    bne 0, .LBB6_2
-; CHECK-NEXT:  # BB#1: # %loadbb1
+; CHECK-NEXT:  # %bb.1: # %loadbb1
 ; CHECK-NEXT:    li 4, 3
 ; CHECK-NEXT:    ld 3, 8(3)
 ; CHECK-NEXT:    sldi 4, 4, 32
@@ -199,7 +199,7 @@ define signext i32 @equalityFoldOneConstant(i8* %X) {
 
 define i1 @length2_eq_nobuiltin_attr(i8* %X, i8* %Y) {
 ; CHECK-LABEL: length2_eq_nobuiltin_attr:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    std 0, 16(1)
 ; CHECK-NEXT:    stdu 1, -32(1)
diff --git a/test/CodeGen/PowerPC/memcmp.ll b/test/CodeGen/PowerPC/memcmp.ll
index 392be4d712c..4aa5b400dd7 100644
--- a/test/CodeGen/PowerPC/memcmp.ll
+++ b/test/CodeGen/PowerPC/memcmp.ll
@@ -3,7 +3,7 @@
 
 define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp8:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ldbrx 3, 0, 3
 ; CHECK-NEXT:    ldbrx 4, 0, 4
 ; CHECK-NEXT:    subfc 5, 3, 4
@@ -23,7 +23,7 @@ define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture rea
 
 define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp4:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lwbrx 3, 0, 3
 ; CHECK-NEXT:    lwbrx 4, 0, 4
 ; CHECK-NEXT:    sub 5, 4, 3
@@ -41,7 +41,7 @@ define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture rea
 
 define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp2:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lhbrx 3, 0, 3
 ; CHECK-NEXT:    lhbrx 4, 0, 4
 ; CHECK-NEXT:    subf 3, 4, 3
@@ -55,7 +55,7 @@ define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture rea
 
 define signext i32 @memcmp1(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp1:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lbz 3, 0(3)
 ; CHECK-NEXT:    lbz 4, 0(4)
 ; CHECK-NEXT:    subf 3, 4, 3
diff --git a/test/CodeGen/PowerPC/negate-i1.ll b/test/CodeGen/PowerPC/negate-i1.ll
index c6a7867fe9d..a56048d67a8 100644
--- a/test/CodeGen/PowerPC/negate-i1.ll
+++ b/test/CodeGen/PowerPC/negate-i1.ll
@@ -4,7 +4,7 @@
 
 define i32 @select_i32_neg1_or_0(i1 %a) {
 ; CHECK-LABEL: select_i32_neg1_or_0:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrldi 3, 3, 63
 ; CHECK-NEXT:    neg 3, 3
 ; CHECK-NEXT:    blr
@@ -15,7 +15,7 @@ define i32 @select_i32_neg1_or_0(i1 %a) {
 
 define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
 ; CHECK-LABEL: select_i32_neg1_or_0_zeroext:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    neg 3, 3
 ; CHECK-NEXT:    blr
 ;
diff --git a/test/CodeGen/PowerPC/ppc32-nest.ll b/test/CodeGen/PowerPC/ppc32-nest.ll
index 221e8be2951..b933edcf616 100644
--- a/test/CodeGen/PowerPC/ppc32-nest.ll
+++ b/test/CodeGen/PowerPC/ppc32-nest.ll
@@ -7,7 +7,7 @@ target triple = "powerpc-unknown-linux-gnu"
 
 define i8* @nest_receiver(i8* nest %arg) nounwind {
 ; CHECK-LABEL: nest_receiver:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
 ; CHECK-NEXT: mr 3, 11
 ; CHECK-NEXT: blr
 
diff --git a/test/CodeGen/PowerPC/ppc64-nest.ll b/test/CodeGen/PowerPC/ppc64-nest.ll
index 14872632e81..cd2366cfa45 100644
--- a/test/CodeGen/PowerPC/ppc64-nest.ll
+++ b/test/CodeGen/PowerPC/ppc64-nest.ll
@@ -7,7 +7,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i8* @nest_receiver(i8* nest %arg) nounwind {
 ; CHECK-LABEL: nest_receiver:
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
 ; CHECK-NEXT: mr 3, 11
 ; CHECK-NEXT: blr
 
diff --git a/test/CodeGen/PowerPC/pr32140.ll b/test/CodeGen/PowerPC/pr32140.ll
index 827a90404e4..3feb9bd9c9e 100644
--- a/test/CodeGen/PowerPC/pr32140.ll
+++ b/test/CodeGen/PowerPC/pr32140.ll
@@ -9,7 +9,7 @@
 
 define void @bswapStorei64Toi32() {
 ; CHECK-LABEL: bswapStorei64Toi32:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         lwa 3, 0(3)
 ; CHECK-NEXT:    rldicl 3, 3, 32, 32
 ; CHECK-NEXT:    stwbrx 3, 0, 4
@@ -25,7 +25,7 @@ entry:
 
 define void @bswapStorei32Toi16() {
 ; CHECK-LABEL: bswapStorei32Toi16:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         lha 3, 0(3)
 ; CHECK-NEXT:    srwi 3, 3, 16
 ; CHECK-NEXT:    sthbrx 3, 0, 4
@@ -41,7 +41,7 @@ entry:
 
 define void @bswapStorei64Toi16() {
 ; CHECK-LABEL: bswapStorei64Toi16:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         lha 3, 0(3)
 ; CHECK-NEXT:    rldicl 3, 3, 16, 48
 ; CHECK-NEXT:    sthbrx 3, 0, 4
diff --git a/test/CodeGen/PowerPC/pr33093.ll b/test/CodeGen/PowerPC/pr33093.ll
index fc28bcfd0ca..af0350e17fd 100644
--- a/test/CodeGen/PowerPC/pr33093.ll
+++ b/test/CodeGen/PowerPC/pr33093.ll
@@ -4,7 +4,7 @@
 
 define zeroext i32 @ReverseBits(i32 zeroext %n) {
 ; CHECK-LABEL: ReverseBits:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis 4, -21846
 ; CHECK-NEXT:    lis 5, 21845
 ; CHECK-NEXT:    slwi 6, 3, 1
@@ -68,7 +68,7 @@ entry:
 
 define i64 @ReverseBits64(i64 %n) {
 ; CHECK-LABEL: ReverseBits64:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis 4, -21846
 ; CHECK-NEXT:    lis 5, 21845
 ; CHECK-NEXT:    lis 6, -13108
diff --git a/test/CodeGen/PowerPC/select-addrRegRegOnly.ll b/test/CodeGen/PowerPC/select-addrRegRegOnly.ll
index 6be31eaea74..46b23ff04f2 100644
--- a/test/CodeGen/PowerPC/select-addrRegRegOnly.ll
+++ b/test/CodeGen/PowerPC/select-addrRegRegOnly.ll
@@ -4,7 +4,7 @@
 ; Function Attrs: norecurse nounwind readonly
 define float @testSingleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 {
 ; CHECK-LABEL: testSingleAccess:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi 3, 3, 8
 ; CHECK-NEXT:    lfiwax 0, 0, 3
 ; CHECK-NEXT:    xscvsxdsp 1, 0
@@ -19,7 +19,7 @@ entry:
 ; Function Attrs: norecurse nounwind readonly
 define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 {
 ; CHECK-LABEL: testMultipleAccess:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz 4, 8(3)
 ; CHECK-NEXT:    lwz 12, 12(3)
 ; CHECK-NEXT:    add 3, 12, 4
diff --git a/test/CodeGen/PowerPC/select_const.ll b/test/CodeGen/PowerPC/select_const.ll
index fd864805abd..178d9187e3b 100644
--- a/test/CodeGen/PowerPC/select_const.ll
+++ b/test/CodeGen/PowerPC/select_const.ll
@@ -9,7 +9,7 @@
 
 define i32 @select_0_or_1(i1 %cond) {
 ; ALL-LABEL: select_0_or_1:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    not 3, 3
 ; ALL-NEXT:    clrldi 3, 3, 63
 ; ALL-NEXT:    blr
@@ -19,7 +19,7 @@ define i32 @select_0_or_1(i1 %cond) {
 
 define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {
 ; ALL-LABEL: select_0_or_1_zeroext:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    xori 3, 3, 1
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 0, i32 1
@@ -28,7 +28,7 @@ define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {
 
 define i32 @select_0_or_1_signext(i1 signext %cond) {
 ; ALL-LABEL: select_0_or_1_signext:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    not 3, 3
 ; ALL-NEXT:    clrldi 3, 3, 63
 ; ALL-NEXT:    blr
@@ -40,7 +40,7 @@ define i32 @select_0_or_1_signext(i1 signext %cond) {
 
 define i32 @select_1_or_0(i1 %cond) {
 ; ALL-LABEL: select_1_or_0:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    clrldi 3, 3, 63
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 1, i32 0
@@ -49,7 +49,7 @@ define i32 @select_1_or_0(i1 %cond) {
 
 define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
 ; ALL-LABEL: select_1_or_0_zeroext:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 1, i32 0
   ret i32 %sel
@@ -57,7 +57,7 @@ define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
 
 define i32 @select_1_or_0_signext(i1 signext %cond) {
 ; ALL-LABEL: select_1_or_0_signext:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    clrldi 3, 3, 63
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 1, i32 0
@@ -68,7 +68,7 @@ define i32 @select_1_or_0_signext(i1 signext %cond) {
 
 define i32 @select_0_or_neg1(i1 %cond) {
 ; ISEL-LABEL: select_0_or_neg1:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    oris 3, 4, 65535
@@ -77,7 +77,7 @@ define i32 @select_0_or_neg1(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_0_or_neg1:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    oris 3, 4, 65535
@@ -93,7 +93,7 @@ define i32 @select_0_or_neg1(i1 %cond) {
 
 define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
 ; ISEL-LABEL: select_0_or_neg1_zeroext:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    oris 3, 4, 65535
@@ -102,7 +102,7 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_0_or_neg1_zeroext:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    oris 3, 4, 65535
@@ -118,7 +118,7 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
 
 define i32 @select_0_or_neg1_signext(i1 signext %cond) {
 ; ISEL-LABEL: select_0_or_neg1_signext:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    oris 3, 4, 65535
@@ -127,7 +127,7 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_0_or_neg1_signext:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    oris 3, 4, 65535
@@ -145,7 +145,7 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) {
 
 define i32 @select_neg1_or_0(i1 %cond) {
 ; ISEL-LABEL: select_neg1_or_0:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    oris 3, 4, 65535
@@ -154,13 +154,13 @@ define i32 @select_neg1_or_0(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_neg1_or_0:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    oris 3, 4, 65535
 ; NO_ISEL-NEXT:    ori 3, 3, 65535
 ; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 -1, i32 0
@@ -169,7 +169,7 @@ define i32 @select_neg1_or_0(i1 %cond) {
 
 define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
 ; ISEL-LABEL: select_neg1_or_0_zeroext:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    oris 3, 4, 65535
@@ -178,13 +178,13 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_neg1_or_0_zeroext:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    oris 3, 4, 65535
 ; NO_ISEL-NEXT:    ori 3, 3, 65535
 ; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 -1, i32 0
@@ -193,7 +193,7 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
 
 define i32 @select_neg1_or_0_signext(i1 signext %cond) {
 ; ISEL-LABEL: select_neg1_or_0_signext:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    oris 3, 4, 65535
@@ -202,13 +202,13 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_neg1_or_0_signext:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    oris 3, 4, 65535
 ; NO_ISEL-NEXT:    ori 3, 3, 65535
 ; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 -1, i32 0
@@ -219,7 +219,7 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) {
 
 define i32 @select_Cplus1_C(i1 %cond) {
 ; ALL-LABEL: select_Cplus1_C:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    clrldi 3, 3, 63
 ; ALL-NEXT:    addi 3, 3, 41
 ; ALL-NEXT:    blr
@@ -229,7 +229,7 @@ define i32 @select_Cplus1_C(i1 %cond) {
 
 define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
 ; ALL-LABEL: select_Cplus1_C_zeroext:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    addi 3, 3, 41
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 42, i32 41
@@ -238,7 +238,7 @@ define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
 
 define i32 @select_Cplus1_C_signext(i1 signext %cond) {
 ; ALL-LABEL: select_Cplus1_C_signext:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    subfic 3, 3, 41
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 42, i32 41
@@ -249,7 +249,7 @@ define i32 @select_Cplus1_C_signext(i1 signext %cond) {
 
 define i32 @select_C_Cplus1(i1 %cond) {
 ; ALL-LABEL: select_C_Cplus1:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    clrldi 3, 3, 63
 ; ALL-NEXT:    subfic 3, 3, 42
 ; ALL-NEXT:    blr
@@ -259,7 +259,7 @@ define i32 @select_C_Cplus1(i1 %cond) {
 
 define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
 ; ALL-LABEL: select_C_Cplus1_zeroext:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    subfic 3, 3, 42
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 41, i32 42
@@ -268,7 +268,7 @@ define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
 
 define i32 @select_C_Cplus1_signext(i1 signext %cond) {
 ; ALL-LABEL: select_C_Cplus1_signext:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    addi 3, 3, 42
 ; ALL-NEXT:    blr
   %sel = select i1 %cond, i32 41, i32 42
@@ -280,7 +280,7 @@ define i32 @select_C_Cplus1_signext(i1 signext %cond) {
 
 define i32 @select_C1_C2(i1 %cond) {
 ; ISEL-LABEL: select_C1_C2:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
@@ -288,7 +288,7 @@ define i32 @select_C1_C2(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 421
 ; NO_ISEL-NEXT:    li 3, 42
@@ -303,7 +303,7 @@ define i32 @select_C1_C2(i1 %cond) {
 
 define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
 ; ISEL-LABEL: select_C1_C2_zeroext:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
@@ -311,7 +311,7 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_zeroext:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 421
 ; NO_ISEL-NEXT:    li 3, 42
@@ -326,7 +326,7 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
 
 define i32 @select_C1_C2_signext(i1 signext %cond) {
 ; ISEL-LABEL: select_C1_C2_signext:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
@@ -334,7 +334,7 @@ define i32 @select_C1_C2_signext(i1 signext %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_signext:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 421
 ; NO_ISEL-NEXT:    li 3, 42
@@ -351,7 +351,7 @@ define i32 @select_C1_C2_signext(i1 signext %cond) {
 
 define i8 @sel_constants_add_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_add_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 1
 ; ISEL-NEXT:    li 3, 28
@@ -359,7 +359,7 @@ define i8 @sel_constants_add_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_add_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 1
 ; NO_ISEL-NEXT:    li 3, 28
@@ -375,7 +375,7 @@ define i8 @sel_constants_add_constant(i1 %cond) {
 
 define i8 @sel_constants_sub_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sub_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    oris 3, 4, 65535
@@ -385,14 +385,14 @@ define i8 @sel_constants_sub_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    oris 3, 4, 65535
 ; NO_ISEL-NEXT:    li 4, 18
 ; NO_ISEL-NEXT:    ori 3, 3, 65527
 ; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
@@ -402,7 +402,7 @@ define i8 @sel_constants_sub_constant(i1 %cond) {
 
 define i8 @sel_constants_mul_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_mul_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    lis 4, 16383
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    ori 3, 4, 65531
@@ -412,14 +412,14 @@ define i8 @sel_constants_mul_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_mul_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    lis 4, 16383
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    ori 3, 4, 65531
 ; NO_ISEL-NEXT:    li 4, 115
 ; NO_ISEL-NEXT:    sldi 3, 3, 2
 ; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
@@ -429,14 +429,14 @@ define i8 @sel_constants_mul_constant(i1 %cond) {
 
 define i8 @sel_constants_sdiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sdiv_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 4
 ; ISEL-NEXT:    isel 3, 0, 3, 1
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sdiv_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 3, 4
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB24_1
@@ -451,7 +451,7 @@ define i8 @sel_constants_sdiv_constant(i1 %cond) {
 
 define i8 @sel_constants_udiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_udiv_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 50
 ; ISEL-NEXT:    li 3, 4
@@ -459,7 +459,7 @@ define i8 @sel_constants_udiv_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_udiv_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 50
 ; NO_ISEL-NEXT:    li 3, 4
@@ -475,7 +475,7 @@ define i8 @sel_constants_udiv_constant(i1 %cond) {
 
 define i8 @sel_constants_srem_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_srem_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    lis 4, 16383
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    ori 3, 4, 65535
@@ -485,14 +485,14 @@ define i8 @sel_constants_srem_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_srem_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    lis 4, 16383
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    ori 3, 4, 65535
 ; NO_ISEL-NEXT:    li 4, 3
 ; NO_ISEL-NEXT:    sldi 3, 3, 2
 ; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
@@ -502,7 +502,7 @@ define i8 @sel_constants_srem_constant(i1 %cond) {
 
 define i8 @sel_constants_urem_constant(i1 %cond) {
 ; ALL-LABEL: sel_constants_urem_constant:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
 ; ALL-NEXT:    subfic 3, 3, 3
 ; ALL-NEXT:    blr
@@ -513,7 +513,7 @@ define i8 @sel_constants_urem_constant(i1 %cond) {
 
 define i8 @sel_constants_and_constant(i1 %cond) {
 ; ALL-LABEL: sel_constants_and_constant:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    rlwinm 3, 3, 0, 31, 31
 ; ALL-NEXT:    subfic 3, 3, 5
 ; ALL-NEXT:    blr
@@ -524,7 +524,7 @@ define i8 @sel_constants_and_constant(i1 %cond) {
 
 define i8 @sel_constants_or_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_or_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    oris 3, 4, 65535
@@ -534,14 +534,14 @@ define i8 @sel_constants_or_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_or_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    oris 3, 4, 65535
 ; NO_ISEL-NEXT:    li 4, 23
 ; NO_ISEL-NEXT:    ori 3, 3, 65533
 ; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
@@ -551,7 +551,7 @@ define i8 @sel_constants_or_constant(i1 %cond) {
 
 define i8 @sel_constants_xor_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_xor_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    li 4, 0
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    oris 3, 4, 65535
@@ -561,14 +561,14 @@ define i8 @sel_constants_xor_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_xor_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    li 4, 0
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    oris 3, 4, 65535
 ; NO_ISEL-NEXT:    li 4, 18
 ; NO_ISEL-NEXT:    ori 3, 3, 65529
 ; NO_ISEL-NEXT:    bclr 12, 1, 0
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
@@ -578,7 +578,7 @@ define i8 @sel_constants_xor_constant(i1 %cond) {
 
 define i8 @sel_constants_shl_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_shl_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    lis 5, 511
 ; ISEL-NEXT:    lis 4, 2047
 ; ISEL-NEXT:    andi. 3, 3, 1
@@ -590,7 +590,7 @@ define i8 @sel_constants_shl_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_shl_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    lis 5, 511
 ; NO_ISEL-NEXT:    lis 4, 2047
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
@@ -610,7 +610,7 @@ define i8 @sel_constants_shl_constant(i1 %cond) {
 
 define i8 @sel_constants_lshr_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_lshr_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 7
 ; ISEL-NEXT:    li 3, 0
@@ -618,7 +618,7 @@ define i8 @sel_constants_lshr_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_lshr_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 7
 ; NO_ISEL-NEXT:    li 3, 0
@@ -634,7 +634,7 @@ define i8 @sel_constants_lshr_constant(i1 %cond) {
 
 define i8 @sel_constants_ashr_constant(i1 %cond) {
 ; ALL-LABEL: sel_constants_ashr_constant:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    clrldi 3, 3, 63
 ; ALL-NEXT:    neg 3, 3
 ; ALL-NEXT:    blr
@@ -645,7 +645,7 @@ define i8 @sel_constants_ashr_constant(i1 %cond) {
 
 define double @sel_constants_fadd_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fadd_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI34_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI34_1@toc@ha
@@ -656,14 +656,14 @@ define double @sel_constants_fadd_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fadd_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI34_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI34_1@toc@ha
 ; NO_ISEL-NEXT:    addi 4, 4, .LCPI34_0@toc@l
 ; NO_ISEL-NEXT:    addi 3, 3, .LCPI34_1@toc@l
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB34_2
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB34_2
 ; NO_ISEL-NEXT:  .LBB34_2:
@@ -676,7 +676,7 @@ define double @sel_constants_fadd_constant(i1 %cond) {
 
 define double @sel_constants_fsub_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fsub_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI35_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
@@ -687,14 +687,14 @@ define double @sel_constants_fsub_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fsub_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI35_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI35_1@toc@ha
 ; NO_ISEL-NEXT:    addi 4, 4, .LCPI35_0@toc@l
 ; NO_ISEL-NEXT:    addi 3, 3, .LCPI35_1@toc@l
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB35_2
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB35_2
 ; NO_ISEL-NEXT:  .LBB35_2:
@@ -707,7 +707,7 @@ define double @sel_constants_fsub_constant(i1 %cond) {
 
 define double @sel_constants_fmul_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fmul_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI36_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI36_1@toc@ha
@@ -718,14 +718,14 @@ define double @sel_constants_fmul_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fmul_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI36_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI36_1@toc@ha
 ; NO_ISEL-NEXT:    addi 4, 4, .LCPI36_0@toc@l
 ; NO_ISEL-NEXT:    addi 3, 3, .LCPI36_1@toc@l
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB36_2
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB36_2
 ; NO_ISEL-NEXT:  .LBB36_2:
@@ -738,7 +738,7 @@ define double @sel_constants_fmul_constant(i1 %cond) {
 
 define double @sel_constants_fdiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fdiv_constant:
-; ISEL:       # BB#0:
+; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI37_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI37_1@toc@ha
@@ -749,14 +749,14 @@ define double @sel_constants_fdiv_constant(i1 %cond) {
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fdiv_constant:
-; NO_ISEL:       # BB#0:
+; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI37_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI37_1@toc@ha
 ; NO_ISEL-NEXT:    addi 4, 4, .LCPI37_0@toc@l
 ; NO_ISEL-NEXT:    addi 3, 3, .LCPI37_1@toc@l
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB37_2
-; NO_ISEL-NEXT:  # BB#1:
+; NO_ISEL-NEXT:  # %bb.1:
 ; NO_ISEL-NEXT:    ori 3, 4, 0
 ; NO_ISEL-NEXT:    b .LBB37_2
 ; NO_ISEL-NEXT:  .LBB37_2:
@@ -769,10 +769,10 @@ define double @sel_constants_fdiv_constant(i1 %cond) {
 
 define double @sel_constants_frem_constant(i1 %cond) {
 ; ALL-LABEL: sel_constants_frem_constant:
-; ALL:       # BB#0:
+; ALL:       # %bb.0:
 ; ALL-NEXT:    andi. 3, 3, 1
 ; ALL-NEXT:    bc 12, 1, .LBB38_2
-; ALL-NEXT:  # BB#1:
+; ALL-NEXT:  # %bb.1:
 ; ALL-NEXT:    addis 3, 2, .LCPI38_0@toc@ha
 ; ALL-NEXT:    addi 3, 3, .LCPI38_0@toc@l
 ; ALL-NEXT:    lxsdx 1, 0, 3
diff --git a/test/CodeGen/PowerPC/setcc-logic.ll b/test/CodeGen/PowerPC/setcc-logic.ll
index 108a6bb2909..b17869f312c 100644
--- a/test/CodeGen/PowerPC/setcc-logic.ll
+++ b/test/CodeGen/PowerPC/setcc-logic.ll
@@ -3,7 +3,7 @@
 
 define zeroext i1 @all_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_bits_clear:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 5
@@ -16,7 +16,7 @@ define zeroext i1 @all_bits_clear(i32 %P, i32 %Q)  {
 
 define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_clear:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    nor 3, 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
@@ -29,7 +29,7 @@ define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q)  {
 
 define zeroext i1 @all_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_bits_set:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    xor 3, 3, 5
@@ -44,7 +44,7 @@ define zeroext i1 @all_bits_set(i32 %P, i32 %Q)  {
 
 define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_set:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
@@ -56,7 +56,7 @@ define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q)  {
 
 define zeroext i1 @any_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_bits_set:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 5
@@ -70,7 +70,7 @@ define zeroext i1 @any_bits_set(i32 %P, i32 %Q)  {
 
 define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_set:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
@@ -82,7 +82,7 @@ define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q)  {
 
 define zeroext i1 @any_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_bits_clear:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    xor 3, 3, 5
@@ -98,7 +98,7 @@ define zeroext i1 @any_bits_clear(i32 %P, i32 %Q)  {
 
 define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_clear:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    nor 3, 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
@@ -112,10 +112,10 @@ define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q)  {
 ; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0
 define i32 @all_bits_clear_branch(i32* %P, i32* %Q)  {
 ; CHECK-LABEL: all_bits_clear_branch:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or. 3, 3, 4
 ; CHECK-NEXT:    bne 0, .LBB8_2
-; CHECK-NEXT:  # BB#1: # %bb1
+; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB8_2: # %return
@@ -136,11 +136,11 @@ return:
 
 define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_clear_branch:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    cmpwi 0, 3, 0
 ; CHECK-NEXT:    blt 0, .LBB9_2
-; CHECK-NEXT:  # BB#1: # %bb1
+; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB9_2: # %return
@@ -161,11 +161,11 @@ return:
 
 define i32 @all_bits_set_branch(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_bits_set_branch:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    cmpwi 0, 3, -1
 ; CHECK-NEXT:    bne 0, .LBB10_2
-; CHECK-NEXT:  # BB#1: # %bb1
+; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB10_2: # %return
@@ -186,11 +186,11 @@ return:
 
 define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_set_branch:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    cmpwi 0, 3, -1
 ; CHECK-NEXT:    bgt 0, .LBB11_2
-; CHECK-NEXT:  # BB#1: # %bb1
+; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB11_2: # %return
@@ -212,10 +212,10 @@ return:
 ; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0
 define i32 @any_bits_set_branch(i32* %P, i32* %Q)  {
 ; CHECK-LABEL: any_bits_set_branch:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or. 3, 3, 4
 ; CHECK-NEXT:    beq 0, .LBB12_2
-; CHECK-NEXT:  # BB#1: # %bb1
+; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB12_2: # %return
@@ -236,11 +236,11 @@ return:
 
 define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_set_branch:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    cmpwi 0, 3, -1
 ; CHECK-NEXT:    bgt 0, .LBB13_2
-; CHECK-NEXT:  # BB#1: # %bb1
+; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB13_2: # %return
@@ -261,11 +261,11 @@ return:
 
 define i32 @any_bits_clear_branch(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_bits_clear_branch:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    cmpwi 0, 3, -1
 ; CHECK-NEXT:    beq 0, .LBB14_2
-; CHECK-NEXT:  # BB#1: # %bb1
+; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB14_2: # %return
@@ -286,11 +286,11 @@ return:
 
 define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_clear_branch:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    cmpwi 0, 3, 0
 ; CHECK-NEXT:    blt 0, .LBB15_2
-; CHECK-NEXT:  # BB#1: # %bb1
+; CHECK-NEXT:  # %bb.1: # %bb1
 ; CHECK-NEXT:    li 3, 4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB15_2: # %return
@@ -311,7 +311,7 @@ return:
 
 define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_bits_clear_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlxor 36, 36, 36
 ; CHECK-NEXT:    xxlor 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
@@ -324,7 +324,7 @@ define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 
 define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_sign_bits_clear_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisb 4, -1
 ; CHECK-NEXT:    xxlor 34, 34, 35
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 4
@@ -337,7 +337,7 @@ define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 
 define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_bits_set_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisb 4, -1
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
@@ -350,7 +350,7 @@ define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 
 define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: all_sign_bits_set_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlxor 36, 36, 36
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpgtsw 2, 4, 2
@@ -363,7 +363,7 @@ define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 
 define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_bits_set_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlxor 36, 36, 36
 ; CHECK-NEXT:    xxlor 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
@@ -377,7 +377,7 @@ define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 
 define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_sign_bits_set_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xxlxor 36, 36, 36
 ; CHECK-NEXT:    xxlor 34, 34, 35
 ; CHECK-NEXT:    vcmpgtsw 2, 4, 2
@@ -390,7 +390,7 @@ define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
 
 define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_bits_clear_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisb 4, -1
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpequw 2, 2, 4
@@ -404,7 +404,7 @@ define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 
 define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 ; CHECK-LABEL: any_sign_bits_clear_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisb 4, -1
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    vcmpgtsw 2, 2, 4
@@ -417,7 +417,7 @@ define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
 
 define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
 ; CHECK-LABEL: ne_neg1_and_ne_zero:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    subfc 3, 3, 4
@@ -434,7 +434,7 @@ define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
 
 define zeroext i1 @and_eq(i16 zeroext  %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
 ; CHECK-LABEL: and_eq:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor 5, 5, 6
 ; CHECK-NEXT:    xor 3, 3, 4
 ; CHECK-NEXT:    or 3, 3, 5
@@ -449,7 +449,7 @@ define zeroext i1 @and_eq(i16 zeroext  %a, i16 zeroext %b, i16 zeroext %c, i16 z
 
 define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {
 ; CHECK-LABEL: or_ne:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor 5, 5, 6
 ; CHECK-NEXT:    xor 3, 3, 4
 ; CHECK-NEXT:    or 3, 3, 5
@@ -467,7 +467,7 @@ define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {
 
 define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
 ; CHECK-LABEL: and_eq_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-NEXT:    vcmpequw 19, 4, 5
 ; CHECK-NEXT:    xxland 34, 34, 51
diff --git a/test/CodeGen/PowerPC/setcc-to-sub.ll b/test/CodeGen/PowerPC/setcc-to-sub.ll
index 752ebe0c9d8..a143d73c7c0 100644
--- a/test/CodeGen/PowerPC/setcc-to-sub.ll
+++ b/test/CodeGen/PowerPC/setcc-to-sub.ll
@@ -8,7 +8,7 @@
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test1:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz 3, 0(3)
 ; CHECK-NEXT:    lwz 4, 0(4)
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
@@ -30,7 +30,7 @@ entry:
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i1 @test2(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test2:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz 3, 0(3)
 ; CHECK-NEXT:    lwz 4, 0(4)
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
@@ -53,7 +53,7 @@ entry:
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i1 @test3(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test3:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz 3, 0(3)
 ; CHECK-NEXT:    lwz 4, 0(4)
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
@@ -75,7 +75,7 @@ entry:
 ; Function Attrs: norecurse nounwind readonly
 define zeroext i1 @test4(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
 ; CHECK-LABEL: test4:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lwz 3, 0(3)
 ; CHECK-NEXT:    lwz 4, 0(4)
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
diff --git a/test/CodeGen/PowerPC/shift_mask.ll b/test/CodeGen/PowerPC/shift_mask.ll
index e9ca9b0bdf0..59382c61531 100644
--- a/test/CodeGen/PowerPC/shift_mask.ll
+++ b/test/CodeGen/PowerPC/shift_mask.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64le-linux-gnu"
 
 define i8 @test000(i8 %a, i8 %b) {
 ; CHECK-LABEL: test000:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 29, 31
 ; CHECK-NEXT:    slw 3, 3, 4
 ; CHECK-NEXT:    blr
@@ -15,7 +15,7 @@ define i8 @test000(i8 %a, i8 %b) {
 
 define i16 @test001(i16 %a, i16 %b) {
 ; CHECK-LABEL: test001:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
 ; CHECK-NEXT:    slw 3, 3, 4
 ; CHECK-NEXT:    blr
@@ -26,7 +26,7 @@ define i16 @test001(i16 %a, i16 %b) {
 
 define i32 @test002(i32 %a, i32 %b) {
 ; CHECK-LABEL: test002:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 27, 31
 ; CHECK-NEXT:    slw 3, 3, 4
 ; CHECK-NEXT:    blr
@@ -37,7 +37,7 @@ define i32 @test002(i32 %a, i32 %b) {
 
 define i64 @test003(i64 %a, i64 %b) {
 ; CHECK-LABEL: test003:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
 ; CHECK-NEXT:    sld 3, 3, 4
 ; CHECK-NEXT:    blr
@@ -48,7 +48,7 @@ define i64 @test003(i64 %a, i64 %b) {
 
 define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test010:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vslb 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
@@ -58,7 +58,7 @@ define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) {
 
 define <8 x i16> @test011(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test011:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vslh 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
@@ -68,7 +68,7 @@ define <8 x i16> @test011(<8 x i16> %a, <8 x i16> %b) {
 
 define <4 x i32> @test012(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test012:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vslw 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
@@ -78,7 +78,7 @@ define <4 x i32> @test012(<4 x i32> %a, <4 x i32> %b) {
 
 define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test013:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsld 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <2 x i64> %b, <i64 63, i64 63>
@@ -88,7 +88,7 @@ define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) {
 
 define i8 @test100(i8 %a, i8 %b) {
 ; CHECK-LABEL: test100:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 24, 31
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 29, 31
 ; CHECK-NEXT:    srw 3, 3, 4
@@ -100,7 +100,7 @@ define i8 @test100(i8 %a, i8 %b) {
 
 define i16 @test101(i16 %a, i16 %b) {
 ; CHECK-LABEL: test101:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 16, 31
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
 ; CHECK-NEXT:    srw 3, 3, 4
@@ -112,7 +112,7 @@ define i16 @test101(i16 %a, i16 %b) {
 
 define i32 @test102(i32 %a, i32 %b) {
 ; CHECK-LABEL: test102:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 27, 31
 ; CHECK-NEXT:    srw 3, 3, 4
 ; CHECK-NEXT:    blr
@@ -123,7 +123,7 @@ define i32 @test102(i32 %a, i32 %b) {
 
 define i64 @test103(i64 %a, i64 %b) {
 ; CHECK-LABEL: test103:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
 ; CHECK-NEXT:    srd 3, 3, 4
 ; CHECK-NEXT:    blr
@@ -134,7 +134,7 @@ define i64 @test103(i64 %a, i64 %b) {
 
 define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test110:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsrb 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
@@ -144,7 +144,7 @@ define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) {
 
 define <8 x i16> @test111(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test111:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsrh 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
@@ -154,7 +154,7 @@ define <8 x i16> @test111(<8 x i16> %a, <8 x i16> %b) {
 
 define <4 x i32> @test112(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test112:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsrw 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
@@ -164,7 +164,7 @@ define <4 x i32> @test112(<4 x i32> %a, <4 x i32> %b) {
 
 define <2 x i64> @test113(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test113:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsrd 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <2 x i64> %b, <i64 63, i64 63>
@@ -174,7 +174,7 @@ define <2 x i64> @test113(<2 x i64> %a, <2 x i64> %b) {
 
 define i8 @test200(i8 %a, i8 %b) {
 ; CHECK-LABEL: test200:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    extsb 3, 3
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 29, 31
 ; CHECK-NEXT:    sraw 3, 3, 4
@@ -186,7 +186,7 @@ define i8 @test200(i8 %a, i8 %b) {
 
 define i16 @test201(i16 %a, i16 %b) {
 ; CHECK-LABEL: test201:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    extsh 3, 3
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
 ; CHECK-NEXT:    sraw 3, 3, 4
@@ -198,7 +198,7 @@ define i16 @test201(i16 %a, i16 %b) {
 
 define i32 @test202(i32 %a, i32 %b) {
 ; CHECK-LABEL: test202:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 27, 31
 ; CHECK-NEXT:    sraw 3, 3, 4
 ; CHECK-NEXT:    blr
@@ -209,7 +209,7 @@ define i32 @test202(i32 %a, i32 %b) {
 
 define i64 @test203(i64 %a, i64 %b) {
 ; CHECK-LABEL: test203:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
 ; CHECK-NEXT:    srad 3, 3, 4
 ; CHECK-NEXT:    blr
@@ -220,7 +220,7 @@ define i64 @test203(i64 %a, i64 %b) {
 
 define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test210:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsrab 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
@@ -230,7 +230,7 @@ define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) {
 
 define <8 x i16> @test211(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test211:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsrah 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
@@ -240,7 +240,7 @@ define <8 x i16> @test211(<8 x i16> %a, <8 x i16> %b) {
 
 define <4 x i32> @test212(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test212:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsraw 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
@@ -250,7 +250,7 @@ define <4 x i32> @test212(<4 x i32> %a, <4 x i32> %b) {
 
 define <2 x i64> @test213(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test213:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsrad 2, 2, 3
 ; CHECK-NEXT:    blr
   %rem = and <2 x i64> %b, <i64 63, i64 63>
diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll
index 14aec583891..68b53417f01 100644
--- a/test/CodeGen/PowerPC/sjlj.ll
+++ b/test/CodeGen/PowerPC/sjlj.ll
@@ -77,7 +77,7 @@ return:                                           ; preds = %if.end, %if.then
 ; CHECK: bcl 20, 31, .LBB1_3
 ; CHECK: li 3, 1
 ; CHECK: #EH_SjLj_Setup	.LBB1_3
-; CHECK: # BB#1:
+; CHECK: # %bb.1:
 
 ; CHECK: .LBB1_3:
 ; CHECK: mflr [[REGL:[0-9]+]]
diff --git a/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll b/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll
index 0b101457161..3ff4753200e 100644
--- a/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll
+++ b/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll
@@ -12,17 +12,17 @@ declare void @f4()
 
 ; Function Attrs: nounwind
 ; CHECK-LABEL: tail_dup_fallthrough_with_branch
-; CHECK: # %entry
+; CHECK: # %bb.{{[0-9]+}}: # %entry
 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
-; CHECK: # %entry
+; CHECK: # %bb.{{[0-9]+}}: # %entry
 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
-; CHECK: # %sw.0
+; CHECK: # %bb.{{[0-9]+}}: # %sw.0
 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
 ; CHECK: # %sw.1
 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
 ; CHECK: # %sw.default
 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
-; CHECK: # %if.then
+; CHECK: # %bb.{{[0-9]+}}: # %if.then
 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
 ; CHECK: # %if.else
 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
diff --git a/test/CodeGen/PowerPC/tail-dup-layout.ll b/test/CodeGen/PowerPC/tail-dup-layout.ll
index 9665901e874..badeed5b30a 100644
--- a/test/CodeGen/PowerPC/tail-dup-layout.ll
+++ b/test/CodeGen/PowerPC/tail-dup-layout.ll
@@ -278,7 +278,7 @@ exit:
 ;CHECK: addi
 ;CHECK: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check
 ;CHECK: lwz [[TAGREG:[0-9]+]], 0([[TAGPTRREG]])
-;CHECK: # %test1
+;CHECK: # %bb.{{[0-9]+}}: # %test1
 ;CHECK: andi. {{[0-9]+}}, [[TAGREG]], 1
 ;CHECK-NEXT: bc 12, 1, .[[OPT1LABEL:[._0-9A-Za-z]+]]
 ;CHECK-NEXT: # %test2
@@ -366,12 +366,12 @@ exit:
 ; code is independent of the outlining code, which works by choosing the
 ; "unavoidable" blocks.
 ; CHECK-LABEL: avoidable_test:
-; CHECK: # %entry
+; CHECK: # %bb.{{[0-9]+}}: # %entry
 ; CHECK: andi.
-; CHECK: # %test2
+; CHECK: # %bb.{{[0-9]+}}: # %test2
 ; Make sure then2 falls through from test2
 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}
-; CHECK: # %then2
+; CHECK: # %bb.{{[0-9]+}}: # %then2
 ; CHECK: rlwinm. {{[0-9]+}}, {{[0-9]+}}, 0, 29, 29
 ; CHECK: # %else1
 ; CHECK: bl a
@@ -420,8 +420,8 @@ end1:
 ; The f;g->h;i trellis should be resolved as f->i;g->h.
 ; The h;i->j;ret trellis contains a triangle edge, and should be resolved as
 ; h->j->ret
-; CHECK: # %entry
-; CHECK: # %c10
+; CHECK: # %bb.{{[0-9]+}}: # %entry
+; CHECK: # %bb.{{[0-9]+}}: # %c10
 ; CHECK: # %e9
 ; CHECK: # %g10
 ; CHECK: # %h10
@@ -504,8 +504,8 @@ ret:
 ; checking, it's profitable to duplicate G into F. The weights here are not
 ; really important. They are there to help make the test stable.
 ; CHECK-LABEL: trellis_then_dup_test
-; CHECK: # %entry
-; CHECK: # %b
+; CHECK: # %bb.{{[0-9]+}}: # %entry
+; CHECK: # %bb.{{[0-9]+}}: # %b
 ; CHECK: # %d
 ; CHECK: # %g
 ; CHECK: # %ret1
@@ -568,8 +568,8 @@ ret:
 ; Verify that we did not mis-identify triangle trellises if it is not
 ; really a triangle.
 ; CHECK-LABEL: trellis_no_triangle
-; CHECK: # %entry
-; CHECK: # %b
+; CHECK: # %bb.{{[0-9]+}}: # %entry
+; CHECK: # %bb.{{[0-9]+}}: # %b
 ; CHECK: # %d
 ; CHECK: # %ret
 ; CHECK: # %c
diff --git a/test/CodeGen/PowerPC/testBitReverse.ll b/test/CodeGen/PowerPC/testBitReverse.ll
index 1508af9e4d0..22fefe45468 100644
--- a/test/CodeGen/PowerPC/testBitReverse.ll
+++ b/test/CodeGen/PowerPC/testBitReverse.ll
@@ -4,7 +4,7 @@
 declare i32 @llvm.bitreverse.i32(i32)
 define i32 @testBitReverseIntrinsicI32(i32 %arg) {
 ; CHECK-LABEL: testBitReverseIntrinsicI32:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21846
 ; CHECK-NEXT:    lis 5, 21845
 ; CHECK-NEXT:    slwi 6, 3, 1
@@ -44,7 +44,7 @@ define i32 @testBitReverseIntrinsicI32(i32 %arg) {
 declare i64 @llvm.bitreverse.i64(i64)
 define i64 @testBitReverseIntrinsicI64(i64 %arg) {
 ; CHECK-LABEL: testBitReverseIntrinsicI64:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21846
 ; CHECK-NEXT:    lis 5, 21845
 ; CHECK-NEXT:    lis 6, -13108
diff --git a/test/CodeGen/PowerPC/testComparesi32gtu.ll b/test/CodeGen/PowerPC/testComparesi32gtu.ll
index 1d0cee72823..4341b59390e 100644
--- a/test/CodeGen/PowerPC/testComparesi32gtu.ll
+++ b/test/CodeGen/PowerPC/testComparesi32gtu.ll
@@ -11,7 +11,7 @@ declare signext i32 @fn2(...) local_unnamed_addr #1
 ; Function Attrs: nounwind
 define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
 ; CHECK-LABEL: testCompare1:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         lbz r3, 0(r3)
 ; CHECK-DAG:     clrlwi r3, r3, 31
 ; CHECK-DAG:     clrldi r3, r3, 32
@@ -35,7 +35,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: testCompare2:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-DAG:     rlwinm r3, r3, 0, 31, 31
 ; CHECK-DAG:     rlwinm r4, r4, 0, 31, 31
 ; CHECK-DAG:     clrldi r3, r3, 32
diff --git a/test/CodeGen/PowerPC/testComparesi32leu.ll b/test/CodeGen/PowerPC/testComparesi32leu.ll
index 65a75dacbeb..3ba967b51da 100644
--- a/test/CodeGen/PowerPC/testComparesi32leu.ll
+++ b/test/CodeGen/PowerPC/testComparesi32leu.ll
@@ -8,7 +8,7 @@
 
 define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rlwinm r3, r3, 0, 31, 31
 ; CHECK-NEXT:    rlwinm r4, r4, 0, 31, 31
 ; CHECK-NEXT:    clrldi r3, r3, 32
diff --git a/test/CodeGen/PowerPC/testComparesi32ltu.ll b/test/CodeGen/PowerPC/testComparesi32ltu.ll
index fb6b3f88bb5..9623a63e9bc 100644
--- a/test/CodeGen/PowerPC/testComparesi32ltu.ll
+++ b/test/CodeGen/PowerPC/testComparesi32ltu.ll
@@ -11,7 +11,7 @@ declare signext i32 @fn2(...) local_unnamed_addr #1
 ; Function Attrs: nounwind
 define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
 ; CHECK-LABEL: testCompare1:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         lbz r3, 0(r3)
 ; CHECK-DAG:     clrlwi r3, r3, 31
 ; CHECK-DAG:     clrldi r3, r3, 32
@@ -35,7 +35,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: testCompare2:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-DAG:     rlwinm r3, r3, 0, 31, 31
 ; CHECK-DAG:     rlwinm r4, r4, 0, 31, 31
 ; CHECK-DAG:     clrldi r3, r3, 32
diff --git a/test/CodeGen/PowerPC/testComparesieqsc.ll b/test/CodeGen/PowerPC/testComparesieqsc.ll
index e65abd317f4..aa0211ebb65 100644
--- a/test/CodeGen/PowerPC/testComparesieqsc.ll
+++ b/test/CodeGen/PowerPC/testComparesieqsc.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -41,7 +41,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsc_z(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -54,7 +54,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsc_sext_z(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -68,7 +68,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -86,7 +86,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ieqsc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -105,7 +105,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsc_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -122,7 +122,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsc_sext_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_ieqsc_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesieqsi.ll b/test/CodeGen/PowerPC/testComparesieqsi.ll
index 81b28ac6fe5..0a6b7b9ca35 100644
--- a/test/CodeGen/PowerPC/testComparesieqsi.ll
+++ b/test/CodeGen/PowerPC/testComparesieqsi.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -41,7 +41,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsi_z(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -54,7 +54,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsi_sext_z(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -68,7 +68,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -86,7 +86,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ieqsi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -105,7 +105,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsi_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -122,7 +122,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsi_sext_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_ieqsi_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesieqsll.ll b/test/CodeGen/PowerPC/testComparesieqsll.ll
index bedd0ed9c97..1dae985c36c 100644
--- a/test/CodeGen/PowerPC/testComparesieqsll.ll
+++ b/test/CodeGen/PowerPC/testComparesieqsll.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ieqsll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ieqsll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    subfe r3, r3, r3
@@ -40,7 +40,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsll_z(i64 %a) {
 ; CHECK-LABEL: test_ieqsll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
 ; CHECK-NEXT:    blr
@@ -53,7 +53,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqsll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_ieqsll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    blr
@@ -66,7 +66,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ieqsll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -84,7 +84,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ieqsll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -102,7 +102,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsll_z_store(i64 %a) {
 ; CHECK-LABEL: test_ieqsll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -119,7 +119,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqsll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_ieqsll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesieqss.ll b/test/CodeGen/PowerPC/testComparesieqss.ll
index 66a1fa814b9..93a92e17807 100644
--- a/test/CodeGen/PowerPC/testComparesieqss.ll
+++ b/test/CodeGen/PowerPC/testComparesieqss.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -41,7 +41,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqss_z(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -54,7 +54,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ieqss_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -68,7 +68,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -86,7 +86,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_ieqss_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -105,7 +105,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqss_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -122,7 +122,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_ieqss_sext_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_ieqss_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesiequc.ll b/test/CodeGen/PowerPC/testComparesiequc.ll
index 2616ab56d8d..592f7bc83bb 100644
--- a/test/CodeGen/PowerPC/testComparesiequc.ll
+++ b/test/CodeGen/PowerPC/testComparesiequc.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -41,7 +41,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequc_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -54,7 +54,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -68,7 +68,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -86,7 +86,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iequc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -105,7 +105,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequc_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -122,7 +122,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_iequc_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesiequi.ll b/test/CodeGen/PowerPC/testComparesiequi.ll
index a4a1b7635e8..9a639dc5410 100644
--- a/test/CodeGen/PowerPC/testComparesiequi.ll
+++ b/test/CodeGen/PowerPC/testComparesiequi.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -41,7 +41,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequi_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -54,7 +54,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequi_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -68,7 +68,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -86,7 +86,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iequi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -105,7 +105,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequi_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -122,7 +122,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequi_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_iequi_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesiequll.ll b/test/CodeGen/PowerPC/testComparesiequll.ll
index 4d9035813a8..f147478d5ea 100644
--- a/test/CodeGen/PowerPC/testComparesiequll.ll
+++ b/test/CodeGen/PowerPC/testComparesiequll.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iequll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iequll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    subfe r3, r3, r3
@@ -40,7 +40,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequll_z(i64 %a) {
 ; CHECK-LABEL: test_iequll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
 ; CHECK-NEXT:    blr
@@ -53,7 +53,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_iequll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    blr
@@ -66,7 +66,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iequll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -84,7 +84,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iequll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -102,7 +102,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequll_z_store(i64 %a) {
 ; CHECK-LABEL: test_iequll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -119,7 +119,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_iequll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesiequs.ll b/test/CodeGen/PowerPC/testComparesiequs.ll
index 5d47c38f739..195339ddb2e 100644
--- a/test/CodeGen/PowerPC/testComparesiequs.ll
+++ b/test/CodeGen/PowerPC/testComparesiequs.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -41,7 +41,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequs_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -54,7 +54,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -68,7 +68,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -86,7 +86,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iequs_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -105,7 +105,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequs_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -122,7 +122,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iequs_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_iequs_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesigesc.ll b/test/CodeGen/PowerPC/testComparesigesc.ll
index 130127bf351..69dd97fc9c4 100644
--- a/test/CodeGen/PowerPC/testComparesigesc.ll
+++ b/test/CodeGen/PowerPC/testComparesigesc.ll
@@ -9,7 +9,7 @@
 
 define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -22,7 +22,7 @@ entry:
 
 define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -35,7 +35,7 @@ entry:
 
 define void @test_igesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -52,7 +52,7 @@ entry:
 
 define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igesc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesigesi.ll b/test/CodeGen/PowerPC/testComparesigesi.ll
index 018fb940a2c..7efc8ae8245 100644
--- a/test/CodeGen/PowerPC/testComparesigesi.ll
+++ b/test/CodeGen/PowerPC/testComparesigesi.ll
@@ -9,7 +9,7 @@
 
 define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -22,7 +22,7 @@ entry:
 
 define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -35,7 +35,7 @@ entry:
 
 define void @test_igesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -52,7 +52,7 @@ entry:
 
 define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igesi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesigesll.ll b/test/CodeGen/PowerPC/testComparesigesll.ll
index 8ce71c0fd9c..30efe3da3e9 100644
--- a/test/CodeGen/PowerPC/testComparesigesll.ll
+++ b/test/CodeGen/PowerPC/testComparesigesll.ll
@@ -9,7 +9,7 @@
 
 define signext i32 @test_igesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igesll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
 ; CHECK-NEXT:    rldicl r6, r4, 1, 63
 ; CHECK-NEXT:    subfc r3, r4, r3
@@ -23,7 +23,7 @@ entry:
 
 define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igesll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
 ; CHECK-NEXT:    rldicl r6, r4, 1, 63
 ; CHECK-NEXT:    subfc r3, r4, r3
@@ -38,7 +38,7 @@ entry:
 
 define signext i32 @test_igesll_z(i64 %a) {
 ; CHECK-LABEL: test_igesll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -50,7 +50,7 @@ entry:
 
 define signext i32 @test_igesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_igesll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    blr
@@ -62,7 +62,7 @@ entry:
 
 define void @test_igesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igesll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:    sradi r6, r3, 63
 ; CHECK:    subfc r3, r4, r3
 ; CHECK:    rldicl r3, r4, 1, 63
@@ -78,7 +78,7 @@ entry:
 
 define void @test_igesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igesll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r3, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subfc r3, r4, r3
@@ -97,7 +97,7 @@ entry:
 
 define void @test_igesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_igesll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -113,7 +113,7 @@ entry:
 
 define void @test_igesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_igesll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesigess.ll b/test/CodeGen/PowerPC/testComparesigess.ll
index 8773d423a58..231a26c916d 100644
--- a/test/CodeGen/PowerPC/testComparesigess.ll
+++ b/test/CodeGen/PowerPC/testComparesigess.ll
@@ -9,7 +9,7 @@
 
 define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -22,7 +22,7 @@ entry:
 
 define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -35,7 +35,7 @@ entry:
 
 define void @test_igess_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -52,7 +52,7 @@ entry:
 
 define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igess_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesigtsc.ll b/test/CodeGen/PowerPC/testComparesigtsc.ll
index 9af61599398..8009043c45d 100644
--- a/test/CodeGen/PowerPC/testComparesigtsc.ll
+++ b/test/CodeGen/PowerPC/testComparesigtsc.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igtsc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
 ; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
 ; CHECK-NEXT:    blr
@@ -23,7 +23,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igtsc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -37,7 +37,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsc_z(i8 signext %a) {
 ; CHECK-LABEL: test_igtsc_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
@@ -62,7 +62,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igtsc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r4, r3
 ; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
 entry:
@@ -75,7 +75,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igtsc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r4, r3
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
 entry:
@@ -89,7 +89,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsc_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_igtsc_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesigtsi.ll b/test/CodeGen/PowerPC/testComparesigtsi.ll
index f7a32c9c49b..77dfc3583f1 100644
--- a/test/CodeGen/PowerPC/testComparesigtsi.ll
+++ b/test/CodeGen/PowerPC/testComparesigtsi.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igtsi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
 ; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
 ; CHECK-NEXT:    blr
@@ -23,7 +23,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igtsi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -37,7 +37,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsi_z(i32 signext %a) {
 ; CHECK-LABEL: test_igtsi_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
@@ -62,7 +62,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igtsi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r4, r3
 ; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
 entry:
@@ -75,7 +75,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igtsi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r4, r3
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
 entry:
@@ -89,7 +89,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsi_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_igtsi_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesigtsll.ll b/test/CodeGen/PowerPC/testComparesigtsll.ll
index bd681f9e168..75314d708f5 100644
--- a/test/CodeGen/PowerPC/testComparesigtsll.ll
+++ b/test/CodeGen/PowerPC/testComparesigtsll.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igtsll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igtsll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
@@ -44,7 +44,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsll_z(i64 %a) {
 ; CHECK-LABEL: test_igtsll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
 ; CHECK-NEXT:    nor r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
@@ -70,7 +70,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igtsll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
 ; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
@@ -87,7 +87,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igtsll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
 ; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
@@ -105,7 +105,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsll_z_store(i64 %a) {
 ; CHECK-LABEL: test_igtsll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addi r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesigtss.ll b/test/CodeGen/PowerPC/testComparesigtss.ll
index 65ea0b58e78..23ddbe30f7e 100644
--- a/test/CodeGen/PowerPC/testComparesigtss.ll
+++ b/test/CodeGen/PowerPC/testComparesigtss.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igtss:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG1:r[0-9]+]], r4, r3
 ; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
 ; CHECK-NEXT:    blr
@@ -23,7 +23,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igtss_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -37,7 +37,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtss_z(i16 signext %a) {
 ; CHECK-LABEL: test_igtss_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
@@ -50,7 +50,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtss_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_igtss_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:    neg [[REG2:r[0-9]+]], r3
 ; CHECK-NEXT:    sradi r3, [[REG2]], 63
 ; CHECK-NEXT:    blr
@@ -63,7 +63,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtss_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igtss_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG1:r[0-9]+]], r4, r3
 ; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
 entry:
@@ -76,7 +76,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igtss_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r4, r3
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
 entry:
@@ -90,7 +90,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtss_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_igtss_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesilesc.ll b/test/CodeGen/PowerPC/testComparesilesc.ll
index b932867ef31..422dc3adc5d 100644
--- a/test/CodeGen/PowerPC/testComparesilesc.ll
+++ b/test/CodeGen/PowerPC/testComparesilesc.ll
@@ -9,7 +9,7 @@
 
 define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -22,7 +22,7 @@ entry:
 
 define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -35,7 +35,7 @@ entry:
 
 define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -52,7 +52,7 @@ entry:
 
 define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_ilesc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesilesi.ll b/test/CodeGen/PowerPC/testComparesilesi.ll
index 250cbc704c1..72439bd9aa3 100644
--- a/test/CodeGen/PowerPC/testComparesilesi.ll
+++ b/test/CodeGen/PowerPC/testComparesilesi.ll
@@ -9,7 +9,7 @@
 
 define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -22,7 +22,7 @@ entry:
 
 define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -35,7 +35,7 @@ entry:
 
 define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -52,7 +52,7 @@ entry:
 
 define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_ilesi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesilesll.ll b/test/CodeGen/PowerPC/testComparesilesll.ll
index 8c23dcd95cd..21b67664c30 100644
--- a/test/CodeGen/PowerPC/testComparesilesll.ll
+++ b/test/CodeGen/PowerPC/testComparesilesll.ll
@@ -9,7 +9,7 @@
 
 define signext i32 @test_ilesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ilesll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
 ; CHECK-NEXT:    rldicl r6, r3, 1, 63
 ; CHECK-NEXT:    subfc r12, r3, r4
@@ -23,7 +23,7 @@ entry:
 
 define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ilesll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
 ; CHECK-NEXT:    rldicl r6, r3, 1, 63
 ; CHECK-NEXT:    subfc r12, r3, r4
@@ -38,7 +38,7 @@ entry:
 
 define signext i32 @test_ilesll_z(i64 %a) {
 ; CHECK-LABEL: test_ilesll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
@@ -51,7 +51,7 @@ entry:
 
 define signext i32 @test_ilesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_ilesll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    sradi r3, r3, 63
@@ -64,7 +64,7 @@ entry:
 
 define void @test_ilesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ilesll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:    sradi r6, r4, 63
 ; CHECK:    subfc r4, r3, r4
 ; CHECK:    rldicl r3, r3, 1, 63
@@ -80,7 +80,7 @@ entry:
 
 define void @test_ilesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ilesll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:    sradi r6, r4, 63
 ; CHECK-DAG:    rldicl r3, r3, 1, 63
 ; CHECK-DAG:    subfc r4, r3, r4
@@ -97,7 +97,7 @@ entry:
 
 define void @test_ilesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_ilesll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addi r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -114,7 +114,7 @@ entry:
 
 define void @test_ilesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_ilesll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addi r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesiless.ll b/test/CodeGen/PowerPC/testComparesiless.ll
index 5e4a455990d..c85ff6078e7 100644
--- a/test/CodeGen/PowerPC/testComparesiless.ll
+++ b/test/CodeGen/PowerPC/testComparesiless.ll
@@ -9,7 +9,7 @@
 
 define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -22,7 +22,7 @@ entry:
 
 define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -35,7 +35,7 @@ entry:
 
 define void @test_iless_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -52,7 +52,7 @@ entry:
 
 define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iless_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesiltsc.ll b/test/CodeGen/PowerPC/testComparesiltsc.ll
index d4f267cc12a..08a023302bd 100644
--- a/test/CodeGen/PowerPC/testComparesiltsc.ll
+++ b/test/CodeGen/PowerPC/testComparesiltsc.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_iltsc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
 ; CHECK-NEXT:    blr
@@ -24,7 +24,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_iltsc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -48,7 +48,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_iltsc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r3, r4
 ; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
 entry:
@@ -61,7 +61,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_iltsc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r3, r4
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
 entry:
diff --git a/test/CodeGen/PowerPC/testComparesiltsi.ll b/test/CodeGen/PowerPC/testComparesiltsi.ll
index 191afd20eaa..39f37387f53 100644
--- a/test/CodeGen/PowerPC/testComparesiltsi.ll
+++ b/test/CodeGen/PowerPC/testComparesiltsi.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_iltsi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
 ; CHECK-NEXT:    blr
@@ -24,7 +24,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_iltsi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -37,7 +37,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltsi_sext_z(i32 signext %a) {
 ; CHECK-LABEL: test_iltsi_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    srawi r3, r3, 31
 ; CHECK-NEXT:    blr
 entry:
@@ -49,7 +49,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_iltsi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r3, r4
 ; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
 entry:
@@ -62,7 +62,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_iltsi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r3, r4
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
 entry:
diff --git a/test/CodeGen/PowerPC/testComparesiltsll.ll b/test/CodeGen/PowerPC/testComparesiltsll.ll
index a0452954917..4152b8556df 100644
--- a/test/CodeGen/PowerPC/testComparesiltsll.ll
+++ b/test/CodeGen/PowerPC/testComparesiltsll.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iltsll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
@@ -27,7 +27,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iltsll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
@@ -44,7 +44,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltsll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_iltsll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -56,7 +56,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iltsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iltsll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
 ; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
@@ -73,7 +73,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iltsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iltsll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
 ; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
diff --git a/test/CodeGen/PowerPC/testComparesiltss.ll b/test/CodeGen/PowerPC/testComparesiltss.ll
index 4d66fad13ad..db5a60dfb66 100644
--- a/test/CodeGen/PowerPC/testComparesiltss.ll
+++ b/test/CodeGen/PowerPC/testComparesiltss.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iltss:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
 ; CHECK-NEXT:    blr
@@ -24,7 +24,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iltss_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -48,7 +48,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iltss_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iltss_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r3, r4
 ; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
 entry:
@@ -61,7 +61,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iltss_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r3, r4
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
 entry:
diff --git a/test/CodeGen/PowerPC/testComparesinesll.ll b/test/CodeGen/PowerPC/testComparesinesll.ll
index 5f49d2290a6..cccff24c504 100644
--- a/test/CodeGen/PowerPC/testComparesinesll.ll
+++ b/test/CodeGen/PowerPC/testComparesinesll.ll
@@ -10,7 +10,7 @@
 
 define signext i32 @test_inesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_inesll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
@@ -23,7 +23,7 @@ entry:
 
 define signext i32 @test_inesll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_inesll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    subfe r3, r3, r3
@@ -36,7 +36,7 @@ entry:
 
 define signext i32 @test_inesll_z(i64 %a) {
 ; CHECK-LABEL: test_inesll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
 ; CHECK-NEXT:    blr
@@ -48,7 +48,7 @@ entry:
 
 define signext i32 @test_inesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_inesll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    blr
@@ -60,7 +60,7 @@ entry:
 
 define void @test_inesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_inesll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -77,7 +77,7 @@ entry:
 
 define void @test_inesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_inesll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -94,7 +94,7 @@ entry:
 
 define void @test_inesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_inesll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addic r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -110,7 +110,7 @@ entry:
 
 define void @test_inesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_inesll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesineuc.ll b/test/CodeGen/PowerPC/testComparesineuc.ll
index 3f99fbcd212..c478041b19e 100644
--- a/test/CodeGen/PowerPC/testComparesineuc.ll
+++ b/test/CodeGen/PowerPC/testComparesineuc.ll
@@ -9,7 +9,7 @@
 
 define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ineuc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -23,7 +23,7 @@ entry:
 
 define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ineuc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -38,7 +38,7 @@ entry:
 
 define signext i32 @test_ineuc_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_ineuc_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -51,7 +51,7 @@ entry:
 
 define signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_ineuc_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -65,7 +65,7 @@ entry:
 
 define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ineuc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -83,7 +83,7 @@ entry:
 
 define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_ineuc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -102,7 +102,7 @@ entry:
 
 define void @test_ineuc_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_ineuc_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -119,7 +119,7 @@ entry:
 
 define void @test_ineuc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_ineuc_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
diff --git a/test/CodeGen/PowerPC/testComparesineull.ll b/test/CodeGen/PowerPC/testComparesineull.ll
index 6d645f5d33b..ba388a45fad 100644
--- a/test/CodeGen/PowerPC/testComparesineull.ll
+++ b/test/CodeGen/PowerPC/testComparesineull.ll
@@ -10,7 +10,7 @@
 
 define signext i32 @test_ineull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ineull:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
@@ -23,7 +23,7 @@ entry:
 
 define signext i32 @test_ineull_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ineull_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    subfe r3, r3, r3
@@ -36,7 +36,7 @@ entry:
 
 define signext i32 @test_ineull_z(i64 %a) {
 ; CHECK-LABEL: test_ineull_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
 ; CHECK-NEXT:    blr
@@ -48,7 +48,7 @@ entry:
 
 define signext i32 @test_ineull_sext_z(i64 %a) {
 ; CHECK-LABEL: test_ineull_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    blr
@@ -60,7 +60,7 @@ entry:
 
 define void @test_ineull_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ineull_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -77,7 +77,7 @@ entry:
 
 define void @test_ineull_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_ineull_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -94,7 +94,7 @@ entry:
 
 define void @test_ineull_z_store(i64 %a) {
 ; CHECK-LABEL: test_ineull_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addic r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -110,7 +110,7 @@ entry:
 
 define void @test_ineull_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_ineull_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesineus.ll b/test/CodeGen/PowerPC/testComparesineus.ll
index 38c62f7dc3f..a78671b6407 100644
--- a/test/CodeGen/PowerPC/testComparesineus.ll
+++ b/test/CodeGen/PowerPC/testComparesineus.ll
@@ -10,7 +10,7 @@
 
 define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ineus:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -24,7 +24,7 @@ entry:
 
 define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ineus_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -39,7 +39,7 @@ entry:
 
 define signext i32 @test_ineus_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_ineus_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -52,7 +52,7 @@ entry:
 
 define signext i32 @test_ineus_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_ineus_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -66,7 +66,7 @@ entry:
 
 define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ineus_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -84,7 +84,7 @@ entry:
 
 define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_ineus_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -103,7 +103,7 @@ entry:
 
 define void @test_ineus_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_ineus_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -120,7 +120,7 @@ entry:
 
 define void @test_ineus_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_ineus_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
diff --git a/test/CodeGen/PowerPC/testCompareslleqsc.ll b/test/CodeGen/PowerPC/testCompareslleqsc.ll
index 8559665f53d..43fb358efef 100644
--- a/test/CodeGen/PowerPC/testCompareslleqsc.ll
+++ b/test/CodeGen/PowerPC/testCompareslleqsc.ll
@@ -12,7 +12,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lleqsc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lleqsc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -41,7 +41,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsc_z(i8 signext %a) {
 ; CHECK-LABEL: test_lleqsc_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -54,7 +54,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsc_sext_z(i8 signext %a) {
 ; CHECK-LABEL: test_lleqsc_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -68,7 +68,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lleqsc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -86,7 +86,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lleqsc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -105,7 +105,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsc_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_lleqsc_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -122,7 +122,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsc_sext_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_lleqsc_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testCompareslleqsi.ll b/test/CodeGen/PowerPC/testCompareslleqsi.ll
index 131c088a8ab..ae8dffb1e22 100644
--- a/test/CodeGen/PowerPC/testCompareslleqsi.ll
+++ b/test/CodeGen/PowerPC/testCompareslleqsi.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lleqsi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -25,7 +25,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lleqsi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -40,7 +40,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsi_z(i32 signext %a) {
 ; CHECK-LABEL: test_lleqsi_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -53,7 +53,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsi_sext_z(i32 signext %a) {
 ; CHECK-LABEL: test_lleqsi_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -67,7 +67,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lleqsi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -85,7 +85,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lleqsi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -104,7 +104,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsi_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_lleqsi_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -122,7 +122,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsi_sext_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_lleqsi_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testCompareslleqsll.ll b/test/CodeGen/PowerPC/testCompareslleqsll.ll
index 8484586c160..89ef960a6f9 100644
--- a/test/CodeGen/PowerPC/testCompareslleqsll.ll
+++ b/test/CodeGen/PowerPC/testCompareslleqsll.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lleqsll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
@@ -25,7 +25,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lleqsll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    subfe r3, r3, r3
@@ -39,7 +39,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsll_z(i64 %a) {
 ; CHECK-LABEL: test_lleqsll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
 ; CHECK-NEXT:    blr
@@ -52,7 +52,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqsll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_lleqsll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    blr
@@ -65,7 +65,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lleqsll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -83,7 +83,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lleqsll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -101,7 +101,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsll_z_store(i64 %a) {
 ; CHECK-LABEL: test_lleqsll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -118,7 +118,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqsll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_lleqsll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testCompareslleqss.ll b/test/CodeGen/PowerPC/testCompareslleqss.ll
index 1eac65f268c..5d1945d73e3 100644
--- a/test/CodeGen/PowerPC/testCompareslleqss.ll
+++ b/test/CodeGen/PowerPC/testCompareslleqss.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqss(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_lleqss:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -25,7 +25,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_lleqss_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -40,7 +40,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqss_z(i16 signext %a) {
 ; CHECK-LABEL: test_lleqss_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -53,7 +53,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lleqss_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_lleqss_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -67,7 +67,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqss_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_lleqss_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -85,7 +85,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_lleqss_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -104,7 +104,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqss_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_lleqss_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -121,7 +121,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lleqss_sext_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_lleqss_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesllequc.ll b/test/CodeGen/PowerPC/testComparesllequc.ll
index a1733b86516..0f5d4c6f287 100644
--- a/test/CodeGen/PowerPC/testComparesllequc.ll
+++ b/test/CodeGen/PowerPC/testComparesllequc.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llequc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -25,7 +25,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llequc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -40,7 +40,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequc_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_llequc_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -53,7 +53,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_llequc_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -67,7 +67,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llequc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -85,7 +85,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llequc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -104,7 +104,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequc_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_llequc_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -121,7 +121,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_llequc_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesllequi.ll b/test/CodeGen/PowerPC/testComparesllequi.ll
index ab3176d49ac..350168e0e6c 100644
--- a/test/CodeGen/PowerPC/testComparesllequi.ll
+++ b/test/CodeGen/PowerPC/testComparesllequi.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llequi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -25,7 +25,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llequi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -40,7 +40,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequi_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_llequi_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -53,7 +53,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequi_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_llequi_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -67,7 +67,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llequi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -85,7 +85,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llequi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -104,7 +104,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequi_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llequi_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -121,7 +121,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequi_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llequi_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesllequll.ll b/test/CodeGen/PowerPC/testComparesllequll.ll
index 8ca9767e879..7d1fe527e8a 100644
--- a/test/CodeGen/PowerPC/testComparesllequll.ll
+++ b/test/CodeGen/PowerPC/testComparesllequll.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llequll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
@@ -25,7 +25,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llequll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    subfe r3, r3, r3
@@ -39,7 +39,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequll_z(i64 %a) {
 ; CHECK-LABEL: test_llequll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
 ; CHECK-NEXT:    blr
@@ -52,7 +52,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_llequll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    blr
@@ -65,7 +65,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llequll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -83,7 +83,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llequll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -101,7 +101,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequll_z_store(i64 %a) {
 ; CHECK-LABEL: test_llequll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -118,7 +118,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llequll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addic r3, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesllequs.ll b/test/CodeGen/PowerPC/testComparesllequs.ll
index 0cc2b43bdff..cc215216dfc 100644
--- a/test/CodeGen/PowerPC/testComparesllequs.ll
+++ b/test/CodeGen/PowerPC/testComparesllequs.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llequs:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -25,7 +25,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llequs_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
@@ -40,7 +40,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequs_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_llequs_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    blr
@@ -53,7 +53,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llequs_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_llequs_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    neg r3, r3
@@ -67,7 +67,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llequs_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -85,7 +85,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llequs_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
@@ -104,7 +104,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequs_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_llequs_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -121,7 +121,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llequs_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_llequs_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesllgesc.ll b/test/CodeGen/PowerPC/testComparesllgesc.ll
index 744ef362abf..82f54cd6b1b 100644
--- a/test/CodeGen/PowerPC/testComparesllgesc.ll
+++ b/test/CodeGen/PowerPC/testComparesllgesc.ll
@@ -9,7 +9,7 @@
 
 define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -22,7 +22,7 @@ entry:
 
 define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -35,7 +35,7 @@ entry:
 
 define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -52,7 +52,7 @@ entry:
 
 define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_llgesc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesllgesi.ll b/test/CodeGen/PowerPC/testComparesllgesi.ll
index eec3e671b8f..82c1fa11b8b 100644
--- a/test/CodeGen/PowerPC/testComparesllgesi.ll
+++ b/test/CodeGen/PowerPC/testComparesllgesi.ll
@@ -9,7 +9,7 @@
 
 define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -22,7 +22,7 @@ entry:
 
 define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -35,7 +35,7 @@ entry:
 
 define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -52,7 +52,7 @@ entry:
 
 define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_llgesi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesllgesll.ll b/test/CodeGen/PowerPC/testComparesllgesll.ll
index 9fa5985ba6e..6fb53977a55 100644
--- a/test/CodeGen/PowerPC/testComparesllgesll.ll
+++ b/test/CodeGen/PowerPC/testComparesllgesll.ll
@@ -9,7 +9,7 @@
 
 define i64 @test_llgesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgesll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
 ; CHECK-NEXT:    rldicl r6, r4, 1, 63
 ; CHECK-NEXT:    subfc r3, r4, r3
@@ -23,7 +23,7 @@ entry:
 
 define i64 @test_llgesll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgesll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
 ; CHECK-NEXT:    rldicl r6, r4, 1, 63
 ; CHECK-NEXT:    subfc r3, r4, r3
@@ -38,7 +38,7 @@ entry:
 
 define i64 @test_llgesll_z(i64 %a) {
 ; CHECK-LABEL: test_llgesll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -50,7 +50,7 @@ entry:
 
 define i64 @test_llgesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_llgesll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    not r3, r3
 ; CHECK-NEXT:    blr
@@ -62,7 +62,7 @@ entry:
 
 define void @test_llgesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgesll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:    sradi r6, r3, 63
 ; CHECK:    subfc r3, r4, r3
 ; CHECK:    rldicl r3, r4, 1, 63
@@ -78,7 +78,7 @@ entry:
 
 define void @test_llgesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgesll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r6, r3, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subfc r3, r4, r3
@@ -97,7 +97,7 @@ entry:
 
 define void @test_llgesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgesll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -113,7 +113,7 @@ entry:
 
 define void @test_llgesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgesll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesllgess.ll b/test/CodeGen/PowerPC/testComparesllgess.ll
index 04b07b2200e..1206339a23b 100644
--- a/test/CodeGen/PowerPC/testComparesllgess.ll
+++ b/test/CodeGen/PowerPC/testComparesllgess.ll
@@ -9,7 +9,7 @@
 
 define i64 @test_llgess(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -22,7 +22,7 @@ entry:
 
 define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -35,7 +35,7 @@ entry:
 
 define void @test_llgess_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -52,7 +52,7 @@ entry:
 
 define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llgess_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesllgtsll.ll b/test/CodeGen/PowerPC/testComparesllgtsll.ll
index 2467468afac..0dc1374374f 100644
--- a/test/CodeGen/PowerPC/testComparesllgtsll.ll
+++ b/test/CodeGen/PowerPC/testComparesllgtsll.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgtsll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
@@ -26,7 +26,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgtsll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
@@ -44,7 +44,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtsll_z(i64 %a) {
 ; CHECK-LABEL: test_llgtsll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
 ; CHECK-NEXT:    nor r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
@@ -70,7 +70,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgtsll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
 ; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
@@ -87,7 +87,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgtsll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
 ; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
@@ -105,7 +105,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtsll_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgtsll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addi r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesllgtus.ll b/test/CodeGen/PowerPC/testComparesllgtus.ll
index 8d06b4b3790..3758e8e097c 100644
--- a/test/CodeGen/PowerPC/testComparesllgtus.ll
+++ b/test/CodeGen/PowerPC/testComparesllgtus.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgtus:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
 ; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
 ; CHECK-NEXT:    blr
@@ -23,7 +23,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgtus_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -36,7 +36,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtus_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_llgtus_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -50,7 +50,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtus_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_llgtus_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -65,7 +65,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgtus_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r4, r3
 ; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
 entry:
@@ -78,7 +78,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgtus_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r4, r3
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
 entry:
@@ -91,7 +91,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtus_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_llgtus_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -109,7 +109,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtus_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_llgtus_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
diff --git a/test/CodeGen/PowerPC/testCompareslllesc.ll b/test/CodeGen/PowerPC/testCompareslllesc.ll
index cb564cc721b..f9352990f2c 100644
--- a/test/CodeGen/PowerPC/testCompareslllesc.ll
+++ b/test/CodeGen/PowerPC/testCompareslllesc.ll
@@ -10,7 +10,7 @@
 
 define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -23,7 +23,7 @@ entry:
 
 define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -36,7 +36,7 @@ entry:
 
 define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -53,7 +53,7 @@ entry:
 
 define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_lllesc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testCompareslllesi.ll b/test/CodeGen/PowerPC/testCompareslllesi.ll
index d39f61fbd88..42062692a08 100644
--- a/test/CodeGen/PowerPC/testCompareslllesi.ll
+++ b/test/CodeGen/PowerPC/testCompareslllesi.ll
@@ -10,7 +10,7 @@
 
 define i64 @test_lllesi(i32 signext %a, i32 signext %b)  {
 ; CHECK-LABEL: test_lllesi:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -23,7 +23,7 @@ entry:
 
 define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b)  {
 ; CHECK-LABEL: test_lllesi_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -36,7 +36,7 @@ entry:
 
 define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lllesi_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -53,7 +53,7 @@ entry:
 
 define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_lllesi_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testCompareslllesll.ll b/test/CodeGen/PowerPC/testCompareslllesll.ll
index 375bd2295a7..8db1ee19ebb 100644
--- a/test/CodeGen/PowerPC/testCompareslllesll.ll
+++ b/test/CodeGen/PowerPC/testCompareslllesll.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lllesll(i64 %a, i64 %b)  {
 ; CHECK-LABEL: test_lllesll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
 ; CHECK-NEXT:    rldicl r6, r3, 1, 63
 ; CHECK-NEXT:    subfc r12, r3, r4
@@ -25,7 +25,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lllesll_sext(i64 %a, i64 %b)  {
 ; CHECK-LABEL: test_lllesll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
 ; CHECK-NEXT:    rldicl r6, r3, 1, 63
 ; CHECK-NEXT:    subfc r12, r3, r4
@@ -41,7 +41,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lllesll_z(i64 %a)  {
 ; CHECK-LABEL: test_lllesll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
@@ -55,7 +55,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_lllesll_sext_z(i64 %a)  {
 ; CHECK-LABEL: test_lllesll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    sradi r3, r3, 63
@@ -69,7 +69,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lllesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lllesll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:    sradi r6, r4, 63
 ; CHECK:    subfc r4, r3, r4
 ; CHECK:    rldicl r3, r3, 1, 63
@@ -86,7 +86,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lllesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_lllesll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:    sradi r6, r4, 63
 ; CHECK-DAG:    rldicl r3, r3, 1, 63
 ; CHECK-DAG:    subfc r4, r3, r4
@@ -104,7 +104,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lllesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_lllesll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addi r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -122,7 +122,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_lllesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_lllesll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addi r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesllless.ll b/test/CodeGen/PowerPC/testComparesllless.ll
index 4971fb75900..a6f3b5e3988 100644
--- a/test/CodeGen/PowerPC/testComparesllless.ll
+++ b/test/CodeGen/PowerPC/testComparesllless.ll
@@ -10,7 +10,7 @@
 
 define i64 @test_llless(i16 signext %a, i16 signext %b)  {
 ; CHECK-LABEL: test_llless:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -23,7 +23,7 @@ entry:
 
 define i64 @test_llless_sext(i16 signext %a, i16 signext %b)  {
 ; CHECK-LABEL: test_llless_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    addi r3, r3, -1
@@ -36,7 +36,7 @@ entry:
 
 define void @test_llless_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llless_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -53,7 +53,7 @@ entry:
 
 define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_llless_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
diff --git a/test/CodeGen/PowerPC/testComparesllltsll.ll b/test/CodeGen/PowerPC/testComparesllltsll.ll
index 887c14faf7b..3e37daf046f 100644
--- a/test/CodeGen/PowerPC/testComparesllltsll.ll
+++ b/test/CodeGen/PowerPC/testComparesllltsll.ll
@@ -11,7 +11,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llltsll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
@@ -27,7 +27,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llltsll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
 ; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
 ; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
@@ -44,7 +44,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltsll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_llltsll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
@@ -56,7 +56,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llltsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llltsll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
 ; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
@@ -73,7 +73,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llltsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llltsll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
 ; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
diff --git a/test/CodeGen/PowerPC/testComparesllltuc.ll b/test/CodeGen/PowerPC/testComparesllltuc.ll
index a02452554b5..a8244e757b1 100644
--- a/test/CodeGen/PowerPC/testComparesllltuc.ll
+++ b/test/CodeGen/PowerPC/testComparesllltuc.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llltuc:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
 ; CHECK-NEXT:    blr
@@ -23,7 +23,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llltuc_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -36,7 +36,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llltuc_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[2-9]+]], r3, r4
 ; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
 entry:
@@ -49,7 +49,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llltuc_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r3, r4
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
 entry:
diff --git a/test/CodeGen/PowerPC/testComparesllltui.ll b/test/CodeGen/PowerPC/testComparesllltui.ll
index bea180168da..e785942b3c9 100644
--- a/test/CodeGen/PowerPC/testComparesllltui.ll
+++ b/test/CodeGen/PowerPC/testComparesllltui.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llltui:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NOT:     clrldi
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
@@ -24,7 +24,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llltui_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -37,7 +37,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltui_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_llltui_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    blr
 entry:
@@ -47,7 +47,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltui_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_llltui_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    blr
 entry:
@@ -57,7 +57,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llltui_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NOT:     clrldi
 ; CHECK:         sub [[REG:r[2-9]+]], r3, r4
 ; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
@@ -71,7 +71,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llltui_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NOT:     clrldi
 ; CHECK:         sub [[REG:r[0-9]+]], r3, r4
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
@@ -85,7 +85,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llltui_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llltui_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         li [[REG:r[0-9]+]], 0
 ; CHECK:         stw [[REG]], 0(r3)
 ; CHECK-NEXT:    blr
@@ -97,7 +97,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llltui_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llltui_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         li [[REG:r[0-9]+]], 0
 ; CHECK:         stw [[REG]], 0(r3)
 ; CHECK-NEXT:    blr
diff --git a/test/CodeGen/PowerPC/testComparesllltus.ll b/test/CodeGen/PowerPC/testComparesllltus.ll
index 713bc220442..e997d0aa8b8 100644
--- a/test/CodeGen/PowerPC/testComparesllltus.ll
+++ b/test/CodeGen/PowerPC/testComparesllltus.ll
@@ -10,7 +10,7 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llltus:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
 ; CHECK-NEXT:    blr
@@ -23,7 +23,7 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llltus_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
 ; CHECK-NEXT:    sradi r3, [[REG]], 63
 ; CHECK-NEXT:    blr
@@ -48,7 +48,7 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llltus_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK:         sub [[REG:r[0-9]+]], r3, r4
 ; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
 entry:
diff --git a/test/CodeGen/PowerPC/testComparesllnesll.ll b/test/CodeGen/PowerPC/testComparesllnesll.ll
index 6b2b662dcc7..cdd272f57bd 100644
--- a/test/CodeGen/PowerPC/testComparesllnesll.ll
+++ b/test/CodeGen/PowerPC/testComparesllnesll.ll
@@ -10,7 +10,7 @@
 
 define i64 @test_llnesll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llnesll:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
@@ -23,7 +23,7 @@ entry:
 
 define i64 @test_llnesll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llnesll_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    subfe r3, r3, r3
@@ -36,7 +36,7 @@ entry:
 
 define i64 @test_llnesll_z(i64 %a) {
 ; CHECK-LABEL: test_llnesll_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
 ; CHECK-NEXT:    blr
@@ -48,7 +48,7 @@ entry:
 
 define i64 @test_llnesll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_llnesll_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    blr
@@ -60,7 +60,7 @@ entry:
 
 define void @test_llnesll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llnesll_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -77,7 +77,7 @@ entry:
 
 define void @test_llnesll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llnesll_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -94,7 +94,7 @@ entry:
 
 define void @test_llnesll_z_store(i64 %a) {
 ; CHECK-LABEL: test_llnesll_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addic r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -110,7 +110,7 @@ entry:
 
 define void @test_llnesll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llnesll_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/testComparesllneull.ll b/test/CodeGen/PowerPC/testComparesllneull.ll
index 0cf47e4ac03..7956881f495 100644
--- a/test/CodeGen/PowerPC/testComparesllneull.ll
+++ b/test/CodeGen/PowerPC/testComparesllneull.ll
@@ -10,7 +10,7 @@
 
 define i64 @test_llneull(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llneull:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
@@ -23,7 +23,7 @@ entry:
 
 define i64 @test_llneull_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llneull_sext:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    subfe r3, r3, r3
@@ -36,7 +36,7 @@ entry:
 
 define i64 @test_llneull_z(i64 %a) {
 ; CHECK-LABEL: test_llneull_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addic r4, r3, -1
 ; CHECK-NEXT:    subfe r3, r4, r3
 ; CHECK-NEXT:    blr
@@ -48,7 +48,7 @@ entry:
 
 define i64 @test_llneull_sext_z(i64 %a) {
 ; CHECK-LABEL: test_llneull_sext_z:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    subfe r3, r3, r3
 ; CHECK-NEXT:    blr
@@ -60,7 +60,7 @@ entry:
 
 define void @test_llneull_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llneull_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -77,7 +77,7 @@ entry:
 
 define void @test_llneull_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llneull_sext_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    xor r3, r3, r4
 ; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
@@ -94,7 +94,7 @@ entry:
 
 define void @test_llneull_z_store(i64 %a) {
 ; CHECK-LABEL: test_llneull_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    addic r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
@@ -110,7 +110,7 @@ entry:
 
 define void @test_llneull_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llneull_sext_z_store:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subfic r3, r3, 0
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
diff --git a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
index f42f7d11783..8f3864ff268 100644
--- a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
+++ b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
@@ -8,7 +8,7 @@ define <1 x i128> @out_of_bounds_insertelement(<1 x i128> %x, i128 %val) nounwin
        %result = add <1 x i128> %x, %tmpvec
        ret <1 x i128> %result
 ; CHECK-LABEL: @out_of_bounds_insertelement
-; CHECK: # BB#0:
+; CHECK: # %bb.0:
 ; CHECK-NEXT: blr
 }
 
diff --git a/test/CodeGen/PowerPC/vec_extract_p9.ll b/test/CodeGen/PowerPC/vec_extract_p9.ll
index b07c905ceec..7e397f54684 100644
--- a/test/CodeGen/PowerPC/vec_extract_p9.ll
+++ b/test/CodeGen/PowerPC/vec_extract_p9.ll
@@ -4,12 +4,12 @@
 
 define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test1:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test1:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 56
 ; CHECK-BE-NEXT:    blr
@@ -21,12 +21,12 @@ entry:
 
 define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test2:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    extsb 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test2:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
 ; CHECK-BE-NEXT:    extsb 3, 3
 ; CHECK-BE-NEXT:    blr
@@ -38,13 +38,13 @@ entry:
 
 define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test3:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test3:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 48
@@ -57,13 +57,13 @@ entry:
 
 define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test4:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsh 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test4:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    extsh 3, 3
@@ -76,12 +76,12 @@ entry:
 
 define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test5:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test5:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    blr
@@ -93,13 +93,13 @@ entry:
 
 define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test6:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test6:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    extsw 3, 3
@@ -113,13 +113,13 @@ entry:
 ; Test with immediate index
 define zeroext i8 @test7(<16 x i8> %a) {
 ; CHECK-LE-LABEL: test7:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 1
 ; CHECK-LE-NEXT:    vextubrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test7:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 1
 ; CHECK-BE-NEXT:    vextublx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 56
@@ -132,13 +132,13 @@ entry:
 
 define zeroext i16 @test8(<8 x i16> %a) {
 ; CHECK-LE-LABEL: test8:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 2
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test8:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 2
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 48
@@ -151,12 +151,12 @@ entry:
 
 define zeroext i32 @test9(<4 x i32> %a) {
 ; CHECK-LE-LABEL: test9:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 12
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test9:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 12
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    blr
diff --git a/test/CodeGen/PowerPC/vec_extract_p9_2.ll b/test/CodeGen/PowerPC/vec_extract_p9_2.ll
index 9734a88fdec..f2ce7924ed9 100644
--- a/test/CodeGen/PowerPC/vec_extract_p9_2.ll
+++ b/test/CodeGen/PowerPC/vec_extract_p9_2.ll
@@ -4,13 +4,13 @@
 
 define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) {
 ; CHECK-LE-LABEL: test_add1:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    rlwinm 3, 3, 0, 24, 31
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add1:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
 ; CHECK-BE-NEXT:    rlwinm 3, 3, 0, 24, 31
@@ -26,13 +26,13 @@ entry:
 
 define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) {
 ; CHECK-LE-LABEL: test_add2:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    extsb 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add2:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
 ; CHECK-BE-NEXT:    extsb 3, 3
@@ -48,14 +48,14 @@ entry:
 
 define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) {
 ; CHECK-LE-LABEL: test_add3:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    rlwinm 3, 3, 0, 16, 31
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add3:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
@@ -72,14 +72,14 @@ entry:
 
 define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) {
 ; CHECK-LE-LABEL: test_add4:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    extsh 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add4:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
@@ -96,14 +96,14 @@ entry:
 
 define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) {
 ; CHECK-LE-LABEL: test_add5:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    clrldi 3, 3, 32
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add5:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
@@ -117,14 +117,14 @@ entry:
 
 define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) {
 ; CHECK-LE-LABEL: test_add6:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add6:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
@@ -139,11 +139,11 @@ entry:
 ; When extracting word element 2 on LE, it's better to use mfvsrwz rather than vextuwrx
 define zeroext i32 @test7(<4 x i32> %a) {
 ; CHECK-LE-LABEL: test7:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrwz 3, 34
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test7:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 8
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    blr
@@ -154,13 +154,13 @@ entry:
 
 define zeroext i32 @testadd_7(<4 x i32> %a, i32 zeroext %c) {
 ; CHECK-LE-LABEL: testadd_7:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrwz 3, 34
 ; CHECK-LE-NEXT:    add 3, 3, 5
 ; CHECK-LE-NEXT:    clrldi 3, 3, 32
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: testadd_7:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 8
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 5
@@ -174,12 +174,12 @@ entry:
 
 define signext i32 @test8(<4 x i32> %a) {
 ; CHECK-LE-LABEL: test8:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrwz 3, 34
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test8:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 8
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    extsw 3, 3
@@ -191,13 +191,13 @@ entry:
 
 define signext i32 @testadd_8(<4 x i32> %a, i32 signext %c) {
 ; CHECK-LE-LABEL: testadd_8:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    mfvsrwz 3, 34
 ; CHECK-LE-NEXT:    add 3, 3, 5
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: testadd_8:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 8
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 5
@@ -212,13 +212,13 @@ entry:
 ; When extracting word element 1 on BE, it's better to use mfvsrwz rather than vextuwlx
 define signext i32 @test9(<4 x i32> %a) {
 ; CHECK-LE-LABEL: test9:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 4
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test9:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mfvsrwz 3, 34
 ; CHECK-BE-NEXT:    extsw 3, 3
 ; CHECK-BE-NEXT:    blr
@@ -229,14 +229,14 @@ entry:
 
 define signext i32 @testadd_9(<4 x i32> %a, i32 signext %c) {
 ; CHECK-LE-LABEL: testadd_9:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 4
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 5
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: testadd_9:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mfvsrwz 3, 34
 ; CHECK-BE-NEXT:    add 3, 3, 5
 ; CHECK-BE-NEXT:    extsw 3, 3
diff --git a/test/CodeGen/PowerPC/vec_int_ext.ll b/test/CodeGen/PowerPC/vec_int_ext.ll
index d7bed503318..1c86e38d060 100644
--- a/test/CodeGen/PowerPC/vec_int_ext.ll
+++ b/test/CodeGen/PowerPC/vec_int_ext.ll
@@ -4,11 +4,11 @@
 
 define <4 x i32> @vextsb2wLE(<16 x i8> %a) {
 ; CHECK-LE-LABEL: vextsb2wLE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsb2w 2, 2
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: vextsb2wLE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE:         vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    vextsb2w 2, 2
 ; CHECK-BE-NEXT:    blr
@@ -31,11 +31,11 @@ entry:
 
 define <2 x i64> @vextsb2dLE(<16 x i8> %a) {
 ; CHECK-LE-LABEL: vextsb2dLE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsb2d 2, 2
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: vextsb2dLE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE:         vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    vextsb2d 2, 2
 ; CHECK-BE-NEXT:    blr
@@ -52,11 +52,11 @@ entry:
 
 define <4 x i32> @vextsh2wLE(<8 x i16> %a) {
 ; CHECK-LE-LABEL: vextsh2wLE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsh2w 2, 2
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: vextsh2wLE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE:         vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    vextsh2w 2, 2
 ; CHECK-BE-NEXT:    blr
@@ -79,11 +79,11 @@ entry:
 
 define <2 x i64> @vextsh2dLE(<8 x i16> %a) {
 ; CHECK-LE-LABEL: vextsh2dLE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsh2d 2, 2
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: vextsh2dLE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE:         vperm 2, 2, 2, 3
 ; CHECK-BE-NEXT:    vextsh2d 2, 2
 ; CHECK-BE-NEXT:    blr
@@ -100,11 +100,11 @@ entry:
 
 define <2 x i64> @vextsw2dLE(<4 x i32> %a) {
 ; CHECK-LE-LABEL: vextsw2dLE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsw2d 2, 2
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: vextsw2dLE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE:         vmrgew
 ; CHECK-BE-NEXT:    vextsw2d 2, 2
 ; CHECK-BE-NEXT:    blr
@@ -121,11 +121,11 @@ entry:
 
 define <4 x i32> @vextsb2wBE(<16 x i8> %a) {
 ; CHECK-BE-LABEL: vextsb2wBE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextsb2w 2, 2
 ; CHECK-BE-NEXT:    blr
 ; CHECK-LE-LABEL: vextsb2wBE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 13
 ; CHECK-LE-NEXT:    vextsb2w 2, 2
 ; CHECK-LE-NEXT:    blr
@@ -147,11 +147,11 @@ entry:
 
 define <2 x i64> @vextsb2dBE(<16 x i8> %a) {
 ; CHECK-BE-LABEL: vextsb2dBE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextsb2d 2, 2
 ; CHECK-BE-NEXT:    blr
 ; CHECK-LE-LABEL: vextsb2dBE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 9
 ; CHECK-LE-NEXT:    vextsb2d 2, 2
 ; CHECK-LE-NEXT:    blr
@@ -167,11 +167,11 @@ entry:
 
 define <4 x i32> @vextsh2wBE(<8 x i16> %a) {
 ; CHECK-BE-LABEL: vextsh2wBE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextsh2w 2, 2
 ; CHECK-BE-NEXT:    blr
 ; CHECK-LE-LABEL: vextsh2wBE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 14
 ; CHECK-LE-NEXT:    vextsh2w 2, 2
 ; CHECK-LE-NEXT:    blr
@@ -193,11 +193,11 @@ entry:
 
 define <2 x i64> @vextsh2dBE(<8 x i16> %a) {
 ; CHECK-BE-LABEL: vextsh2dBE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextsh2d 2, 2
 ; CHECK-BE-NEXT:    blr
 ; CHECK-LE-LABEL: vextsh2dBE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 10
 ; CHECK-LE-NEXT:    vextsh2d 2, 2
 ; CHECK-LE-NEXT:    blr
@@ -213,11 +213,11 @@ entry:
 
 define <2 x i64> @vextsw2dBE(<4 x i32> %a) {
 ; CHECK-BE-LABEL: vextsw2dBE:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextsw2d 2, 2
 ; CHECK-BE-NEXT:    blr
 ; CHECK-LE-LABEL: vextsw2dBE:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 12
 ; CHECK-LE-NEXT:    vextsw2d 2, 2
 ; CHECK-LE-NEXT:    blr
@@ -233,11 +233,11 @@ entry:
 
 define <2 x i64> @vextDiffVectors(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LE-LABEL: vextDiffVectors:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NOT:     vextsw2d
 
 ; CHECK-BE-LABEL: vextDiffVectors:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NOT:     vextsw2d
 entry:
   %vecext = extractelement <4 x i32> %a, i32 0
@@ -252,11 +252,11 @@ entry:
 define <8 x i16> @testInvalidExtend(<16 x i8> %a) {
 entry:
 ; CHECK-LE-LABEL: testInvalidExtend:
-; CHECK-LE:       # BB#0: # %entry
+; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NOT:     vexts
 
 ; CHECK-BE-LABEL: testInvalidExtend:
-; CHECK-BE:       # BB#0: # %entry
+; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NOT:     vexts
 
   %vecext = extractelement <16 x i8> %a, i32 0
diff --git a/test/CodeGen/PowerPC/vec_revb.ll b/test/CodeGen/PowerPC/vec_revb.ll
index c09164bae13..00c08a1204f 100644
--- a/test/CodeGen/PowerPC/vec_revb.ll
+++ b/test/CodeGen/PowerPC/vec_revb.ll
@@ -3,7 +3,7 @@
 
 define <8 x i16> @testXXBRH(<8 x i16> %a) {
 ; CHECK-LABEL: testXXBRH:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxbrh 34, 34
 ; CHECK-NEXT:    blr
 
@@ -16,7 +16,7 @@ entry:
 
 define <4 x i32> @testXXBRW(<4 x i32> %a) {
 ; CHECK-LABEL: testXXBRW:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxbrw 34, 34
 ; CHECK-NEXT:    blr
 
@@ -29,7 +29,7 @@ entry:
 
 define <2 x double> @testXXBRD(<2 x double> %a) {
 ; CHECK-LABEL: testXXBRD:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxbrd 34, 34
 ; CHECK-NEXT:    blr
 
@@ -42,7 +42,7 @@ entry:
 
 define <1 x i128> @testXXBRQ(<1 x i128> %a) {
 ; CHECK-LABEL: testXXBRQ:
-; CHECK:       # BB#0: # %entry
+; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxbrq 34, 34
 ; CHECK-NEXT:    blr
 
diff --git a/test/CodeGen/PowerPC/vselect-constants.ll b/test/CodeGen/PowerPC/vselect-constants.ll
index 077eb2defc0..5f23c3e40de 100644
--- a/test/CodeGen/PowerPC/vselect-constants.ll
+++ b/test/CodeGen/PowerPC/vselect-constants.ll
@@ -9,7 +9,7 @@
 
 define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_C1_or_C2_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
@@ -29,7 +29,7 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
 
 define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_C1_or_C2_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; CHECK-NEXT:    addis 4, 2, .LCPI1_1@toc@ha
@@ -46,7 +46,7 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
 
 define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_Cplus1_or_C_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, 1
 ; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
@@ -60,7 +60,7 @@ define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
 
 define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI3_0@toc@l
@@ -74,7 +74,7 @@ define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
 
 define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_Cminus1_or_C_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
 ; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
@@ -91,7 +91,7 @@ define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
 
 define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI5_0@toc@l
@@ -105,7 +105,7 @@ define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
 
 define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_minus1_or_0_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, -16
 ; CHECK-NEXT:    vspltisw 4, 15
 ; CHECK-NEXT:    vsubuwm 3, 4, 3
@@ -118,7 +118,7 @@ define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {
 
 define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_minus1_or_0_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-NEXT:    blr
   %cond = icmp eq <4 x i32> %x, %y
@@ -128,7 +128,7 @@ define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
 
 define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_0_or_minus1_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, 1
 ; CHECK-NEXT:    vspltisb 4, -1
 ; CHECK-NEXT:    xxland 34, 34, 35
@@ -140,7 +140,7 @@ define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
 
 define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_0_or_minus1_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-NEXT:    xxlnor 34, 34, 34
 ; CHECK-NEXT:    blr
@@ -151,7 +151,7 @@ define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
 
 define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_1_or_0_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, 1
 ; CHECK-NEXT:    xxland 34, 34, 35
 ; CHECK-NEXT:    blr
@@ -161,7 +161,7 @@ define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
 
 define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_1_or_0_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-NEXT:    vspltisw 19, 1
 ; CHECK-NEXT:    xxland 34, 34, 51
@@ -173,7 +173,7 @@ define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
 
 define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_0_or_1_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 3, 1
 ; CHECK-NEXT:    xxlandc 34, 35, 34
 ; CHECK-NEXT:    blr
@@ -183,7 +183,7 @@ define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {
 
 define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_0_or_1_vec:
-; CHECK:       # BB#0:
+; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpequw 2, 2, 3
 ; CHECK-NEXT:    vspltisw 19, 1
 ; CHECK-NEXT:    xxlnor 0, 34, 34
author	Francis Visoiu Mistrih <francisvm@yahoo.com>	2017-12-04 17:18:51 +0000
committer	Francis Visoiu Mistrih <francisvm@yahoo.com>	2017-12-04 17:18:51 +0000
commit	ca0df55065b11f2310f55c731b2f990d09ae1c32 (patch)
tree	fff52bf80df56346069e50ec52b17a4e36907e87 /test/CodeGen/PowerPC
parent	93356784e0e357e3f1f74d565480cc9c25ea4bc9 (diff)