[CodeGen] Print register names in lowercase in both MIR and debug output

As part of the unification of the debug format and the MIR format,
always print registers as lowercase.

* Only debug printing is affected. It now follows MIR.

Differential Revision: https://reviews.llvm.org/D40417

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319187 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 13 insertions, 13 deletions

diff --git a/test/CodeGen/PowerPC/addegluecrash.ll b/test/CodeGen/PowerPC/addegluecrash.ll
index 7605340d305..f17b6dce9a9 100644
--- a/test/CodeGen/PowerPC/addegluecrash.ll
+++ b/test/CodeGen/PowerPC/addegluecrash.ll
@@ -23,7 +23,7 @@ define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* n
 ; CHECK-NEXT:    cmpld 7, 4, 5
 ; CHECK-NEXT:    mfocrf 10, 1
 ; CHECK-NEXT:    rlwinm 10, 10, 29, 31, 31
-; CHECK-NEXT:    # implicit-def: %X4
+; CHECK-NEXT:    # implicit-def: %x4
 ; CHECK-NEXT:    mr 4, 10
 ; CHECK-NEXT:    clrldi 4, 4, 32
 ; CHECK-NEXT:    std 4, 0(3)
diff --git a/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll b/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
index deacbd6a00f..c5651562f85 100644
--- a/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
+++ b/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
@@ -10,7 +10,7 @@ entry:
 lnext:
   %elementArray = load i32*, i32** %elementArrayPtr, align 8
 ; CHECK: lwz [[LDREG:[0-9]+]], 124(1)                   # 4-byte Folded Reload
-; CHECK: # implicit-def: %X[[TEMPREG:[0-9]+]]
+; CHECK: # implicit-def: %x[[TEMPREG:[0-9]+]]
   %element = load i32, i32* %elementArray, align 4
 ; CHECK: mr [[TEMPREG]], [[LDREG]]
 ; CHECK: clrldi   4, [[TEMPREG]], 32
diff --git a/test/CodeGen/PowerPC/byval-agg-info.ll b/test/CodeGen/PowerPC/byval-agg-info.ll
index df87896e375..04869665797 100644
--- a/test/CodeGen/PowerPC/byval-agg-info.ll
+++ b/test/CodeGen/PowerPC/byval-agg-info.ll
@@ -13,5 +13,5 @@ entry:
 
 ; Make sure that the MMO on the store has no offset from the byval
 ; variable itself (we used to have mem:ST8[%v+64]).
-; CHECK: STD %X5<kill>, 176, %X1; mem:ST8[%v](align=16)
+; CHECK: STD %x5<kill>, 176, %x1; mem:ST8[%v](align=16)
 
diff --git a/test/CodeGen/PowerPC/fp64-to-int16.ll b/test/CodeGen/PowerPC/fp64-to-int16.ll
index 10d58c2d766..0c5274d9426 100644
--- a/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ b/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -10,7 +10,7 @@ define i1 @Test(double %a) {
 ; CHECK-NEXT:    xori 3, 3, 65534
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 5
-; CHECK-NEXT:    # implicit-def: %X4
+; CHECK-NEXT:    # implicit-def: %x4
 ; CHECK-NEXT:    mr 4, 3
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
diff --git a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
index 5176cdcb600..4ca75a7e365 100644
--- a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
+++ b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
@@ -7,12 +7,12 @@ define signext i32 @fn1(i32 %baz) {
   %2 = zext i32 %1 to i64
   %3 = shl i64 %2, 48
   %4 = ashr exact i64 %3, 48
-; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>;
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def,dead>;
 ; CHECK: CMPLDI
 ; CHECK: BCC
 
-; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>;
-; CHECK: COPY %CR0
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def>;
+; CHECK: COPY %cr0
 ; CHECK: BCC
   %5 = icmp eq i64 %4, 0
   br i1 %5, label %foo, label %bar
@@ -26,8 +26,8 @@ bar:
 
 ; CHECK-LABEL: fn2
 define signext i32 @fn2(i64 %a, i64 %b) {
-; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def>;
-; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
+; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %cr0<imp-def>;
+; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0
 ; CHECK: BCC 12, [[CREG]]<kill>
   %1 = or i64 %b, %a
   %2 = icmp sgt i64 %1, -1
@@ -42,8 +42,8 @@ bar:
 
 ; CHECK-LABEL: fn3
 define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def>;
-; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
+; CHECK: ANDIo {{[^, ]+}}, 10, %cr0<imp-def>;
+; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0
 ; CHECK: BCC 76, [[CREG]]<kill>
   %1 = and i32 %a, 10
   %2 = icmp ne i32 %1, 0
diff --git a/test/CodeGen/PowerPC/quadint-return.ll b/test/CodeGen/PowerPC/quadint-return.ll
index 8b407849718..2cc995f3f20 100644
--- a/test/CodeGen/PowerPC/quadint-return.ll
+++ b/test/CodeGen/PowerPC/quadint-return.ll
@@ -14,6 +14,6 @@ entry:
 
 ; CHECK: ********** Function: foo
 ; CHECK: ********** FAST REGISTER ALLOCATION **********
-; CHECK: %X3<def> = COPY %vreg
-; CHECK-NEXT: %X4<def> = COPY %vreg
+; CHECK: %x3<def> = COPY %vreg
+; CHECK-NEXT: %x4<def> = COPY %vreg
 ; CHECK-NEXT: BLR