[PowerPC] MachineSSA pass to reduce the number of CR-logical operations

The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).

Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.

Differential Revision: https://reviews.llvm.org/D30431


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320584 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 212 insertions, 180 deletions

diff --git a/test/CodeGen/PowerPC/licm-remat.ll b/test/CodeGen/PowerPC/licm-remat.ll
index 393c56bcb86..f9c14052452 100644
--- a/test/CodeGen/PowerPC/licm-remat.ll
+++ b/test/CodeGen/PowerPC/licm-remat.ll
@@ -1,4 +1,5 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-reduce-cr-logicals \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 ; Test case is reduced from the snappy benchmark.
 ; Verify MachineLICM will always hoist trivially rematerializable instructions even when register pressure is high.
@@ -21,8 +22,8 @@ define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompres
 ; CHECK:       # %bb.0: # %entry
 ; CHECK:       addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
 ; CHECK-DAG:   addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l
-; CHECK-DAG:   addis 4, 2, _ZN6snappy8internalL10char_tableE@toc@ha
-; CHECK-DAG:   addi 24, 4, _ZN6snappy8internalL10char_tableE@toc@l
+; CHECK-DAG:   addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha
+; CHECK-DAG:   addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l
 ; CHECK:       b .LBB0_2
 ; CHECK:       .LBB0_2: # %for.cond
 ; CHECK-NOT:   addis {{[0-9]+}}, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
diff --git a/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/test/CodeGen/PowerPC/select-i1-vs-i1.ll
index b7beb8165fd..e8e6f99cb22 100644
--- a/test/CodeGen/PowerPC/select-i1-vs-i1.ll
+++ b/test/CodeGen/PowerPC/select-i1-vs-i1.ll
@@ -1,5 +1,6 @@
-; RUN: llc -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
+; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs \
+; RUN:   -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -475,12 +476,13 @@ entry:
   ret float %cond
 
 ; CHECK-LABEL: @testfloatslt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
@@ -494,12 +496,13 @@ entry:
   ret float %cond
 
 ; CHECK-LABEL: @testfloatult
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
@@ -513,10 +516,10 @@ entry:
   ret float %cond
 
 ; CHECK-LABEL: @testfloatsle
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
@@ -532,10 +535,10 @@ entry:
   ret float %cond
 
 ; CHECK-LABEL: @testfloatule
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
@@ -570,10 +573,10 @@ entry:
   ret float %cond
 
 ; CHECK-LABEL: @testfloatsge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
@@ -589,10 +592,10 @@ entry:
   ret float %cond
 
 ; CHECK-LABEL: @testfloatuge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
@@ -608,12 +611,13 @@ entry:
   ret float %cond
 
 ; CHECK-LABEL: @testfloatsgt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
@@ -627,12 +631,13 @@ entry:
   ret float %cond
 
 ; CHECK-LABEL: @testfloatugt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
@@ -665,12 +670,13 @@ entry:
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleslt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
@@ -684,12 +690,13 @@ entry:
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleult
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
@@ -703,10 +710,10 @@ entry:
   ret double %cond
 
 ; CHECK-LABEL: @testdoublesle
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
@@ -722,10 +729,10 @@ entry:
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleule
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
@@ -760,10 +767,10 @@ entry:
   ret double %cond
 
 ; CHECK-LABEL: @testdoublesge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
@@ -779,10 +786,10 @@ entry:
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleuge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: fmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: fmr 1, 5
@@ -798,12 +805,13 @@ entry:
   ret double %cond
 
 ; CHECK-LABEL: @testdoublesgt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
@@ -817,12 +825,13 @@ entry:
   ret double %cond
 
 ; CHECK-LABEL: @testdoubleugt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: fmr 1, 5
 ; CHECK: blr
 }
@@ -856,9 +865,10 @@ entry:
 
 ; CHECK-LABEL: @testv4floatslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 12, 2, 0
+; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -872,10 +882,11 @@ entry:
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatult
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bclr 4, 2, 0
+; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -889,10 +900,10 @@ entry:
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatsle
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 4, 2, 0
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bclr 12, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -907,9 +918,9 @@ entry:
 
 ; CHECK-LABEL: @testv4floatule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 12, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -943,9 +954,9 @@ entry:
 
 ; CHECK-LABEL: @testv4floatsge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 12, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -960,9 +971,9 @@ entry:
 
 ; CHECK-LABEL: @testv4floatuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 4, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 12, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -976,10 +987,10 @@ entry:
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatsgt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -993,10 +1004,11 @@ entry:
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floatugt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
+; CHECK: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: bclr 12, 2, 0
+; CHECK: .LBB[[BB]]
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -1059,9 +1071,10 @@ entry:
 
 ; CHECK-LABEL: @testv2doubleslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bc 4, 2, .LBB[[BB]]
+; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -1076,9 +1089,10 @@ entry:
 
 ; CHECK-LABEL: @testv2doubleult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bc 12, 2, .LBB[[BB]]
+; CHECK: .LBB[[BB]]:
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -1093,9 +1107,9 @@ entry:
 
 ; CHECK-LABEL: @testv2doublesle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 4, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 12, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -1110,9 +1124,9 @@ entry:
 
 ; CHECK-LABEL: @testv2doubleule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 12, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -1146,9 +1160,9 @@ entry:
 
 ; CHECK-LABEL: @testv2doublesge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 12, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 4, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -1163,9 +1177,9 @@ entry:
 
 ; CHECK-LABEL: @testv2doubleuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bclr 4, 2, 0
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bclr 12, 2, 0
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -1180,9 +1194,10 @@ entry:
 
 ; CHECK-LABEL: @testv2doublesgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bc 12, 2, .LBB[[BB]]
+; CHECK: .LBB[[BB]]
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -1197,9 +1212,10 @@ entry:
 
 ; CHECK-LABEL: @testv2doubleugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
+; CHECK: bc 4, 2, .LBB[[BB]]
+; CHECK: .LBB[[BB]]
 ; CHECK: vmr 2, 3
 ; CHECK: blr
 }
@@ -1231,11 +1247,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4doubleslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1250,11 +1267,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4doubleult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1269,9 +1287,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4doublesle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1288,9 +1306,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4doubleule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1326,9 +1344,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4doublesge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1345,9 +1363,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4doubleuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1364,11 +1382,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4doublesgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1383,11 +1402,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4doubleugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1421,11 +1441,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4floatslt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1440,11 +1461,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4floatult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1459,9 +1481,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4floatsle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1478,9 +1500,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4floatule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1516,9 +1538,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4floatsge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1535,9 +1557,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4floatuge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1554,11 +1576,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4floatsgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1573,11 +1596,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4floatugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1611,11 +1635,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4i1slt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1630,11 +1655,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4i1ult
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1649,9 +1675,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4i1sle
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1668,9 +1694,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4i1ule
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1706,9 +1732,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4i1sge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1725,9 +1751,9 @@ entry:
 
 ; CHECK-LABEL: @testqv4i1uge
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB]]
 ; CHECK: qvfmr 5, 6
 ; CHECK: .LBB[[BB]]:
 ; CHECK: qvfmr 1, 5
@@ -1744,11 +1770,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4i1sgt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
@@ -1763,11 +1790,12 @@ entry:
 
 ; CHECK-LABEL: @testqv4i1ugt
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
+; CHECK: .LBB[[BB1]]:
 ; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
+; CHECK: .LBB[[BB2]]:
 ; CHECK: qvfmr 1, 5
 ; CHECK: blr
 }
diff --git a/test/CodeGen/PowerPC/tail-dup-layout.ll b/test/CodeGen/PowerPC/tail-dup-layout.ll
index badeed5b30a..c9019983e93 100644
--- a/test/CodeGen/PowerPC/tail-dup-layout.ll
+++ b/test/CodeGen/PowerPC/tail-dup-layout.ll
@@ -1,5 +1,7 @@
-; RUN: llc -O2 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O2 %s
-; RUN: llc -O3 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-O3 %s
+; RUN: llc -O2 -ppc-reduce-cr-logicals -o - %s | FileCheck \
+; RUN:   --check-prefix=CHECK --check-prefix=CHECK-O2 %s
+; RUN: llc -O3 -ppc-reduce-cr-logicals -o - %s | FileCheck \
+; RUN:   --check-prefix=CHECK --check-prefix=CHECK-O3 %s
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-grtev4-linux-gnu"
 
@@ -276,8 +278,9 @@ exit:
 ;CHECK: add [[TAGPTRREG:[0-9]+]], 3, 4
 ;CHECK: .[[LATCHLABEL:[._0-9A-Za-z]+]]: # %for.latch
 ;CHECK: addi
-;CHECK: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check
+;CHECK-O2: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check
 ;CHECK: lwz [[TAGREG:[0-9]+]], 0([[TAGPTRREG]])
+;CHECK-O3: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check
 ;CHECK: # %bb.{{[0-9]+}}: # %test1
 ;CHECK: andi. {{[0-9]+}}, [[TAGREG]], 1
 ;CHECK-NEXT: bc 12, 1, .[[OPT1LABEL:[._0-9A-Za-z]+]]