diff options
author | Mehdi Amini <mehdi.amini@apple.com> | 2015-09-16 05:34:32 +0000 |
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committer | Mehdi Amini <mehdi.amini@apple.com> | 2015-09-16 05:34:32 +0000 |
commit | 793a2b15e7c0b8340fc3369348444823e55ceba5 (patch) | |
tree | 0eb4275978b8f78d0dd183d20779e17d10d771d7 /test/CodeGen/PowerPC | |
parent | ecd56aa51827c1236bbbfa802731621951d41e53 (diff) |
Make the default triple optional by allowing an empty string
When building LLVM as a (potentially dynamic) library that can be linked against
by multiple compilers, the default triple is not really meaningful.
We allow to explicitely set it to an empty string when configuring LLVM.
In this case, said "target independent" tests in the test suite that are using
the default triple are disabled by matching the newly available feature
"default_triple".
Reviewers: probinson, echristo
Differential Revision: http://reviews.llvm.org/D12660
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247775 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
-rw-r--r-- | test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll | 1 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll | 1 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll | 1 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll | 1 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll | 1 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/load-shift-combine.ll | 1 |
6 files changed, 6 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll index fde330321aa..d20e3b05c09 100644 --- a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll +++ b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s +; REQUIRES: default_triple define void @iterative_hash_host_wide_int() { %zero = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll index c63fd9ae170..3d5fa52d0ab 100644 --- a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll +++ b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s +; REQUIRES: default_triple %struct..0anon = type { i32 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] } diff --git a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll index 0e770985740..c064c273173 100644 --- a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll +++ b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=ppc64 ; RUN: llc < %s -march=ppc32 ; RUN: llc < %s +; REQUIRES: default_triple define void @bitap() { entry: diff --git a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll index 9660d450cb4..8536dda0a9b 100644 --- a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll +++ b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=ppc64 ; RUN: llc < %s -march=ppc32 ; RUN: llc < %s +; REQUIRES: default_triple @qsz.b = external global i1 ; <i1*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll index 4830ca60f9f..aa39dfd0374 100644 --- a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll +++ b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s -march=ppc32 -mcpu=g3 ; RUN: llc < %s -march=ppc32 -mcpu=g5 ; PR1811 +; REQUIRES: default_triple define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) { diff --git a/test/CodeGen/PowerPC/load-shift-combine.ll b/test/CodeGen/PowerPC/load-shift-combine.ll index 8d1f8146db9..3b468572521 100644 --- a/test/CodeGen/PowerPC/load-shift-combine.ll +++ b/test/CodeGen/PowerPC/load-shift-combine.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s +; REQUIRES: default_triple ; This used to cause a crash. A standard load is converted to a pre-increment ; load. Later the pre-increment load is combined with a subsequent SRL to |