[PowerPC] Expand ISEL instruction into if-then-else sequence.

Generally, the ISEL is expanded into if-then-else sequence, in some
cases (like when the destination register is the same with the true
or false value register), it may just be expanded into just the if
or else sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292154 91177308-0d34-0410-b5e6-96231b3b80d8

24 files changed, 1151 insertions, 25 deletions

diff --git a/test/CodeGen/PowerPC/crbit-asm.ll b/test/CodeGen/PowerPC/crbit-asm.ll
index 11999670bd6..c156d3bcc08 100644
--- a/test/CodeGen/PowerPC/crbit-asm.ll
+++ b/test/CodeGen/PowerPC/crbit-asm.ll
@@ -1,5 +1,8 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false  < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
+; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
+
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -18,6 +21,10 @@ entry:
 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
 ; CHECK-DAG: li [[REG4:[0-9]+]], 1
 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
+; CHECK-NO-ISEL-LABEL: @testi1
+; CHECK-NO-ISEL: bclr 12, 20, 0
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
diff --git a/test/CodeGen/PowerPC/crbits.ll b/test/CodeGen/PowerPC/crbits.ll
index 97f02ef31b3..b894a361d26 100644
--- a/test/CodeGen/PowerPC/crbits.ll
+++ b/test/CodeGen/PowerPC/crbits.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -19,6 +20,12 @@ entry:
 ; CHECK: crnor
 ; CHECK: crnand [[REG4:[0-9]+]],
 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
+; CHECK-NO-ISEL-LABEL: @test1
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
diff --git a/test/CodeGen/PowerPC/expand-contiguous-isel.ll b/test/CodeGen/PowerPC/expand-contiguous-isel.ll
new file mode 100644
index 00000000000..5fe69ebcf58
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-contiguous-isel.ll
@@ -0,0 +1,151 @@
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+; This file mainly tests that one of the ISEL instruction in the group uses the same register for operand RT, RA, RB
+; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE
+; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
+; Function Attrs: norecurse nounwind readnone
+@.str = private unnamed_addr constant [3 x i8] c"]]\00", align 1
+@.str.1 = private unnamed_addr constant [35 x i8] c"Index < Length && \22Invalid index!\22\00", align 1
+@.str.2 = private unnamed_addr constant [50 x i8] c"/home/jtony/src/llvm/include/llvm/ADT/StringRef.h\00", align 1
+@__PRETTY_FUNCTION__._ZNK4llvm9StringRefixEm = private unnamed_addr constant [47 x i8] c"char llvm::StringRef::operator[](size_t) const\00", align 1
+@.str.3 = private unnamed_addr constant [95 x i8] c"(data || length == 0) && \22StringRef cannot be built from a NULL argument with non-null length\22\00", align 1
+@__PRETTY_FUNCTION__._ZN4llvm9StringRefC2EPKcm = private unnamed_addr constant [49 x i8] c"llvm::StringRef::StringRef(const char *, size_t)\00", align 1
+; Function Attrs: nounwind
+define i64 @_Z3fn1N4llvm9StringRefE([2 x i64] %Str.coerce) local_unnamed_addr #0 {
+entry:
+  %Str.coerce.fca.0.extract = extractvalue [2 x i64] %Str.coerce, 0
+  %Str.coerce.fca.1.extract = extractvalue [2 x i64] %Str.coerce, 1
+  br label %while.cond.outer
+while.cond.outer:                                 ; preds = %_ZNK4llvm9StringRef6substrEmm.exit, %entry
+  %Str.sroa.0.0.ph = phi i64 [ %8, %_ZNK4llvm9StringRef6substrEmm.exit ], [ %Str.coerce.fca.0.extract, %entry ]
+  %.sink.ph = phi i64 [ %sub.i, %_ZNK4llvm9StringRef6substrEmm.exit ], [ %Str.coerce.fca.1.extract, %entry ]
+  %BracketDepth.0.ph = phi i64 [ %BracketDepth.1, %_ZNK4llvm9StringRef6substrEmm.exit ], [ undef, %entry ]
+  %cmp65 = icmp eq i64 %BracketDepth.0.ph, 0
+  br i1 %cmp65, label %while.cond.us.preheader, label %while.cond.preheader
+while.cond.us.preheader:                          ; preds = %while.cond.outer
+  br label %while.cond.us
+while.cond.preheader:                             ; preds = %while.cond.outer
+  %cmp.i34129 = icmp eq i64 %.sink.ph, 0
+  br i1 %cmp.i34129, label %cond.false.i.loopexit135, label %_ZNK4llvm9StringRefixEm.exit.preheader
+_ZNK4llvm9StringRefixEm.exit.preheader:           ; preds = %while.cond.preheader
+  br label %_ZNK4llvm9StringRefixEm.exit
+while.cond.us:                                    ; preds = %while.cond.us.preheader, %_ZNK4llvm9StringRef6substrEmm.exit50.us
+  %Str.sroa.0.0.us = phi i64 [ %3, %_ZNK4llvm9StringRef6substrEmm.exit50.us ], [ %Str.sroa.0.0.ph, %while.cond.us.preheader ]
+  %.sink.us = phi i64 [ %sub.i41.us, %_ZNK4llvm9StringRef6substrEmm.exit50.us ], [ %.sink.ph, %while.cond.us.preheader ]
+  %cmp.i30.us = icmp ult i64 %.sink.us, 2
+  br i1 %cmp.i30.us, label %if.end.us, label %if.end.i.i.us
+if.end.i.i.us:                                    ; preds = %while.cond.us
+  %0 = inttoptr i64 %Str.sroa.0.0.us to i8*
+  %call.i.i.us = tail call signext i32 @memcmp(i8* %0, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i64 0, i64 0), i64 2) #3
+  %phitmp.i.us = icmp eq i32 %call.i.i.us, 0
+  br i1 %phitmp.i.us, label %if.then, label %_ZNK4llvm9StringRefixEm.exit.us
+if.end.us:                                        ; preds = %while.cond.us
+  %cmp.i34.us = icmp eq i64 %.sink.us, 0
+  br i1 %cmp.i34.us, label %cond.false.i.loopexit, label %_ZNK4llvm9StringRefixEm.exit.us
+_ZNK4llvm9StringRefixEm.exit.us:                  ; preds = %if.end.i.i.us, %if.end.us
+  %1 = inttoptr i64 %Str.sroa.0.0.us to i8*
+  %2 = load i8, i8* %1, align 1, !tbaa !2
+  switch i8 %2, label %_ZNK4llvm9StringRef6substrEmm.exit.loopexit [
+    i8 92, label %if.then4.us
+    i8 93, label %if.then9
+  ]
+if.then4.us:                                      ; preds = %_ZNK4llvm9StringRefixEm.exit.us
+  %.sroa.speculated12.i38.us = select i1 %cmp.i30.us, i64 %.sink.us, i64 2
+  %add.ptr.i40.us = getelementptr inbounds i8, i8* %1, i64 %.sroa.speculated12.i38.us
+  %sub.i41.us = sub i64 %.sink.us, %.sroa.speculated12.i38.us
+  %tobool.i.i44.us = icmp ne i8* %add.ptr.i40.us, null
+  %cmp.i4.i45.us = icmp eq i64 %sub.i41.us, 0
+  %or.cond.i.i46.us = or i1 %tobool.i.i44.us, %cmp.i4.i45.us
+  br i1 %or.cond.i.i46.us, label %_ZNK4llvm9StringRef6substrEmm.exit50.us, label %cond.false.i.i47.loopexit
+_ZNK4llvm9StringRef6substrEmm.exit50.us:          ; preds = %if.then4.us
+  %3 = ptrtoint i8* %add.ptr.i40.us to i64
+  br label %while.cond.us
+if.then:                                          ; preds = %if.end.i.i.us
+  ret i64 undef
+cond.false.i.loopexit:                            ; preds = %if.end.us
+  br label %cond.false.i
+cond.false.i.loopexit134:                         ; preds = %_ZNK4llvm9StringRef6substrEmm.exit50
+  br label %cond.false.i
+cond.false.i.loopexit135:                         ; preds = %while.cond.preheader
+  br label %cond.false.i
+cond.false.i:                                     ; preds = %cond.false.i.loopexit135, %cond.false.i.loopexit134, %cond.false.i.loopexit
+  tail call void @__assert_fail(i8* getelementptr inbounds ([35 x i8], [35 x i8]* @.str.1, i64 0, i64 0), i8* getelementptr inbounds ([50 x i8], [50 x i8]* @.str.2, i64 0, i64 0), i32 zeroext 225, i8* getelementptr inbounds ([47 x i8], [47 x i8]* @__PRETTY_FUNCTION__._ZNK4llvm9StringRefixEm, i64 0, i64 0)) #4
+  unreachable
+_ZNK4llvm9StringRefixEm.exit:                     ; preds = %_ZNK4llvm9StringRefixEm.exit.preheader, %_ZNK4llvm9StringRef6substrEmm.exit50
+  %.sink131 = phi i64 [ %sub.i41, %_ZNK4llvm9StringRef6substrEmm.exit50 ], [ %.sink.ph, %_ZNK4llvm9StringRefixEm.exit.preheader ]
+  %Str.sroa.0.0130 = phi i64 [ %6, %_ZNK4llvm9StringRef6substrEmm.exit50 ], [ %Str.sroa.0.0.ph, %_ZNK4llvm9StringRefixEm.exit.preheader ]
+  %4 = inttoptr i64 %Str.sroa.0.0130 to i8*
+  %5 = load i8, i8* %4, align 1, !tbaa !2
+  switch i8 %5, label %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 [
+    i8 92, label %if.then4
+    i8 93, label %if.end10
+  ]
+if.then4:                                         ; preds = %_ZNK4llvm9StringRefixEm.exit
+  %cmp.i.i37 = icmp ult i64 %.sink131, 2
+  %.sroa.speculated12.i38 = select i1 %cmp.i.i37, i64 %.sink131, i64 2
+  %add.ptr.i40 = getelementptr inbounds i8, i8* %4, i64 %.sroa.speculated12.i38
+  %sub.i41 = sub i64 %.sink131, %.sroa.speculated12.i38
+  %tobool.i.i44 = icmp ne i8* %add.ptr.i40, null
+  %cmp.i4.i45 = icmp eq i64 %sub.i41, 0
+  %or.cond.i.i46 = or i1 %tobool.i.i44, %cmp.i4.i45
+  br i1 %or.cond.i.i46, label %_ZNK4llvm9StringRef6substrEmm.exit50, label %cond.false.i.i47.loopexit133
+cond.false.i.i47.loopexit:                        ; preds = %if.then4.us
+  br label %cond.false.i.i47
+cond.false.i.i47.loopexit133:                     ; preds = %if.then4
+  br label %cond.false.i.i47
+cond.false.i.i47:                                 ; preds = %cond.false.i.i47.loopexit133, %cond.false.i.i47.loopexit
+  tail call void @__assert_fail(i8* getelementptr inbounds ([95 x i8], [95 x i8]* @.str.3, i64 0, i64 0), i8* getelementptr inbounds ([50 x i8], [50 x i8]* @.str.2, i64 0, i64 0), i32 zeroext 90, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @__PRETTY_FUNCTION__._ZN4llvm9StringRefC2EPKcm, i64 0, i64 0)) #4
+  unreachable
+_ZNK4llvm9StringRef6substrEmm.exit50:             ; preds = %if.then4
+  %6 = ptrtoint i8* %add.ptr.i40 to i64
+  %cmp.i34 = icmp eq i64 %sub.i41, 0
+  br i1 %cmp.i34, label %cond.false.i.loopexit134, label %_ZNK4llvm9StringRefixEm.exit
+if.then9:                                         ; preds = %_ZNK4llvm9StringRefixEm.exit.us
+  tail call void @exit(i32 signext 1) #4
+  unreachable
+if.end10:                                         ; preds = %_ZNK4llvm9StringRefixEm.exit
+  %dec = add i64 %BracketDepth.0.ph, -1
+  br label %_ZNK4llvm9StringRef6substrEmm.exit
+_ZNK4llvm9StringRef6substrEmm.exit.loopexit:      ; preds = %_ZNK4llvm9StringRefixEm.exit.us
+  br label %_ZNK4llvm9StringRef6substrEmm.exit
+_ZNK4llvm9StringRef6substrEmm.exit.loopexit132:   ; preds = %_ZNK4llvm9StringRefixEm.exit
+  br label %_ZNK4llvm9StringRef6substrEmm.exit
+_ZNK4llvm9StringRef6substrEmm.exit:               ; preds = %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit, %if.end10
+  %.sink76 = phi i64 [ %.sink131, %if.end10 ], [ %.sink.us, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %.sink131, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ]
+  %7 = phi i8* [ %4, %if.end10 ], [ %1, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %4, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ]
+  %BracketDepth.1 = phi i64 [ %dec, %if.end10 ], [ 0, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %BracketDepth.0.ph, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ]
+  %sub.i = add i64 %.sink76, -1
+  %add.ptr.i = getelementptr inbounds i8, i8* %7, i64 1
+  %8 = ptrtoint i8* %add.ptr.i to i64
+  br label %while.cond.outer
+
+; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE
+; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
+; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
+; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT: [[TRUE]]
+; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+}
+
+
+
+; Function Attrs: noreturn nounwind
+declare void @exit(i32 signext) local_unnamed_addr #1
+; Function Attrs: nounwind readonly
+declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_addr #2
+; Function Attrs: noreturn nounwind
+declare void @__assert_fail(i8*, i8*, i32 zeroext, i8*) local_unnamed_addr #1
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind readonly }
+attributes #4 = { noreturn nounwind }
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+!0 = !{i32 1, !"PIC Level", i32 2}
+!1 = !{!"clang version 4.0.0 (trunk 286863) (llvm/trunk 286967)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C++ TBAA"}
diff --git a/test/CodeGen/PowerPC/expand-isel-1.mir b/test/CodeGen/PowerPC/expand-isel-1.mir
new file mode 100644
index 00000000000..e666ad47fca
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-isel-1.mir
@@ -0,0 +1,57 @@
+# This file tests the scenario: ISEL R0, ZERO, R0, CR
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
+  entry:
+    %cmp = icmp sgt i32 %i, 0
+    %add = add nsw i32 %i, 1
+    %cond = select i1 %cmp, i32 %add, i32 %j
+    ret i32 %cond
+  }
+
+...
+---
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r0 = ISEL %zero, %r0, %cr0gt
+    ; CHECK-LABEL: testExpandISEL
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK-NEXT: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r0 = ADDI %zero, 0
+
+    %x3 = EXTSW_32_64 %r0
+
+...
+
diff --git a/test/CodeGen/PowerPC/expand-isel-2.mir b/test/CodeGen/PowerPC/expand-isel-2.mir
new file mode 100644
index 00000000000..8e9c3a25e60
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-isel-2.mir
@@ -0,0 +1,57 @@
+# This file tests the scenario: ISEL RX, ZERO, RY, CR  (X != 0 && Y != 0)
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
+  entry:
+    %cmp = icmp sgt i32 %i, 0
+    %add = add nsw i32 %i, 1
+    %cond = select i1 %cmp, i32 %add, i32 %j
+    ret i32 %cond
+  }
+
+...
+---
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+  - { reg: '%x4' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3, %x4
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r3 = ISEL %zero, %r4, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r3 = ORI %r4, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r3 = ADDI %zero, 0
+
+    %x3 = EXTSW_32_64 %r3
+...
diff --git a/test/CodeGen/PowerPC/expand-isel-3.mir b/test/CodeGen/PowerPC/expand-isel-3.mir
new file mode 100644
index 00000000000..c8987266f47
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-isel-3.mir
@@ -0,0 +1,58 @@
+# This file tests the scenario: ISEL RX, RY, R0, CR  (X != 0 && Y != 0)
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
+  entry:
+    %cmp = icmp sgt i32 %i, 0
+    %add = add nsw i32 %i, 1
+    %cond = select i1 %cmp, i32 %add, i32 %j
+    ret i32 %cond
+  }
+
+...
+---
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+  - { reg: '%x4' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3, %x4
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r3 = ISEL %r4, %r0, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r3 = ORI %r0, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r3 = ADDI  %r4, 0
+
+    %x3 = EXTSW_32_64  %r3
+
+...
diff --git a/test/CodeGen/PowerPC/expand-isel-4.mir b/test/CodeGen/PowerPC/expand-isel-4.mir
new file mode 100644
index 00000000000..83624f7c1e3
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-isel-4.mir
@@ -0,0 +1,59 @@
+# This file tests the scenario: ISEL R0, ZERO, RX, CR  (X != 0)
+# It also tests redundant liveins (%x7) and killed registers.
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
+  entry:
+    %cmp = icmp sgt i32 %i, 0
+    %add = add nsw i32 %i, 1
+    %cond = select i1 %cmp, i32 %add, i32 %j
+    ret i32 %cond
+  }
+
+...
+---
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+  - { reg: '%x7' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3, %x7
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r0 = ISEL killed %zero, killed %r5, killed %cr0gt, implicit killed %cr0
+    ; CHECK: BC killed %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r0 = ORI killed %r5, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r0 = ADDI killed %zero, 0
+
+    %x0 = EXTSW_32_64 killed %r0
+
+...
diff --git a/test/CodeGen/PowerPC/expand-isel-5.mir b/test/CodeGen/PowerPC/expand-isel-5.mir
new file mode 100644
index 00000000000..7a7130f80cf
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-isel-5.mir
@@ -0,0 +1,54 @@
+# This file tests the scenario: ISEL R0, RX, R0, CR  (X != 0)
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
+  entry:
+    %cmp = icmp sgt i32 %i, 0
+    %add = add nsw i32 %i, 1
+    %cond = select i1 %cmp, i32 %add, i32 %j
+    ret i32 %cond
+  }
+
+...
+---
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r0 = ISEL %r5, %r0, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r0 = ADDI %r5, 0
+    %x3 = EXTSW_32_64 %r0
+
+...
diff --git a/test/CodeGen/PowerPC/expand-isel-6.mir b/test/CodeGen/PowerPC/expand-isel-6.mir
new file mode 100644
index 00000000000..5aed399e677
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-isel-6.mir
@@ -0,0 +1,57 @@
+# This file tests the scenario when ISEL is the last instruction of the last
+# Basic Block, i.e., the BB cannot fall through to its successor situation.
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
+  entry:
+    %cmp = icmp sgt i32 %i, 0
+    %add = add nsw i32 %i, 1
+    %cond = select i1 %cmp, i32 %add, i32 %j
+    ret i32 %cond
+  }
+
+...
+---
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x0' }
+  - { reg: '%x3' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x3
+
+    %r5 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r3 = ISEL %zero, %r0, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r3 = ORI %r0, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r3 = ADDI %zero, 0
+
+
+...
diff --git a/test/CodeGen/PowerPC/expand-isel-7.mir b/test/CodeGen/PowerPC/expand-isel-7.mir
new file mode 100644
index 00000000000..4043a45a2e7
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-isel-7.mir
@@ -0,0 +1,58 @@
+# This file tests the scenario: ISEL RX, RY, RZ, CR  (X != 0 && Y != 0, Z != 0)
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
+  entry:
+    %cmp = icmp sgt i32 %i, 0
+    %add = add nsw i32 %i, 1
+    %cond = select i1 %cmp, i32 %add, i32 %j
+    ret i32 %cond
+  }
+
+...
+---
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x3' }
+  - { reg: '%x4' }
+  - { reg: '%x5' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x3, %x4, %x5
+
+    %r4 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r5 = ISEL %r3, %r4, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r5 = ORI %r4, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r5 = ADDI %r3, 0
+
+    %x5 = EXTSW_32_64 %r5
+
+...
diff --git a/test/CodeGen/PowerPC/expand-isel-8.mir b/test/CodeGen/PowerPC/expand-isel-8.mir
new file mode 100644
index 00000000000..c8b857e6979
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-isel-8.mir
@@ -0,0 +1,65 @@
+# This file tests combining three consecutive ISELs scenario.
+# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
+  entry:
+    %cmp = icmp sgt i32 %i, 0
+    %add = add nsw i32 %i, 1
+    %cond = select i1 %cmp, i32 %add, i32 %j
+    ret i32 %cond
+  }
+
+...
+---
+name:            testExpandISEL
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%x3' }
+  - { reg: '%x4' }
+  - { reg: '%x5' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x3, %x4, %x5
+
+    %r4 = ADDI %r3, 1
+    %cr0 = CMPWI %r3, 0
+    %r5 = ISEL %r3, %r4, %cr0gt
+    %r3 = ISEL %r4, %r5, %cr0gt
+    %r4 = ISEL %r3, %r5, %cr0gt
+    ; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
+    ; CHECK: %[[FALSE:bb.[0-9]+]]
+    ; CHECK: %r5 = ORI %r4, 0
+    ; CHECK: %r3 = ORI %r5, 0
+    ; CHECK: %r4 = ORI %r5, 0
+    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
+    ; CHECK: [[TRUE]]
+    ; CHECK: %r5 = ADDI %r3, 0
+    ; CHECK: %r3 = ADDI %r4, 0
+    ; CHECK: %r4 = ADDI %r3, 0
+
+    %x5 = EXTSW_32_64 %r5
+    %x3 = EXTSW_32_64 %r3
+
+...
diff --git a/test/CodeGen/PowerPC/expand-isel.ll b/test/CodeGen/PowerPC/expand-isel.ll
new file mode 100644
index 00000000000..553cc3c372e
--- /dev/null
+++ b/test/CodeGen/PowerPC/expand-isel.ll
@@ -0,0 +1,227 @@
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %add = add nsw i32 %i, 1
+  %cond = select i1 %cmp, i32 %add, i32 %j
+  ret i32 %cond
+
+; CHECK-LABEL: @testExpandISELToIfElse
+; CHECK: addi r5, r3, 1
+; CHECK-NEXT: cmpwi cr0, r3, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori r3, r4, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r3, r5, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELToIf(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %cond = select i1 %cmp, i32 %j, i32 %i
+  ret i32 %cond
+
+; CHECK-LABEL: @testExpandISELToIf
+; CHECK: cmpwi	 r3, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: blr
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r3, r4, 0
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELToElse(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %cond = select i1 %cmp, i32 %i, i32 %j
+  ret i32 %cond
+
+; CHECK-LABEL: @testExpandISELToElse
+; CHECK: cmpwi	 r3, 0
+; CHECK-NEXT: bclr 12, 1, 0
+; CHECK: ori r3, r4, 0
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testReplaceISELWithCopy(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %cond = select i1 %cmp, i32 %j, i32 %j
+  ret i32 %cond
+
+; CHECK-LABEL: @testReplaceISELWithCopy
+
+; Fix me should really check: addi r3, r4, 0
+; but for some reason it's optimized to mr r3, r4
+; CHECK: mr r3, r4
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELToNull(i32 signext %i, i32 signext %j) {
+entry:
+  %cmp = icmp sgt i32 %i, 0
+  %cond = select i1 %cmp, i32 %i, i32 %i
+  ret i32 %cond
+
+; CHECK-LABEL: @testExpandISELToNull
+; CHECK-NOT: b {{.LBB[0-9]+}}
+; CHECK-NOT: bc
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELsTo2ORIs2ADDIs
+  (i32 signext %a, i32 signext %b, i32 signext %d,
+   i32 signext %f, i32 signext %g) {
+entry:
+
+  %cmp = icmp sgt i32 %g, 0
+  %a.b = select i1 %cmp, i32 %g, i32 %b
+  %d.f = select i1 %cmp, i32 %d, i32 %f
+  %add = add nsw i32 %a.b, %d.f
+  ret i32 %add
+
+; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs
+; CHECK: cmpwi r7, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori r3, r4, 0
+; CHECK-NEXT: ori r12, r6, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r3, r7, 0
+; CHECK-NEXT: addi r12, r5, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK-NEXT: add r3, r3, r12
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELsTo2ORIs1ADDI
+  (i32 signext %a, i32 signext %b, i32 signext %d,
+   i32 signext %f, i32 signext %g) {
+entry:
+  %cmp = icmp sgt i32 %g, 0
+  %a.b = select i1 %cmp, i32 %a, i32 %b
+  %d.f = select i1 %cmp, i32 %d, i32 %f
+  %add = add nsw i32 %a.b, %d.f
+  ret i32 %add
+
+; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
+; CHECK: cmpwi cr0, r7, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori r3, r4, 0
+; CHECK-NEXT: ori r12, r6, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT: [[TRUE]]
+; CHECK-NEXT: addi r12, r5, 0
+; CHECK-NEXT:  [[SUCCESSOR]]
+; CHECK-NEXT: add r3, r3, r12
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELsTo1ORI1ADDI
+  (i32 signext %a, i32 signext %b, i32 signext %d,
+   i32 signext %f, i32 signext %g) {
+entry:
+
+  %cmp = icmp sgt i32 %g, 0
+  %a.b = select i1 %cmp, i32 %a, i32 %b
+  %d.f = select i1 %cmp, i32 %d, i32 %f
+  %add1 = add nsw i32 %a.b, %d.f
+  %add2 = add nsw i32 %a, %add1
+  ret i32 %add2
+
+; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
+; CHECK: cmpwi cr0, r7, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori r5, r6, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT: [[TRUE]]
+; CHECK-NEXT: addi r4, r3, 0
+; CHECK-NEXT:  [[SUCCESSOR]]
+; CHECK-NEXT: add r4, r4, r5
+; CHECK-NEXT: add r3, r3, r4
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @testExpandISELsTo0ORI2ADDIs
+  (i32 signext %a, i32 signext %b, i32 signext %d,
+   i32 signext %f, i32 signext %g) {
+entry:
+
+  %cmp = icmp sgt i32 %g, 0
+  %a.b = select i1 %cmp, i32 %a, i32 %b
+  %d.f = select i1 %cmp, i32 %d, i32 %f
+  %add1 = add nsw i32 %a.b, %d.f
+  %add2 = add nsw i32 %a, %add1
+  %sub1 = sub nsw i32 %add2, %d
+  ret i32 %sub1
+
+; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
+; CHECK: cmpwi cr0, r7, 0
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r4, r3, 0
+; CHECK-NEXT: addi r6, r5, 0
+; CHECK-NEXT:  [[SUCCESSOR]]
+; CHECK-NEXT: add r4, r4, r6
+; CHECK-NEXT: add r3, r3, r4
+; CHECK-NEXT: subf r3, r5, r3
+; CHECK-NEXT: extsw r3, r3
+; CHECK-NEXT: blr
+}
+
+
+@b = common local_unnamed_addr global i32 0, align 4
+@a = common local_unnamed_addr global i32 0, align 4
+; Function Attrs: norecurse nounwind readonly
+define signext i32 @testComplexISEL() #0 {
+entry:
+  %0 = load i32, i32* @b, align 4, !tbaa !1
+  %tobool = icmp eq i32 %0, 0
+  br i1 %tobool, label %if.end, label %cleanup
+
+if.end:
+  %1 = load i32, i32* @a, align 4, !tbaa !1
+  %conv = sext i32 %1 to i64
+  %2 = inttoptr i64 %conv to i32 (...)*
+  %cmp = icmp eq i32 (...)* %2, bitcast (i32 ()* @testComplexISEL to i32 (...)*)
+  %conv3 = zext i1 %cmp to i32
+  br label %cleanup
+
+cleanup:
+  %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ]
+  ret i32 %retval.0
+
+; CHECK-LABEL: @testComplexISEL
+; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT:  [[TRUE]]
+; CHECK-NEXT: addi r3, r12, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK-NEXT: clrldi r3, r3, 32
+; CHECK-NEXT: blr
+}
+
+!1 = !{!2, !2, i64 0}
+!2 = !{!"int", !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/PowerPC/fold-zero.ll b/test/CodeGen/PowerPC/fold-zero.ll
index 5e620ece0a9..180d8e1b9f5 100644
--- a/test/CodeGen/PowerPC/fold-zero.ll
+++ b/test/CodeGen/PowerPC/fold-zero.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck -check-prefix=CHECK-CRB %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-CRB %s
+; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -7,19 +8,33 @@ define i32 @test1(i1 %a, i32 %c) nounwind  {
   %x = select i1 %a, i32 %c, i32 0
   ret i32 %x
 
-; CHECK: @test1
+; CHECK-LABEL: @test1
 ; CHECK-NOT: li {{[0-9]+}}, 0
 ; CHECK: isel 3, 0,
 ; CHECK: blr
+; CHECK-NO-ISEL-LABEL: @test1
+; CHECK-NO-ISEL: li 3, 0
+; CHECK-NO-ISEL-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 define i32 @test2(i1 %a, i32 %c) nounwind  {
   %x = select i1 %a, i32 0, i32 %c
   ret i32 %x
 
-; CHECK-CRB: @test2
+; CHECK-CRB-LABEL: @test2
 ; CHECK-CRB-NOT: li {{[0-9]+}}, 0
 ; CHECK-CRB: isel 3, 0,
 ; CHECK-CRB: blr
+; CHECK-NO-ISEL-LABEL: @test2
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
diff --git a/test/CodeGen/PowerPC/i1-ext-fold.ll b/test/CodeGen/PowerPC/i1-ext-fold.ll
index 9a71b7baa66..877da486bcd 100644
--- a/test/CodeGen/PowerPC/i1-ext-fold.ll
+++ b/test/CodeGen/PowerPC/i1-ext-fold.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -11,11 +12,19 @@ entry:
   ret i32 %shl
 
 ; CHECK-LABEL: @foo
+; CHECK-NO-ISEL-LABEL: @foo
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 16
 ; CHECK: isel 3, [[REG2]], [[REG1]],
 ; CHECK: blr
+
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 ; Function Attrs: nounwind readnone
@@ -28,11 +37,19 @@ entry:
   ret i32 %add1
 
 ; CHECK-LABEL: @foo2
+; CHECK-NO-ISEL-LABEL: @foo2
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 5
 ; CHECK-DAG: li [[REG2:[0-9]+]], 21
 ; CHECK: isel 3, [[REG2]], [[REG1]],
 ; CHECK: blr
+
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 ; Function Attrs: nounwind readnone
@@ -44,10 +61,18 @@ entry:
   ret i32 %shl
 
 ; CHECK-LABEL: @foo3
+; CHECK-NO-ISEL-LABEL: @foo3
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 16
 ; CHECK: isel 3, 0, [[REG1]],
 ; CHECK: blr
+
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 attributes #0 = { nounwind readnone }
diff --git a/test/CodeGen/PowerPC/i1-to-double.ll b/test/CodeGen/PowerPC/i1-to-double.ll
index 4b13388ff46..7871ac7ae05 100644
--- a/test/CodeGen/PowerPC/i1-to-double.ll
+++ b/test/CodeGen/PowerPC/i1-to-double.ll
@@ -7,15 +7,13 @@ define double @test(i1 %X) {
 ; CHECK-LABEL: @test
 
 ; CHECK: andi. {{[0-9]+}}, 3, 1
-; CHECK: bc 12, 1,
-
-; CHECK: li 3, .LCP[[L1:[A-Z0-9_]+]]@l
-; CHECK: addis 3, 3, .LCP[[L1]]@ha
-; CHECK: lfs 1, 0(3)
-; CHECK: blr
-
-; CHECK: li 3, .LCP[[L2:[A-Z0-9_]+]]@l
-; CHECK: addis 3, 3, .LCP[[L2]]@ha
-; CHECK: lfs 1, 0(3)
-; CHECK: blr
-
+; CHECK-NEXT: addis 4, 4, .LCPI
+; CHECK-NEXT: addis 5, 5, .LCPI
+; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK: ori 3, 4, 0
+; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NEXT: [[TRUE]]
+; CHECK-NEXT: addi 3, 5, 0
+; CHECK-NEXT: [[SUCCESSOR]]
+; CHECK-NEXT: lfs 1, 0(3)
+; CHECK-NEXT: blr
diff --git a/test/CodeGen/PowerPC/i64_fp_round.ll b/test/CodeGen/PowerPC/i64_fp_round.ll
index 1e95dfdec71..5e959f73568 100644
--- a/test/CodeGen/PowerPC/i64_fp_round.ll
+++ b/test/CodeGen/PowerPC/i64_fp_round.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -ppc-gen-isel=false < %s | FileCheck %s --check-prefix=CHECK-NO-ISEL
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -12,10 +13,17 @@ entry:
 ; Note that only parts of the sequence are checked for here, to allow
 ; for minor code generation differences.
 
+;CHECK-LABEL: test
+;CHECK-NO-ISEL-LABEL: test
 ; CHECK: sradi [[REG1:[0-9]+]], 3, 53
 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
 ; CHECK: cmpldi [[REG2]], 1
 ; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 11, 3, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 11, 4, 0
 ; CHECK: std [[REG3]], -{{[0-9]+}}(1)
 
 
diff --git a/test/CodeGen/PowerPC/ifcvt.ll b/test/CodeGen/PowerPC/ifcvt.ll
index 9c966c95b72..b9b594a68f1 100644
--- a/test/CodeGen/PowerPC/ifcvt.ll
+++ b/test/CodeGen/PowerPC/ifcvt.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -18,10 +19,18 @@ cond.false:                                       ; preds = %sw.epilog
   %add37 = add nsw i32 %conv29, %a
   br label %cond.end
 
-; CHECK: @test
+; CHECK-LABEL: @test
+; CHECK-NO-ISEL-LABEL: @test
 ; CHECK: add [[REG:[0-9]+]], 
 ; CHECK: subf [[REG2:[0-9]+]],
 ; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]],
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 5, 6, 0
+; CHECK-NO-ISEL: extsh 5, 5
+; CHECK-NO-ISEL-NEXT: add 3, 3, 5
+; CHECK-NO-ISEL-NEXT: blr
 
 cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ]
diff --git a/test/CodeGen/PowerPC/isel.ll b/test/CodeGen/PowerPC/isel.ll
index 1dc55fcc40b..c1cceb96701 100644
--- a/test/CodeGen/PowerPC/isel.ll
+++ b/test/CodeGen/PowerPC/isel.ll
@@ -2,14 +2,22 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "powerpc64-unknown-linux-gnu"
 ; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 
 define i64 @test1(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
 	%p = icmp uge i64 %a, %b
 	%x = select i1 %p, i64 %c, i64 %d
 	ret i64 %x
-; CHECK: @test1
+; CHECK-LABEL: @test1
+; CHECK-NO-ISEL-LABEL: @test1
 ; CHECK: isel
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 6, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
 define i32 @test2(i32 %a, i32 %b, i32 %c, i32 %d) {
@@ -17,7 +25,14 @@ entry:
 	%p = icmp uge i32 %a, %b
 	%x = select i1 %p, i32 %c, i32 %d
 	ret i32 %x
-; CHECK: @test2
+; CHECK-LABEL: @test2
+; CHECK-NO-ISEL-LABEL: @test2
 ; CHECK: isel
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 5, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 6, 0
+; CHECK-NO-ISEL-NEXT: blr
 }
 
diff --git a/test/CodeGen/PowerPC/optcmp.ll b/test/CodeGen/PowerPC/optcmp.ll
index 5e8ca5a6a67..a1921452d62 100644
--- a/test/CodeGen/PowerPC/optcmp.ll
+++ b/test/CodeGen/PowerPC/optcmp.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -34,9 +35,14 @@ entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @fool
+; CHECK-LABEL: @fool
+; CHECK-NO-ISEL-LABEL: @fool
 ; CHECK: subf. [[REG:[0-9]+]], 4, 3
 ; CHECK: isel 3, 3, 4, 1
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
+
 ; CHECK: std [[REG]], 0(5)
 }
 
@@ -48,9 +54,13 @@ entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @foolb
+; CHECK-LABEL: @foolb
+; CHECK-NO-ISEL-LABEL: @foolb
 ; CHECK: subf. [[REG:[0-9]+]], 4, 3
 ; CHECK: isel 3, 4, 3, 1
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: b .LBB
+; CHECK-NO-ISEL addi: 3, 4, 0
 ; CHECK: std [[REG]], 0(5)
 }
 
@@ -62,9 +72,13 @@ entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @foolc
+; CHECK-LABEL: @foolc
+; CHECK-NO-ISEL-LABEL: @foolc
 ; CHECK: subf. [[REG:[0-9]+]], 3, 4
 ; CHECK: isel 3, 3, 4, 0
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK: std [[REG]], 0(5)
 }
 
@@ -76,9 +90,13 @@ entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @foold
+; CHECK-LABEL: @foold
+; CHECK-NO-ISEL-LABEL: @foold
 ; CHECK: subf. [[REG:[0-9]+]], 3, 4
 ; CHECK: isel 3, 3, 4, 1
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK: std [[REG]], 0(5)
 }
 
@@ -90,9 +108,13 @@ entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
-; CHECK: @foold2
+; CHECK-LABEL: @foold2
+; CHECK-NO-ISEL-LABEL: @foold2
 ; CHECK: subf. [[REG:[0-9]+]], 4, 3
 ; CHECK: isel 3, 3, 4, 0
+; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 4, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK: std [[REG]], 0(5)
 }
 
diff --git a/test/CodeGen/PowerPC/p8-isel-sched.ll b/test/CodeGen/PowerPC/p8-isel-sched.ll
index 6fa5616dd42..b45a123f027 100644
--- a/test/CodeGen/PowerPC/p8-isel-sched.ll
+++ b/test/CodeGen/PowerPC/p8-isel-sched.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -24,10 +25,20 @@ entry:
 ; Make sure that we don't schedule all of the isels together, they should be
 ; intermixed with the adds because each isel starts a new dispatch group.
 ; CHECK-LABEL: @foo
+; CHECK-NO-ISEL-LABEL: @foo
 ; CHECK: isel
+; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 7, 12, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 7, 11, 0
 ; CHECK: addi
 ; CHECK: isel
+; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 10, 11, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 10, 12, 0
 ; CHECK: blr
 
 attributes #0 = { nounwind }
-
diff --git a/test/CodeGen/PowerPC/ppc-crbits-onoff.ll b/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
index fbf69d5319b..0e7f8f1bc66 100644
--- a/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
+++ b/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -12,10 +13,16 @@ entry:
   ret i32 %and
 
 ; CHECK-LABEL: @crbitsoff
+; CHECK-NO-ISEL-LABEL: @crbitsoff
 ; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
 ; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]
+; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 4, 5, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 4, 0, 0
 ; CHECK: and 3, [[REG4]], [[REG3]]
 ; CHECK: blr
 }
@@ -29,11 +36,17 @@ entry:
   ret i32 %and
 
 ; CHECK-LABEL: @crbitson
+; CHECK-NO-ISEL-LABEL: @crbitson
 ; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
 ; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: crorc [[REG3:[0-9]+]],
 ; CHECK: isel 3, 0, [[REG2]], [[REG3]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
diff --git a/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/test/CodeGen/PowerPC/select-i1-vs-i1.ll
index a8f1ef1dd28..f2b8e09a1c1 100644
--- a/test/CodeGen/PowerPC/select-i1-vs-i1.ll
+++ b/test/CodeGen/PowerPC/select-i1-vs-i1.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -15,10 +16,17 @@ entry:
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32slt
+; CHECK-NO-ISEL-LABEL: @testi32slt
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -30,11 +38,17 @@ entry:
   %cond = select i1 %cmp3, i32 %a1, i32 %a2
   ret i32 %cond
 
-; CHECK-LABEL: @testi32ult
+; CHECK-NO-ISEL-LABEL: @testi32ult
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -47,10 +61,17 @@ entry:
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32sle
+; CHECK-NO-ISEL-LABEL: @testi32sle
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -63,10 +84,17 @@ entry:
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32ule
+; CHECK-NO-ISEL-LABEL: @testi32ule
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -79,10 +107,17 @@ entry:
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32eq
+; CHECK-NO-ISEL-LABEL: @testi32eq
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -95,10 +130,17 @@ entry:
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32sge
+; CHECK-NO-ISEL-LABEL: @testi32sge
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -111,10 +153,17 @@ entry:
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32uge
+; CHECK-NO-ISEL-LABEL: @testi32uge
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -127,10 +176,17 @@ entry:
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32sgt
+; CHECK-NO-ISEL-LABEL: @testi32sgt
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -143,10 +199,17 @@ entry:
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32ugt
+; CHECK-NO-ISEL-LABEL: @testi32ugt
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -159,10 +222,17 @@ entry:
   ret i32 %cond
 
 ; CHECK-LABEL: @testi32ne
+; CHECK-NO-ISEL-LABEL: @testi32ne
 ; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -175,10 +245,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64slt
+; CHECK-NO-ISEL-LABEL: @testi64slt
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -191,10 +268,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64ult
+; CHECK-NO-ISEL-LABEL: @testi64ult
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -207,10 +291,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64sle
+; CHECK-NO-ISEL-LABEL: @testi64sle
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -223,10 +314,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64ule
+; CHECK-NO-ISEL-LABEL: @testi64ule
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -239,10 +337,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64eq
+; CHECK-NO-ISEL-LABEL: @testi64eq
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -255,10 +360,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64sge
+; CHECK-NO-ISEL-LABEL: @testi64sge
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -271,10 +383,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64uge
+; CHECK-NO-ISEL-LABEL: @testi64uge
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -287,10 +406,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64sgt
+; CHECK-NO-ISEL-LABEL: @testi64sgt
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -303,10 +429,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64ugt
+; CHECK-NO-ISEL-LABEL: @testi64ugt
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
@@ -319,10 +452,17 @@ entry:
   ret i64 %cond
 
 ; CHECK-LABEL: @testi64ne
+; CHECK-NO-ISEL-LABEL: @testi64ne
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
 ; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
diff --git a/test/CodeGen/PowerPC/subreg-postra-2.ll b/test/CodeGen/PowerPC/subreg-postra-2.ll
index fb33b9e3542..338000cd8ba 100644
--- a/test/CodeGen/PowerPC/subreg-postra-2.ll
+++ b/test/CodeGen/PowerPC/subreg-postra-2.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -31,10 +32,16 @@ while.end418:                                     ; preds = %wait_on_buffer.exit
   br i1 %tobool419, label %if.end421, label %if.then420
 
 ; CHECK-LABEL: @jbd2_journal_commit_transaction
+; CHECK-NO-ISEL-LABEL: @jbd2_journal_commit_transaction
 ; CHECK: andi.
 ; CHECK: crmove [[REG:[0-9]+]], 1
 ; CHECK: stdcx.
 ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
+; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 4, 7, 0
+; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
+; CHECK-NO-ISEL: [[TRUE]]
+; CHECK-NO-ISEL-NEXT: addi 4, 3, 0
 
 if.then420:                                       ; preds = %while.end418
   unreachable
diff --git a/test/CodeGen/PowerPC/subreg-postra.ll b/test/CodeGen/PowerPC/subreg-postra.ll
index 877ceccd918..7557e4e9a46 100644
--- a/test/CodeGen/PowerPC/subreg-postra.ll
+++ b/test/CodeGen/PowerPC/subreg-postra.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -145,10 +146,15 @@ wait_on_buffer.exit1319:                          ; preds = %while.body392
   br i1 %inp8, label %while.end418, label %while.body392
 
 ; CHECK-LABEL: @jbd2_journal_commit_transaction
+; CHECK-NO-ISEL-LABEL: @jbd2_journal_commit_transaction
 ; CHECK: andi.
 ; CHECK: crmove
 ; CHECK: stdcx.
 ; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}},
+; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NO-ISEL: ori 30, 3, 0
+; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
+
 
 while.end418:                                     ; preds = %wait_on_buffer.exit1319, %do.body378
   %err.4.lcssa = phi i32 [ %inp2, %do.body378 ], [ %.err.4, %wait_on_buffer.exit1319 ]