[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLT/SETGT

As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314055 91177308-0d34-0410-b5e6-96231b3b80d8

8 files changed, 610 insertions, 7 deletions

diff --git a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
index 059665adc35..c8c5108673d 100644
--- a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
+++ b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -115,10 +115,9 @@ define signext i32 @zeroEqualityTest04() {
 ; CHECK-NEXT:    li 12, -1
 ; CHECK-NEXT:    isel 5, 12, 11, 0
 ; CHECK-NEXT:  .LBB3_3: # %endblock
-; CHECK-NEXT:    cmpwi 5, 1
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    isel 3, 4, 3, 0
+; CHECK-NEXT:    neg 3, 5
+; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer2 to i8*), i64 16)
   %not.cmp = icmp slt i32 %call, 1
diff --git a/test/CodeGen/PowerPC/no-pref-jumps.ll b/test/CodeGen/PowerPC/no-pref-jumps.ll
index 71f79409820..44643df09bd 100644
--- a/test/CodeGen/PowerPC/no-pref-jumps.ll
+++ b/test/CodeGen/PowerPC/no-pref-jumps.ll
@@ -11,9 +11,13 @@ entry:
   br i1 %or.cond, label %if.then, label %if.else
 
 ; CHECK-LABEL: @foo
-; CHECK: cmpwi
-; CHECK: cmpwi
-; CHECK: cror
+; CHECK: li
+; CHECK: li
+; CHECK: sub
+; CHECK: sub
+; CHECK: rldicl
+; CHECK: rldicl
+; CHECK: or.
 ; CHECK: blr
 
 if.then:                                          ; preds = %entry
diff --git a/test/CodeGen/PowerPC/testComparesigtsc.ll b/test/CodeGen/PowerPC/testComparesigtsc.ll
new file mode 100644
index 00000000000..27692e0f541
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesigtsc.ll
@@ -0,0 +1,116 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_z(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_sext_z:
+; CHECK: neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_igtsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = zext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_igtsc_sext_z_store:
+; CHECK:       neg [[REG2:r[0-9]+]], r3
+; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesigtsi.ll b/test/CodeGen/PowerPC/testComparesigtsi.ll
new file mode 100644
index 00000000000..a6eda86e5fc
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesigtsi.ll
@@ -0,0 +1,116 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_z(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_sext_z:
+; CHECK:  neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK-NEXT: blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_igtsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_igtsi_sext_z_store:
+; CHECK: neg [[REG:r[0-9]+]], r3
+; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesigtss.ll b/test/CodeGen/PowerPC/testComparesigtss.ll
new file mode 100644
index 00000000000..a79d4887229
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesigtss.ll
@@ -0,0 +1,117 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG1:r[0-9]+]], r4, r3
+; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_z(i16 signext %a) {
+; CHECK-LABEL: test_igtss_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv1 = zext i1 %cmp to i32
+  ret i32 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_igtss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_igtss_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK:    neg [[REG2:r[0-9]+]], r3
+; CHECK-NEXT:    sradi r3, [[REG2]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG1:r[0-9]+]], r4, r3
+; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_igtss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r4, r3
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; FIXME
+; Function Attrs: norecurse nounwind
+define void @test_igtss_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igtss_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = zext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_igtss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_igtss_sext_z_store:
+; CHECK:       neg [[REG2:r[0-9]+]], r3
+; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv2 = sext i1 %cmp to i16
+  store i16 %conv2, i16* @glob, align 2
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesiltsc.ll b/test/CodeGen/PowerPC/testComparesiltsc.ll
new file mode 100644
index 00000000000..54e278d4321
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesiltsc.ll
@@ -0,0 +1,83 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i8 0, align 1
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsc_sext_z(i8 signext %a) {
+; CHECK-LABEL: test_iltsc_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
+; CHECK-LABEL: test_iltsc_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @glob, align 1
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsc_sext_z_store(i8 signext %a) {
+; CHECK-LABEL: test_iltsc_sext_z_store:
+; CHECK: srwi {{r[0-9]+}}, r3, 7
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %conv2 = sext i1 %cmp to i8
+  store i8 %conv2, i8* @glob, align 1
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesiltsi.ll b/test/CodeGen/PowerPC/testComparesiltsi.ll
new file mode 100644
index 00000000000..8a5cdd86921
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesiltsi.ll
@@ -0,0 +1,85 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltsi_sext_z(i32 signext %a) {
+; CHECK-LABEL: test_iltsi_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: test_iltsi_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltsi_sext_z_store(i32 signext %a) {
+; CHECK-LABEL: test_iltsi_sext_z_store:
+; CHECK:    srawi {{r[0-9]+}}, r3, 31
+; CHECK:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @glob, align 4
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesiltss.ll b/test/CodeGen/PowerPC/testComparesiltss.ll
new file mode 100644
index 00000000000..a3ec96dda11
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesiltss.ll
@@ -0,0 +1,83 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+@glob = common local_unnamed_addr global i16 0, align 2
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
+; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @test_iltss_sext_z(i16 signext %a) {
+; CHECK-LABEL: test_iltss_sext_z:
+; CHECK:       srawi r3, r3, 31
+; CHECK-NEXT:  blr
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
+; CHECK-LABEL: test_iltss_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:         sub [[REG:r[0-9]+]], r3, r4
+; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @glob, align 2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_iltss_sext_z_store(i16 signext %a) {
+; CHECK-LABEL: test_iltss_sext_z_store:
+; CHECK:       srwi {{r[0-9]+}}, r3, 15
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %sub = sext i1 %cmp to i16
+  store i16 %sub, i16* @glob, align 2
+  ret void
+}