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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-11-28 20:21:15 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-11-28 20:21:15 +0000 |
| commit | 722a86f91d52d85e7fe8bb01db19f669e7028210 (patch) | |
| tree | 6d8cc7a54590fb734e292852f68e6a212244cadd /test/CodeGen/PowerPC | |
| parent | c0c70f9b720e81bbb5adf9ab24e68ae90de390c5 (diff) | |
[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
The IRTranslator cannot generate these instructions at the moment so there's no
issue with not having implemented ISel for them yet. D40092 will add
G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_* to the IRTranslator and a
further patch will add support for lowering G_ATOMIC_CMPXCHG_WITH_SUCCESS into
G_ATOMIC_CMPXCHG with an external success check via the `Lower` action.
The separation of G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMIC_CMPXCHG is
to import SelectionDAG rules while still supporting targets that prefer to
custom lower the original LLVM-IR-like operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319216 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
0 files changed, 0 insertions, 0 deletions