diff options
author | Matthias Braun <matze@braunis.de> | 2016-08-24 01:32:41 +0000 |
---|---|---|
committer | Matthias Braun <matze@braunis.de> | 2016-08-24 01:32:41 +0000 |
commit | 66489736bfd79ad1fd3e2e49b10b747970ab2686 (patch) | |
tree | 2f79d2f6012b144740cc06c9a9da4fa9a91d4a08 /test/CodeGen/PowerPC | |
parent | 459280c4f328b9a0c9145975437d05c465d87fc7 (diff) |
MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.
Specifying isSSA is an extra line at best and results in invalid MI at
worst. Compute the value instead.
Differential Revision: http://reviews.llvm.org/D22722
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279600 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
-rw-r--r-- | test/CodeGen/PowerPC/aantidep-def-ec.mir | 1 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/addisdtprelha-nonr3.mir | 1 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 1 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 1 |
4 files changed, 0 insertions, 4 deletions
diff --git a/test/CodeGen/PowerPC/aantidep-def-ec.mir b/test/CodeGen/PowerPC/aantidep-def-ec.mir index 809d3693af6..31b256c7370 100644 --- a/test/CodeGen/PowerPC/aantidep-def-ec.mir +++ b/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -46,7 +46,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: true allVRegsAllocated: true -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false liveins: diff --git a/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir index 6f52aa21a77..f157b47a172 100644 --- a/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ b/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -28,7 +28,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: true -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false frameInfo: diff --git a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir index 76702ce50fd..479adbba90e 100644 --- a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir +++ b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir @@ -40,7 +40,6 @@ name: main alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: diff --git a/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir index b835ce71c41..942b44c4e4c 100644 --- a/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ b/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -34,7 +34,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false allVRegsAllocated: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: |