[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE

As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential review.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314073 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 524 insertions, 0 deletions

diff --git a/test/CodeGen/PowerPC/testComparesigesll.ll b/test/CodeGen/PowerPC/testComparesigesll.ll
new file mode 100644
index 00000000000..95be923b88a
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesigesll.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_igesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_igesll_z(i64 %a) {
+; CHECK-LABEL: test_igesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_igesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_igesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_igesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r3, 63
+; CHECK:    subfc r3, r4, r3
+; CHECK:    rldicl r3, r4, 1, 63
+; CHECK:    adde r3, r6, r3
+; CHECK:    std r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_igesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    adde r3, r6, r3
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_igesll_z_store(i64 %a) {
+; CHECK-LABEL: test_igesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_igesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_igesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesilesll.ll b/test/CodeGen/PowerPC/testComparesilesll.ll
new file mode 100644
index 00000000000..04381c5ed28
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesilesll.ll
@@ -0,0 +1,130 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_ilesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i32 @test_ilesll_z(i64 %a) {
+; CHECK-LABEL: test_ilesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @test_ilesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_ilesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @test_ilesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r4, 63
+; CHECK:    subfc r4, r3, r4
+; CHECK:    rldicl r3, r3, 1, 63
+; CHECK:    adde r3, r6, r3
+; CHECK:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_ilesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r4, 63
+; CHECK-DAG:    rldicl r3, r3, 1, 63
+; CHECK-DAG:    subfc r4, r3, r4
+; CHECK:    adde r3, r6, r3
+; CHECK:    neg r3, r3
+; CHECK:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_ilesll_z_store(i64 %a) {
+; CHECK-LABEL: test_ilesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_ilesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_ilesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesllgesll.ll b/test/CodeGen/PowerPC/testComparesllgesll.ll
new file mode 100644
index 00000000000..e75c0fad513
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesllgesll.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define i64 @test_llgesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesll_z(i64 %a) {
+; CHECK-LABEL: test_llgesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @test_llgesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_llgesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @test_llgesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r3, 63
+; CHECK:    subfc r3, r4, r3
+; CHECK:    rldicl r3, r4, 1, 63
+; CHECK:    adde r3, r6, r3
+; CHECK:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llgesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r6, r3, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    adde r3, r6, r3
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llgesll_z_store(i64 %a) {
+; CHECK-LABEL: test_llgesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+define void @test_llgesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llgesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, -1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/testCompareslllesll.ll b/test/CodeGen/PowerPC/testCompareslllesll.ll
new file mode 100644
index 00000000000..1b6c204443b
--- /dev/null
+++ b/test/CodeGen/PowerPC/testCompareslllesll.ll
@@ -0,0 +1,138 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_lllesll:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll_sext(i64 %a, i64 %b)  {
+; CHECK-LABEL: test_lllesll_sext:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r12, r3, r4
+; CHECK-NEXT:    adde r3, r5, r6
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll_z(i64 %a)  {
+; CHECK-LABEL: test_lllesll_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll_sext_z(i64 %a)  {
+; CHECK-LABEL: test_lllesll_sext_z:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    or r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lllesll_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r4, 63
+; CHECK:    subfc r4, r3, r4
+; CHECK:    rldicl r3, r3, 1, 63
+; CHECK:    adde r3, r6, r3
+; CHECK:    std r3,
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lllesll_sext_store:
+; CHECK:       # BB#0: # %entry
+; CHECK:    sradi r6, r4, 63
+; CHECK-DAG:    rldicl r3, r3, 1, 63
+; CHECK-DAG:    subfc r4, r3, r4
+; CHECK:    adde r3, r6, r3
+; CHECK:    neg r3, r3
+; CHECK:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_z_store(i64 %a) {
+; CHECK-LABEL: test_lllesll_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_lllesll_sext_z_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    or r3, r5, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @glob, align 8
+  ret void
+}