diff options
author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2015-08-13 17:40:44 +0000 |
---|---|---|
committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2015-08-13 17:40:44 +0000 |
commit | 31f6eee816354985afaa63fabf61d88271627811 (patch) | |
tree | ae75d01d151fdde3a43ea5d44640d67623d0abf3 /test/CodeGen/PowerPC | |
parent | ea56ef761a84bb8895ad74bc8cf5fb91f6c78695 (diff) |
Scalar to vector conversions using direct moves
This patch corresponds to review:
http://reviews.llvm.org/D11471
It improves the code generated for converting a scalar to a vector value. With
direct moves from GPRs to VSRs, we no longer require expensive stack operations
for this. Subsequent patches will handle the reverse case and more general
operations between vectors and their scalar elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244921 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
-rw-r--r-- | test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll | 24 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll | 79 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/vsx.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/vsx_scalar_ld_st.ll | 6 |
4 files changed, 92 insertions, 23 deletions
diff --git a/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll b/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll index 1d9b6482314..4868a18a95a 100644 --- a/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll +++ b/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll @@ -24,8 +24,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z6testfcc ; CHECK: mtvsrwz [[MOVEREG01:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG01]] +; CHECK: xscvuxdsp 1, [[MOVEREG01]] } ; Function Attrs: nounwind @@ -77,8 +76,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z7testfuch ; CHECK: mtvsrwz [[MOVEREG03:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG03]] +; CHECK: xscvuxdsp 1, [[MOVEREG03]] } ; Function Attrs: nounwind @@ -130,8 +128,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z6testfss ; CHECK: mtvsrwa [[MOVEREG05:[0-9]+]], 3 -; FIXME: Once we have XSCVSXDSP implemented, this will change -; CHECK: fcfids 1, [[MOVEREG05]] +; CHECK: xscvsxdsp 1, [[MOVEREG05]] } ; Function Attrs: nounwind @@ -183,8 +180,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z7testfust ; CHECK: mtvsrwz [[MOVEREG07:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG07]] +; CHECK: xscvuxdsp 1, [[MOVEREG07]] } ; Function Attrs: nounwind @@ -236,8 +232,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z6testfii ; CHECK: mtvsrwa [[MOVEREG09:[0-9]+]], 3 -; FIXME: Once we have XSCVSXDSP implemented, this will change -; CHECK: fcfids 1, [[MOVEREG09]] +; CHECK: xscvsxdsp 1, [[MOVEREG09]] } ; Function Attrs: nounwind @@ -289,8 +284,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z7testfuij ; CHECK: mtvsrwz [[MOVEREG11:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG11]] +; CHECK: xscvuxdsp 1, [[MOVEREG11]] } ; Function Attrs: nounwind @@ -342,8 +336,7 @@ entry: ret float %conv ; CHECK-LABEL:@_Z7testfllx ; CHECK: mtvsrd [[MOVEREG13:[0-9]+]], 3 -; FIXME: Once we have XSCVSXDSP implemented, this will change -; CHECK: fcfids 1, [[MOVEREG13]] +; CHECK: xscvsxdsp 1, [[MOVEREG13]] } ; Function Attrs: nounwind @@ -395,8 +388,7 @@ entry: ret float %conv ; CHECK-LABEL: @_Z8testfully ; CHECK: mtvsrd [[MOVEREG15:[0-9]+]], 3 -; FIXME: Once we have XSCVUXDSP implemented, this will change -; CHECK: fcfidus 1, [[MOVEREG15]] +; CHECK: xscvuxdsp 1, [[MOVEREG15]] } ; Function Attrs: nounwind diff --git a/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll new file mode 100644 index 00000000000..535ddf4f574 --- /dev/null +++ b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -0,0 +1,79 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE + +; The build[csilf] functions simply test the scalar_to_vector handling with +; direct moves. This corresponds to the "insertelement" instruction. Subsequent +; to this, there will be a splat corresponding to the shufflevector. + +; Function Attrs: nounwind +define <16 x i8> @buildc(i8 zeroext %a) { +entry: + %a.addr = alloca i8, align 1 + store i8 %a, i8* %a.addr, align 1 + %0 = load i8, i8* %a.addr, align 1 + %splat.splatinsert = insertelement <16 x i8> undef, i8 %0, i32 0 + %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer + ret <16 x i8> %splat.splat +; CHECK: sldi [[REG1:[0-9]+]], 3, 56 +; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] +; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 +; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +} + +; Function Attrs: nounwind +define <8 x i16> @builds(i16 zeroext %a) { +entry: + %a.addr = alloca i16, align 2 + store i16 %a, i16* %a.addr, align 2 + %0 = load i16, i16* %a.addr, align 2 + %splat.splatinsert = insertelement <8 x i16> undef, i16 %0, i32 0 + %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer + ret <8 x i16> %splat.splat +; CHECK: sldi [[REG1:[0-9]+]], 3, 48 +; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] +; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 +; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +} + +; Function Attrs: nounwind +define <4 x i32> @buildi(i32 zeroext %a) { +entry: + %a.addr = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + %0 = load i32, i32* %a.addr, align 4 + %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 + %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + ret <4 x i32> %splat.splat +; CHECK: sldi [[REG1:[0-9]+]], 3, 32 +; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] +; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 +; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +} + +; Function Attrs: nounwind +define <2 x i64> @buildl(i64 %a) { +entry: + %a.addr = alloca i64, align 8 + store i64 %a, i64* %a.addr, align 8 + %0 = load i64, i64* %a.addr, align 8 + %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 + %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer + ret <2 x i64> %splat.splat +; CHECK: mtvsrd {{[0-9]+}}, 3 +; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 +; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +} + +; Function Attrs: nounwind +define <4 x float> @buildf(float %a) { +entry: + %a.addr = alloca float, align 4 + store float %a, float* %a.addr, align 4 + %0 = load float, float* %a.addr, align 4 + %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 + %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer + ret <4 x float> %splat.splat +; CHECK: xscvdpspn {{[0-9]+}}, 1 +; CHECK-LE: xscvdpspn [[REG1:[0-9]+]], 1 +; CHECK-LE: xxsldwi {{[0-9]+}}, [[REG1]], [[REG1]], 1 +} diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index dceb2516c69..b4b1d248d1a 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -1226,11 +1226,11 @@ define <2 x i32> @test80(i32 %v) { ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test80 -; CHECK-LE-DAG: addi [[R1:[0-9]+]], 1, -16 +; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3 ; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI -; CHECK-LE-DAG: lxvd2x [[V1:[0-9]+]], 0, [[R1]] +; CHECK-LE-DAG: xxswapd [[V1:[0-9]+]], [[R1]] ; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]] -; CHECK-LE-DAG: xxswapd 34, [[V1]] +; CHECK-LE-DAG: xxspltd 34, [[V1]] ; CHECK-LE-DAG: xxswapd 35, [[V2]] ; CHECK-LE: vaddudm 2, 2, 3 ; CHECK-LE: blr diff --git a/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll index 10297088596..c2cb71c5888 100644 --- a/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll +++ b/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll @@ -55,8 +55,7 @@ entry: ret void ; CHECK-LABEL: @intToFlt ; CHECK: lxsiwax [[REGLD2:[0-9]+]], -; FIXME: the below will change when the VSX form is implemented -; CHECK: fcfids {{[0-9]}}, [[REGLD2]] +; CHECK: xscvsxdsp {{[0-9]}}, [[REGLD2]] } ; Function Attrs: nounwind @@ -108,8 +107,7 @@ entry: ret void ; CHECK-LABEL: @uIntToFlt ; CHECK: lxsiwzx [[REGLD4:[0-9]+]], -; FIXME: the below will change when the VSX form is implemented -; CHECK: fcfidus {{[0-9]+}}, [[REGLD4]] +; CHECK: xscvuxdsp {{[0-9]+}}, [[REGLD4]] } ; Function Attrs: nounwind |