diff options
| author | Craig Topper <craig.topper@intel.com> | 2017-12-22 17:18:13 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-22 17:18:13 +0000 |
| commit | 15c5ab82da5355381525fe3f4f1c2acfea22cf29 (patch) | |
| tree | 9b7917202831ee7810d5b6a10466285bc97629ca /test/CodeGen/PowerPC | |
| parent | 7c7ca957d2df1e4bc920aca54d307b01245d9fd5 (diff) | |
[SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left.
This seems to improve X86's ability to match this into an address computation. Otherwise the other operand gets assigned to the base register and the stack pointer + frame index ends up in the index register. But index registers can't encode ESP/RSP so we end up having to move it into another register to meet the constraint.
I could try to improve the address matcher in X86, but swapping the producer seemed easier. Several other places already have the operands in this order so this is at least consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321370 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
| -rw-r--r-- | test/CodeGen/PowerPC/variable_elem_vec_extracts.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll b/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll index 82c6c318abd..247961e85b1 100644 --- a/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll +++ b/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll @@ -25,7 +25,7 @@ entry: ; CHECK: extsw 3, [[RSHREG]] ; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29 ; CHECK-P7-DAG: stxvw4x 34, -; CHECK-P7: lwax 3, [[ELEMOFFREG]], +; CHECK-P7: lwax 3, 3, [[ELEMOFFREG]] ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 2 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 2 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] @@ -54,7 +54,7 @@ entry: ; CHECK: mfvsrd 3, ; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 3, 28, 28 ; CHECK-P7-DAG: stxvd2x 34, -; CHECK-P7: ldx 3, [[ELEMOFFREG]], +; CHECK-P7: ldx 3, 3, [[ELEMOFFREG]] ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] @@ -77,7 +77,7 @@ entry: ; CHECK: xscvspdpn 1, ; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29 ; CHECK-P7-DAG: stxvw4x 34, -; CHECK-P7: lfsx 1, [[ELEMOFFREG]], +; CHECK-P7: lfsx 1, 3, [[ELEMOFFREG]] ; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] ; CHECK-BE: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] |