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| author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-10-02 09:24:00 +0000 |
|---|---|---|
| committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-10-02 09:24:00 +0000 |
| commit | 86ba0ab2a727acb8c19079cc2d6ea9dc66187372 (patch) | |
| tree | 2accdd4858043b1883fd43164620da6c1e882ff8 /test/CodeGen/PowerPC/zext-bitperm.ll | |
| parent | 37eec1b4487264448c01314f4cfa90209ab7732f (diff) | |
[PowerPC] support ZERO_EXTEND in tryBitPermutation
This patch add a support of ISD::ZERO_EXTEND in PPCDAGToDAGISel::tryBitPermutation to increase the opportunity to use rotate-and-mask by reordering ZEXT and ANDI.
Since tryBitPermutation stops analyzing nodes if it hits a ZEXT node while traversing SDNodes, we want to avoid ZEXT between two nodes that can be folded into a rotate-and-mask instruction.
For example, we allow these nodes
t9: i32 = add t7, Constant:i32<1>
t11: i32 = and t9, Constant:i32<255>
t12: i64 = zero_extend t11
t14: i64 = shl t12, Constant:i64<2>
to be folded into a rotate-and-mask instruction.
Such case often happens in array accesses with logical AND operation in the index, e.g. array[i & 0xFF];
Differential Revision: https://reviews.llvm.org/D37514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314655 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/zext-bitperm.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/zext-bitperm.ll | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/zext-bitperm.ll b/test/CodeGen/PowerPC/zext-bitperm.ll new file mode 100644 index 00000000000..b6d751d6f2f --- /dev/null +++ b/test/CodeGen/PowerPC/zext-bitperm.ll @@ -0,0 +1,23 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s + +; Test case for PPCTargetLowering::extendSubTreeForBitPermutation. +; We expect mask and rotate are folded into a rlwinm instruction. + +define zeroext i32 @func(i32* %p, i32 zeroext %i) { +; CHECK-LABEL: @func +; CHECK: addi [[REG1:[0-9]+]], 4, 1 +; CHECK: rlwinm [[REG2:[0-9]+]], [[REG1]], 2, 22, 29 +; CHECK-NOT: sldi +; CHECK: lwzx 3, 3, [[REG2]] +; CHECK: blr +entry: + %add = add i32 %i, 1 + %and = and i32 %add, 255 + %idxprom = zext i32 %and to i64 + %arrayidx = getelementptr inbounds i32, i32* %p, i64 %idxprom + %0 = load i32, i32* %arrayidx, align 4 + ret i32 %0 +} + |