diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2015-02-25 21:36:59 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2015-02-25 21:36:59 +0000 |
| commit | 7840990de8f102bf83ee297e74f225b109228512 (patch) | |
| tree | ee115c8e4342e2b29c0348e033acbfe8564a77b3 /test/CodeGen/PowerPC/vec-abi-align.ll | |
| parent | e9e16aa4a5fe2da7fb9621080cc9ef13a3604549 (diff) | |
[PowerPC] Make LDtocL and friends invariant loads
LDtocL, and other loads that roughly correspond to the TOC_ENTRY SDAG node,
represent loads from the TOC, which is invariant. As a result, these loads can
be hoisted out of loops, etc. In order to do this, we need to generate
GOT-style MMOs for TOC_ENTRY, which requires treating it as a legitimate memory
intrinsic node type. Once this is done, the MMO transfer is automatically
handled for TableGen-driven instruction selection, and for nodes generated
directly in PPCISelDAGToDAG, we need to transfer the MMOs manually.
Also, we were not transferring MMOs associated with pre-increment loads, so do
that too.
Lastly, this fixes an exposed bug where R30 was not added as a defined operand of
UpdateGBR.
This problem was highlighted by an example (used to generate the test case)
posted to llvmdev by Francois Pichet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230553 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/vec-abi-align.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/vec-abi-align.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/test/CodeGen/PowerPC/vec-abi-align.ll b/test/CodeGen/PowerPC/vec-abi-align.ll index 5075ff2b8c0..2ec57af3513 100644 --- a/test/CodeGen/PowerPC/vec-abi-align.ll +++ b/test/CodeGen/PowerPC/vec-abi-align.ll @@ -35,17 +35,17 @@ entry: ret void ; CHECK-LABEL: @test2 -; CHECK: ld {{[0-9]+}}, 112(1) -; CHECK: li [[REG16:[0-9]+]], 16 -; CHECK: addi [[REGB:[0-9]+]], 1, 112 -; CHECK: lvx 2, [[REGB]], [[REG16]] +; CHECK-DAG: ld {{[0-9]+}}, 112(1) +; CHECK-DAG: li [[REG16:[0-9]+]], 16 +; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 112 +; CHECK-DAG: lvx 2, [[REGB]], [[REG16]] ; CHECK: blr ; CHECK-VSX-LABEL: @test2 -; CHECK-VSX: ld {{[0-9]+}}, 112(1) -; CHECK-VSX: li [[REG16:[0-9]+]], 16 -; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 112 -; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] +; CHECK-VSX-DAG: ld {{[0-9]+}}, 112(1) +; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16 +; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 112 +; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] ; CHECK-VSX: blr } @@ -61,17 +61,17 @@ entry: ret void ; CHECK-LABEL: @test3 -; CHECK: ld {{[0-9]+}}, 128(1) -; CHECK: li [[REG16:[0-9]+]], 16 -; CHECK: addi [[REGB:[0-9]+]], 1, 128 -; CHECK: lvx 2, [[REGB]], [[REG16]] +; CHECK-DAG: ld {{[0-9]+}}, 128(1) +; CHECK-DAG: li [[REG16:[0-9]+]], 16 +; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 128 +; CHECK-DAG: lvx 2, [[REGB]], [[REG16]] ; CHECK: blr ; CHECK-VSX-LABEL: @test3 -; CHECK-VSX: ld {{[0-9]+}}, 128(1) -; CHECK-VSX: li [[REG16:[0-9]+]], 16 -; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 128 -; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] +; CHECK-VSX-DAG: ld {{[0-9]+}}, 128(1) +; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16 +; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 128 +; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] ; CHECK-VSX: blr } |