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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-09-23 12:53:03 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-09-23 12:53:03 +0000 |
| commit | 2e0c5c57b49457ddccb757848f06a6eca8f14f8a (patch) | |
| tree | e0e6e7ad9b068b3f72a4f31ac454ca38b8f8c81c /test/CodeGen/PowerPC/testComparesllltus.ll | |
| parent | 47a09dc91f35ff9333032dd6d56429b247ed9972 (diff) | |
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULT/SETUGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314062 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/testComparesllltus.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/testComparesllltus.ll | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/testComparesllltus.ll b/test/CodeGen/PowerPC/testComparesllltus.ll new file mode 100644 index 00000000000..e4006965158 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllltus.ll @@ -0,0 +1,59 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llltus: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llltus_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +; Function Attrs: norecurse nounwind +define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llltus_store: +; CHECK: sub [[REG:r[2-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) { +; CHECK-LABEL: test_llltus_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp ult i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} |