[PowerPC] Revert r310346 (and followups r310356 & r310424) which

introduce a miscompile bug.

There appears to be a bug where the generated code to extract the sign
bit doesn't work correctly for 32-bit inputs. I've replied to the
original commit pointing out the problem. I think I see by inspection
(and reading the manual for PPC) how to fix this, but I can't be 100%
confident and I also don't know what the best way to test this is.
Currently it seems nearly impossible to get the backend to hit this code
path, but the patch autohr is likely in a better position to craft such
test cases than I am, and based on where the bug is it should be easily
done.

Original commit message for r310346:
"""
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE

Adds handling for SETLE/SETGE comparisons on i32 values. Furthermore, it
adds the handling for the special case where RHS == 0.

Differential Revision: https://reviews.llvm.org/D34048
"""

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310809 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 68 deletions

diff --git a/test/CodeGen/PowerPC/testComparesllgesc.ll b/test/CodeGen/PowerPC/testComparesllgesc.ll
deleted file mode 100644
index 58f4aa92914..00000000000
--- a/test/CodeGen/PowerPC/testComparesllgesc.ll
+++ /dev/null
@@ -1,68 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
-; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-@glob = common local_unnamed_addr global i8 0, align 1
-
-define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: test_llgesc:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-NEXT:    xori r3, r3, 1
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp sge i8 %a, %b
-  %conv3 = zext i1 %cmp to i64
-  ret i64 %conv3
-}
-
-define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: test_llgesc_sext:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    subf r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-NEXT:    addi r3, r3, -1
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp sge i8 %a, %b
-  %conv3 = sext i1 %cmp to i64
-  ret i64 %conv3
-}
-
-define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: test_llgesc_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-NEXT:    xori r3, r3, 1
-; CHECK-NEXT:    stb r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp sge i8 %a, %b
-  %conv3 = zext i1 %cmp to i8
-  store i8 %conv3, i8* @glob, align 1
-  ret void
-}
-
-define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: test_llgesc_sext_store:
-; CHECK:       # BB#0: # %entry
-; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
-; CHECK-NEXT:    subf r3, r4, r3
-; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-NEXT:    addi r3, r3, -1
-; CHECK-NEXT:    stb r3, 0(r12)
-; CHECK-NEXT:    blr
-entry:
-  %cmp = icmp sge i8 %a, %b
-  %conv3 = sext i1 %cmp to i8
-  store i8 %conv3, i8* @glob, align 1
-  ret void
-}