diff options
author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-09-23 04:41:34 +0000 |
---|---|---|
committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-09-23 04:41:34 +0000 |
commit | 73de9558751c1c477edc198a8c49f6c16d3d7389 (patch) | |
tree | 96c43393e415ef318c6a769e468f27bda7d7a93b /test/CodeGen/PowerPC/testComparesiltss.ll | |
parent | 1fe9675efd21770e045b4885a5c708b0f3595aa4 (diff) |
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLT/SETGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314055 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/testComparesiltss.ll')
-rw-r--r-- | test/CodeGen/PowerPC/testComparesiltss.ll | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/testComparesiltss.ll b/test/CodeGen/PowerPC/testComparesiltss.ll new file mode 100644 index 00000000000..a3ec96dda11 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiltss.ll @@ -0,0 +1,83 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltss(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iltss: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iltss_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 +; CHECK-NEXT: sradi r3, [[REG]], 63 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_iltss_sext_z(i16 signext %a) { +; CHECK-LABEL: test_iltss_sext_z: +; CHECK: srawi r3, r3, 31 +; CHECK-NEXT: blr +entry: + %cmp = icmp slt i16 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +; Function Attrs: norecurse nounwind +define void @test_iltss_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iltss_store: +; CHECK: # BB#0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 +entry: + %cmp = icmp slt i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iltss_sext_store: +; CHECK: # BB#0: # %entry +; CHECK: sub [[REG:r[0-9]+]], r3, r4 +; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 +entry: + %cmp = icmp slt i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +; Function Attrs: norecurse nounwind +define void @test_iltss_sext_z_store(i16 signext %a) { +; CHECK-LABEL: test_iltss_sext_z_store: +; CHECK: srwi {{r[0-9]+}}, r3, 15 +entry: + %cmp = icmp slt i16 %a, 0 + %sub = sext i1 %cmp to i16 + store i16 %sub, i16* @glob, align 2 + ret void +} |