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| author | Michael Zuckerman <Michael.zuckerman@intel.com> | 2017-09-26 18:49:11 +0000 |
|---|---|---|
| committer | Michael Zuckerman <Michael.zuckerman@intel.com> | 2017-09-26 18:49:11 +0000 |
| commit | 9bfa11f2be523359f902358263ce7b5977b0cce0 (patch) | |
| tree | 9636551dc2137f4b8cb2aa183cc4ac64aed3d4a5 /test/CodeGen/PowerPC/testComparesigesll.ll | |
| parent | 4ab489f31f26cbaa9770c36dd836d63b21863b3e (diff) | |
[X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF{8|16|32} stride 3)
This patch expands the support of lowerInterleavedStore to {8|16|32}x8i stride 3.
LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=3 VF={8|16|32}) .
This patch is part two of two patches and it covers the store (interlevaed) side.
The patch goal is to optimize the following sequence:
a0 a1 a2 a3 a4 a5 a6 a7
b0 b1 b2 b3 b4 b5 b6 b7
c0 c1 c2 c3 c4 c5 c6 c7
into
a0 b0 c0 a1 b1 c1 a2 b2
c2 a3 b3 c3 a4 b4 c4 a5
b5 c5 a6 b6 c6 a7 b7 c7
Reviewers:
zvi
guyblank
dorit
Ayal
Differential Revision: https://reviews.llvm.org/D37117
Change-Id: I56ced8bcbea809a37654060771911ade20246ccc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314234 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/testComparesigesll.ll')
0 files changed, 0 insertions, 0 deletions