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author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-09-24 05:48:11 +0000 |
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committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-09-24 05:48:11 +0000 |
commit | 4eb888f6d2ab4b8f226b8839d40b3742ee286530 (patch) | |
tree | c6709ac09869a2e449f9e99802fc379d31e31780 /test/CodeGen/PowerPC/testComparesigesll.ll | |
parent | 213f7476549cce91b39e313cdac44c9200ea1639 (diff) |
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314073 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/testComparesigesll.ll')
-rw-r--r-- | test/CodeGen/PowerPC/testComparesigesll.ll | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/testComparesigesll.ll b/test/CodeGen/PowerPC/testComparesigesll.ll new file mode 100644 index 00000000000..95be923b88a --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigesll.ll @@ -0,0 +1,128 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i64 0, align 8 + +define signext i32 @test_igesll(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_igesll_sext(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r5, r3, 63 +; CHECK-NEXT: rldicl r6, r4, 1, 63 +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: adde r3, r5, r6 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define signext i32 @test_igesll_z(i64 %a) { +; CHECK-LABEL: test_igesll_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_igesll_sext_z(i64 %a) { +; CHECK-LABEL: test_igesll_sext_z: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igesll_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll_store: +; CHECK: # BB#0: # %entry +; CHECK: sradi r6, r3, 63 +; CHECK: subfc r3, r4, r3 +; CHECK: rldicl r3, r4, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_igesll_sext_store(i64 %a, i64 %b) { +; CHECK-LABEL: test_igesll_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sradi r6, r3, 63 +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: subfc r3, r4, r3 +; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: adde r3, r6, r3 +; CHECK-NEXT: neg r3, r3 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_igesll_z_store(i64 %a) { +; CHECK-LABEL: test_igesll_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: std r3, 0(r4) +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} + +define void @test_igesll_sext_z_store(i64 %a) { +; CHECK-LABEL: test_igesll_sext_z_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha +; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: std r3, +; CHECK-NEXT: blr +entry: + %cmp = icmp sgt i64 %a, -1 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob, align 8 + ret void +} |