diff options
author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-08-08 11:20:44 +0000 |
---|---|---|
committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-08-08 11:20:44 +0000 |
commit | 4db6f31bda67af62b0bcdd780b04c5d33711bc78 (patch) | |
tree | 63a2eccd5c7564a9301695fbff4b9e1dcea84273 /test/CodeGen/PowerPC/testComparesigesi.ll | |
parent | c6a1f940fd4aebe4aa14a64497bf5c0a0d9353c4 (diff) |
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE
Adds handling for SETLE/SETGE comparisons on i32 values. Furthermore, it adds
the handling for the special case where RHS == 0.
Differential Revision: https://reviews.llvm.org/D34048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/testComparesigesi.ll')
-rw-r--r-- | test/CodeGen/PowerPC/testComparesigesi.ll | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/testComparesigesi.ll b/test/CodeGen/PowerPC/testComparesigesi.ll new file mode 100644 index 00000000000..01de5d97628 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigesi.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i32 0, align 4 + +define signext i32 @test_igesi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subf r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: subf r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igesi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: subf r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: subf r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} |