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authorEvan Cheng <evan.cheng@apple.com>2007-09-04 20:20:29 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-09-04 20:20:29 +0000
commit67c906dce729d64861af8ca708f5e19d6a058b35 (patch)
tree38be9b8cc6dbcba20b19b37b91717a30ceaf7e1d /test/CodeGen/PowerPC/rotl-64.ll
parent425e8c7eaee57e3c9dab6701bf2ae6872beab628 (diff)
Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41711 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/rotl-64.ll')
-rw-r--r--test/CodeGen/PowerPC/rotl-64.ll20
1 files changed, 20 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/rotl-64.ll b/test/CodeGen/PowerPC/rotl-64.ll
new file mode 100644
index 00000000000..3963d9a9d71
--- /dev/null
+++ b/test/CodeGen/PowerPC/rotl-64.ll
@@ -0,0 +1,20 @@
+; RUN: llvm-as < %s | llc -march=ppc64 | grep rldicl
+; RUN: llvm-as < %s | llc -march=ppc64 | grep rldcl
+; PR1613
+
+define i64 @t1(i64 %A) {
+ %tmp1 = lshr i64 %A, 57
+ %tmp2 = shl i64 %A, 7
+ %tmp3 = or i64 %tmp1, %tmp2
+ ret i64 %tmp3
+}
+
+define i64 @t2(i64 %A, i8 zeroext %Amt) {
+ %Amt1 = zext i8 %Amt to i64
+ %tmp1 = lshr i64 %A, %Amt1
+ %Amt2 = sub i8 64, %Amt
+ %Amt3 = zext i8 %Amt2 to i64
+ %tmp2 = shl i64 %A, %Amt3
+ %tmp3 = or i64 %tmp1, %tmp2
+ ret i64 %tmp3
+}