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authorHal Finkel <hfinkel@anl.gov>2014-04-13 17:10:58 +0000
committerHal Finkel <hfinkel@anl.gov>2014-04-13 17:10:58 +0000
commit6a34916fbf37318e4fc6b371115394c2791a9c80 (patch)
tree0039e4e643f218594f5cd37cb6738a2363a5cbb2 /test/CodeGen/PowerPC/rlwimi-dyn-and.ll
parentf85e6da6d0fe71b5b97584bad8183a2263cb9a95 (diff)
[PowerPC] Fix rlwimi isel when mask is not constant
We had been using the known-zero values of the operand of the or to construct the mask for an rlwimi; this is not quite correct, but fine when the mask is constant. When the mask is constant, then the known zeros of the operand must be a superset of the zeros in the mask. However, when the mask is not a constant, then there might be bits in the operand that are not known to be zero that, at runtime, might be zero in the mask. Therefore, we check that any bits not known to be zero *are* known to be one in the mask. Otherwise, we can't fold the mask with the or and shift. This was revealed as a miscompile of MultiSource/Benchmarks/BitBench/drop3/drop3 when I started experimenting with constant hoisting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206136 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/rlwimi-dyn-and.ll')
-rw-r--r--test/CodeGen/PowerPC/rlwimi-dyn-and.ll48
1 files changed, 48 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/rlwimi-dyn-and.ll b/test/CodeGen/PowerPC/rlwimi-dyn-and.ll
new file mode 100644
index 00000000000..e02801fafbf
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwimi-dyn-and.ll
@@ -0,0 +1,48 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define i32 @test1() #0 {
+entry:
+ %conv67.reload = load i32* undef
+ %const = bitcast i32 65535 to i32
+ br label %next
+
+next:
+ %shl161 = shl nuw nsw i32 %conv67.reload, 15
+ %0 = load i8* undef, align 1
+ %conv169 = zext i8 %0 to i32
+ %shl170 = shl nuw nsw i32 %conv169, 7
+ %const_mat = add i32 %const, -32767
+ %shl161.masked = and i32 %shl161, %const_mat
+ %conv174 = or i32 %shl170, %shl161.masked
+ ret i32 %conv174
+
+; CHECK-LABEL: @test1
+; CHECK-NOT: rlwimi 3, {{[0-9]+}}, 15, 0, 16
+; CHECK: blr
+}
+
+define i32 @test2() #0 {
+entry:
+ %conv67.reload = load i32* undef
+ %const = bitcast i32 65535 to i32
+ br label %next
+
+next:
+ %shl161 = shl nuw nsw i32 %conv67.reload, 15
+ %0 = load i8* undef, align 1
+ %conv169 = zext i8 %0 to i32
+ %shl170 = shl nuw nsw i32 %conv169, 7
+ %shl161.masked = and i32 %shl161, 32768
+ %conv174 = or i32 %shl170, %shl161.masked
+ ret i32 %conv174
+
+; CHECK-LABEL: @test2
+; CHECK: slwi 3, {{[0-9]+}}, 7
+; CHECK: rlwimi 3, {{[0-9]+}}, 15, 16, 16
+; CHECK: blr
+}
+
+attributes #0 = { nounwind }
+