diff options
| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-05-16 16:15:18 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-05-16 16:15:18 +0000 |
| commit | 0d6423b4762be62966c1941738f5284e35c93b65 (patch) | |
| tree | db702d5a6906eb7d5c4799f57c993e736d4f88fc /test/CodeGen/PowerPC/recipest.ll | |
| parent | 8da0cebc9215e13bd5c71115b7d889deac7ebf7b (diff) | |
Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.ll
While testing some experimental code to add vector-scalar registers to
PowerPC, I noticed that a couple of independent instructions were
flipped by the scheduler. The new CHECK-DAG support is perfect for
avoiding this problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182020 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/recipest.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/recipest.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/test/CodeGen/PowerPC/recipest.ll b/test/CodeGen/PowerPC/recipest.ll index 89705faa46e..38d76820bb7 100644 --- a/test/CodeGen/PowerPC/recipest.ll +++ b/test/CodeGen/PowerPC/recipest.ll @@ -14,8 +14,8 @@ entry: ret double %r ; CHECK: @foo -; CHECK: frsqrte -; CHECK: fnmsub +; CHECK-DAG: frsqrte +; CHECK-DAG: fnmsub ; CHECK: fmul ; CHECK: fmadd ; CHECK: fmul @@ -39,8 +39,8 @@ entry: ret double %r ; CHECK: @foof -; CHECK: frsqrtes -; CHECK: fnmsubs +; CHECK-DAG: frsqrtes +; CHECK-DAG: fnmsubs ; CHECK: fmuls ; CHECK: fmadds ; CHECK: fmuls @@ -61,8 +61,8 @@ entry: ret float %r ; CHECK: @foo -; CHECK: frsqrte -; CHECK: fnmsub +; CHECK-DAG: frsqrte +; CHECK-DAG: fnmsub ; CHECK: fmul ; CHECK: fmadd ; CHECK: fmul @@ -86,8 +86,8 @@ entry: ret float %r ; CHECK: @goo -; CHECK: frsqrtes -; CHECK: fnmsubs +; CHECK-DAG: frsqrtes +; CHECK-DAG: fnmsubs ; CHECK: fmuls ; CHECK: fmadds ; CHECK: fmuls @@ -120,8 +120,8 @@ entry: ret double %r ; CHECK: @foo2 -; CHECK: fre -; CHECK: fnmsub +; CHECK-DAG: fre +; CHECK-DAG: fnmsub ; CHECK: fmadd ; CHECK: fnmsub ; CHECK: fmadd @@ -139,8 +139,8 @@ entry: ret float %r ; CHECK: @goo2 -; CHECK: fres -; CHECK: fnmsubs +; CHECK-DAG: fres +; CHECK-DAG: fnmsubs ; CHECK: fmadds ; CHECK: fmuls ; CHECK: blr @@ -169,8 +169,8 @@ entry: ret double %r ; CHECK: @foo3 -; CHECK: frsqrte -; CHECK: fnmsub +; CHECK-DAG: frsqrte +; CHECK-DAG: fnmsub ; CHECK: fmul ; CHECK: fmadd ; CHECK: fmul @@ -195,8 +195,8 @@ entry: ret float %r ; CHECK: @goo3 -; CHECK: frsqrtes -; CHECK: fnmsubs +; CHECK-DAG: frsqrtes +; CHECK-DAG: fnmsubs ; CHECK: fmuls ; CHECK: fmadds ; CHECK: fmuls |