diff options
author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-10-04 11:25:52 +0000 |
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committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-10-04 11:25:52 +0000 |
commit | 94ec1e3c4f12bbb35094e8ef3e37a682cb2c927d (patch) | |
tree | c8c9a6a7bc784bcbd756e2a3160d797f5d099950 /test/CodeGen/PowerPC/ppc64le-aggregates.ll | |
parent | c072c50d24235f40c9d2f0b63caf1db580d36a20 (diff) |
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set
This patch corresponds to review:
The newly added VSX D-Form (register + offset) memory ops target the upper half
of the VSX register set. The existing ones target the lower half. In order to
unify these and have the ability to target all the VSX registers using D-Form
operations, this patch defines Pseudo-ops for the loads/stores which are
expanded post-RA. The expansion then choses the correct opcode based on the
register that was allocated for the operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283212 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/ppc64le-aggregates.ll')
-rw-r--r-- | test/CodeGen/PowerPC/ppc64le-aggregates.ll | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/test/CodeGen/PowerPC/ppc64le-aggregates.ll index 65e94a1face..25b3e5d8933 100644 --- a/test/CodeGen/PowerPC/ppc64le-aggregates.ll +++ b/test/CodeGen/PowerPC/ppc64le-aggregates.ll @@ -1,5 +1,9 @@ -; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mcpu=pwr8 -mattr=+altivec -mattr=-vsx | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mattr=+altivec -mattr=-vsx | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mcpu=pwr8 \ +; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mattr=+altivec \ +; RUN: -mattr=-vsx | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -march=ppc64le -mcpu=pwr9 \ +; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s ; Currently VSX support is disabled for this test because we generate lxsdx ; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we |