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authorNemanja Ivanovic <nemanja.i.ibm@gmail.com>2016-10-04 06:59:23 +0000
committerNemanja Ivanovic <nemanja.i.ibm@gmail.com>2016-10-04 06:59:23 +0000
commitd0e875cdad4ad13facadf6d1219bde72527158c9 (patch)
tree6d2efc011bdcf0f8432d00e30ebe57dac71424ba /test/CodeGen/PowerPC/ppc64-i128-abi.ll
parentaeddc35a35c55f487977d7609060225e03e2028b (diff)
[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions
This patch corresponds to review: https://reviews.llvm.org/D23155 This patch removes the VSHRC register class (based on D20310) and adds exploitation of the Power9 sub-word integer loads into VSX registers as well as vector sign extensions. The new instructions are useful for a few purposes: Int to Fp conversions of 1 or 2-byte values loaded from memory Building vectors of 1 or 2-byte integers with values loaded from memory Storing individual 1 or 2-byte elements from integer vectors This patch implements all of those uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283190 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/ppc64-i128-abi.ll')
-rw-r--r--test/CodeGen/PowerPC/ppc64-i128-abi.ll9
1 files changed, 6 insertions, 3 deletions
diff --git a/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/test/CodeGen/PowerPC/ppc64-i128-abi.ll
index d81a1104c53..924e04a34a9 100644
--- a/test/CodeGen/PowerPC/ppc64-i128-abi.ll
+++ b/test/CodeGen/PowerPC/ppc64-i128-abi.ll
@@ -55,9 +55,12 @@ define <1 x i128> @v1i128_increment_by_one(<1 x i128> %a) nounwind {
; CHECK-LE: blr
; CHECK-P9-LABEL: @v1i128_increment_by_one
-; CHECK-P9-DAG: li [[R1:r[0-9]+]], 1
-; CHECK-P9-DAG: li [[R2:r[0-9]+]], 0
-; CHECK-P9: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]]
+; The below FIXME is due to the lowering for BUILD_VECTOR that will be fixed
+; in a subsequent patch.
+; FIXME: li [[R1:r[0-9]+]], 1
+; FIXME: li [[R2:r[0-9]+]], 0
+; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]]
+; CHECK-P9: lxvx [[V1:v[0-9]+]]
; CHECK-P9: vadduqm v2, v2, [[V1]]
; CHECK-P9: blr