diff options
| author | Nirav Dave <niravd@google.com> | 2016-11-23 16:48:35 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2016-11-23 16:48:35 +0000 |
| commit | 3e65807a6f16ed51a5d74d10fbf21a3ba2ee17ca (patch) | |
| tree | 5a23e3153e1a6737970c4e18350b3510bc992c2a /test/CodeGen/PowerPC/ppc64-align-long-double.ll | |
| parent | 3806d81f86d205af958239a6acfdb0d8b9e46196 (diff) | |
[DAG] Improve loads-from-store forwarding to handle TokenFactor
Forward store values to matching loads down through token
factors. Factored from D14834.
Reviewers: jyknight, hfinkel
Subscribers: hfinkel, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D26080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287773 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/ppc64-align-long-double.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/ppc64-align-long-double.ll | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/test/CodeGen/PowerPC/ppc64-align-long-double.ll index c3cccd5b293..3f335308d9f 100644 --- a/test/CodeGen/PowerPC/ppc64-align-long-double.ll +++ b/test/CodeGen/PowerPC/ppc64-align-long-double.ll @@ -1,6 +1,6 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=-vsx < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-PWR9 %s ; Verify internal alignment of long double in a struct. The double ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain @@ -23,15 +23,27 @@ entry: ; CHECK-DAG: std 5, 64(1) ; CHECK-DAG: std 4, 56(1) ; CHECK-DAG: std 3, 48(1) -; CHECK: lfd 1, 64(1) -; CHECK: lfd 2, 72(1) +; CHECK: std 5, -16(1) +; CHECK: std 6, -8(1) +; CHECK: lfd 1, -16(1) +; CHECK: lfd 2, -8(1) + ; CHECK-VSX-DAG: std 6, 72(1) ; CHECK-VSX-DAG: std 5, 64(1) ; CHECK-VSX-DAG: std 4, 56(1) ; CHECK-VSX-DAG: std 3, 48(1) -; CHECK-VSX: li 3, 16 -; CHECK-VSX: addi 4, 1, 48 -; CHECK-VSX: lxsdx 1, 4, 3 -; CHECK-VSX: li 3, 24 -; CHECK-VSX: lxsdx 2, 4, 3 +; CHECK-VSX: std 5, -16(1) +; CHECK-VSX: std 6, -8(1) +; CHECK-VSX: addi 3, 1, -16 +; CHECK-VSX: lxsdx 1, 0, 3 +; CHECK-VSX: addi 3, 1, -8 +; CHECK-VSX: lxsdx 2, 0, 3 + + +; CHECK-PWR9-DAG: std 6, 72(1) +; CHECK-PWR9-DAG: std 5, 64(1) +; CHECK-PWR9-DAG: std 4, 56(1) +; CHECK-PWR9-DAG: std 3, 48(1) +; CHECK-PWR9: mtvsrd 1, 5 +; CHECK-PWR9: mtvsrd 2, 6
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