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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-10-28 19:38:24 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-10-28 19:38:24 +0000 |
| commit | 0b61b12b8cc1aba81a3a47848f66e601d4c7536f (patch) | |
| tree | 50e254645ef4801bd79f57a266d07e3ff650a698 /test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll | |
| parent | 4c68e05037714aa79f228990adc900a595154de1 (diff) | |
Implement vector count leading/trailing bytes with zero lsb and vector parity
builtins - llvm portion
This patch corresponds to review https://reviews.llvm.org/D26003.
Committing on behalf of Zaara Syeda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285434 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll b/test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll index 673c0e8636f..a41e6f01881 100644 --- a/test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll +++ b/test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll @@ -145,3 +145,58 @@ declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) ; Function Attrs: nounwind readnone declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1) + +; Function Attrs: nounwind readnone +define i32 @testVCLZLSBB(<16 x i8> %a) { +entry: + %0 = tail call i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8> %a) + ret i32 %0 +; CHECK-LABEL: testVCLZLSBB +; CHECK: vclzlsbb 3, 2 +} +; Function Attrs: nounwind readnone +declare i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8>) + +; Function Attrs: nounwind readnone +define i32 @testVCTZLSBB(<16 x i8> %a) { +entry: + %0 = tail call i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8> %a) + ret i32 %0 +; CHECK-LABEL: testVCTZLSBB +; CHECK: vctzlsbb 3, 2 +} +; Function Attrs: nounwind readnone +declare i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8>) + +; Function Attrs: nounwind readnone +define <4 x i32> @testVPRTYBW(<4 x i32> %a) { +entry: + %0 = tail call <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32> %a) + ret <4 x i32> %0 +; CHECK-LABEL: testVPRTYBW +; CHECK: vprtybw 2, 2 +} +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32>) + +; Function Attrs: nounwind readnone +define <2 x i64> @testVPRTYBD(<2 x i64> %a) { +entry: + %0 = tail call <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64> %a) + ret <2 x i64> %0 +; CHECK-LABEL: testVPRTYBD +; CHECK: vprtybd 2, 2 +} +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64>) + +; Function Attrs: nounwind readnone +define <1 x i128> @testVPRTYBQ(<1 x i128> %a) { +entry: + %0 = tail call <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128> %a) + ret <1 x i128> %0 +; CHECK-LABEL: testVPRTYBQ +; CHECK: vprtybq 2, 2 +} +; Function Attrs: nounwind readnone +declare <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128>) |