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| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 17:15:09 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 17:15:09 +0000 |
| commit | a4ec08b6fd62577a5c0e9ddd3c131e223c0672b8 (patch) | |
| tree | 14dc42e84a489e5ec4e9aefdf9e086ab70c1427d /test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | |
| parent | 7005517f42852ddb80ca986a2933f729d4fd0383 (diff) | |
[CodeGen] Print register names in lowercase in both MIR and debug output
As part of the unification of the debug format and the MIR format,
always print registers as lowercase.
* Only debug printing is affected. It now follows MIR.
Differential Revision: https://reviews.llvm.org/D40417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319187 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll index 5176cdcb600..4ca75a7e365 100644 --- a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll +++ b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll @@ -7,12 +7,12 @@ define signext i32 @fn1(i32 %baz) { %2 = zext i32 %1 to i64 %3 = shl i64 %2, 48 %4 = ashr exact i64 %3, 48 -; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>; +; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def,dead>; ; CHECK: CMPLDI ; CHECK: BCC -; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>; -; CHECK: COPY %CR0 +; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def>; +; CHECK: COPY %cr0 ; CHECK: BCC %5 = icmp eq i64 %4, 0 br i1 %5, label %foo, label %bar @@ -26,8 +26,8 @@ bar: ; CHECK-LABEL: fn2 define signext i32 @fn2(i64 %a, i64 %b) { -; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def>; -; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0 +; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %cr0<imp-def>; +; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0 ; CHECK: BCC 12, [[CREG]]<kill> %1 = or i64 %b, %a %2 = icmp sgt i64 %1, -1 @@ -42,8 +42,8 @@ bar: ; CHECK-LABEL: fn3 define signext i32 @fn3(i32 %a) { -; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def>; -; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0 +; CHECK: ANDIo {{[^, ]+}}, 10, %cr0<imp-def>; +; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0 ; CHECK: BCC 76, [[CREG]]<kill> %1 = and i32 %a, 10 %2 = icmp ne i32 %1, 0 |