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authorMatthias Braun <matze@braunis.de>2016-08-24 01:32:41 +0000
committerMatthias Braun <matze@braunis.de>2016-08-24 01:32:41 +0000
commit66489736bfd79ad1fd3e2e49b10b747970ab2686 (patch)
tree2f79d2f6012b144740cc06c9a9da4fa9a91d4a08 /test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
parent459280c4f328b9a0c9145975437d05c465d87fc7 (diff)
MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.
Specifying isSSA is an extra line at best and results in invalid MI at worst. Compute the value instead. Differential Revision: http://reviews.llvm.org/D22722 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279600 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir')
-rw-r--r--test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir1
1 files changed, 0 insertions, 1 deletions
diff --git a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
index 76702ce50fd..479adbba90e 100644
--- a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
+++ b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
@@ -40,7 +40,6 @@ name: main
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
-isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers: