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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-13 14:47:35 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-13 14:47:35 +0000 |
| commit | 7b053da09f2b4bcd94973adb7cbd281736fab8e1 (patch) | |
| tree | c5980d2d7fabf6da2c067cadac4f073c39dcab36 /test/CodeGen/PowerPC/negctr.ll | |
| parent | a9fb8967977dbaa792c97f2de3b66ec8c4bcddf3 (diff) | |
[PowerPC] MachineSSA pass to reduce the number of CR-logical operations
The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).
Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.
Differential Revision: https://reviews.llvm.org/D30431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320584 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/negctr.ll')
0 files changed, 0 insertions, 0 deletions