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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | 7c9c6ed761bf9d28c0c257a045b35781969136e0 (patch) | |
| tree | 508cac951011b10e2817eacecc1fa640bbdba51e /test/CodeGen/PowerPC/mcm-5.ll | |
| parent | dc64962c8649964d13cc60b83c8c400d5ae7504a (diff) | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/mcm-5.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/mcm-5.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/PowerPC/mcm-5.ll b/test/CodeGen/PowerPC/mcm-5.ll index 92ddecaeb8c..0c258459c91 100644 --- a/test/CodeGen/PowerPC/mcm-5.ll +++ b/test/CodeGen/PowerPC/mcm-5.ll @@ -11,7 +11,7 @@ define signext i32 @test_jump_table(i32 signext %i) nounwind { entry: %i.addr = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 - %0 = load i32* %i.addr, align 4 + %0 = load i32, i32* %i.addr, align 4 switch i32 %0, label %sw.default [ i32 3, label %sw.bb i32 4, label %sw.bb1 @@ -23,31 +23,31 @@ sw.default: ; preds = %entry br label %sw.epilog sw.bb: ; preds = %entry - %1 = load i32* %i.addr, align 4 + %1 = load i32, i32* %i.addr, align 4 %mul = mul nsw i32 %1, 7 store i32 %mul, i32* %i.addr, align 4 br label %sw.bb1 sw.bb1: ; preds = %entry, %sw.bb - %2 = load i32* %i.addr, align 4 + %2 = load i32, i32* %i.addr, align 4 %dec = add nsw i32 %2, -1 store i32 %dec, i32* %i.addr, align 4 br label %sw.bb2 sw.bb2: ; preds = %entry, %sw.bb1 - %3 = load i32* %i.addr, align 4 + %3 = load i32, i32* %i.addr, align 4 %add = add nsw i32 %3, 3 store i32 %add, i32* %i.addr, align 4 br label %sw.bb3 sw.bb3: ; preds = %entry, %sw.bb2 - %4 = load i32* %i.addr, align 4 + %4 = load i32, i32* %i.addr, align 4 %shl = shl i32 %4, 1 store i32 %shl, i32* %i.addr, align 4 br label %sw.epilog sw.epilog: ; preds = %sw.bb3, %sw.default - %5 = load i32* %i.addr, align 4 + %5 = load i32, i32* %i.addr, align 4 ret i32 %5 } |