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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-10-04 11:25:52 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-10-04 11:25:52 +0000 |
| commit | 94ec1e3c4f12bbb35094e8ef3e37a682cb2c927d (patch) | |
| tree | c8c9a6a7bc784bcbd756e2a3160d797f5d099950 /test/CodeGen/PowerPC/mcm-4.ll | |
| parent | c072c50d24235f40c9d2f0b63caf1db580d36a20 (diff) | |
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set
This patch corresponds to review:
The newly added VSX D-Form (register + offset) memory ops target the upper half
of the VSX register set. The existing ones target the lower half. In order to
unify these and have the ability to target all the VSX registers using D-Form
operations, this patch defines Pseudo-ops for the loads/stores which are
expanded post-RA. The expansion then choses the correct opcode based on the
register that was allocated for the operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283212 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/mcm-4.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/mcm-4.ll | 30 |
1 files changed, 26 insertions, 4 deletions
diff --git a/test/CodeGen/PowerPC/mcm-4.ll b/test/CodeGen/PowerPC/mcm-4.ll index 34fa4d1093f..180977d8932 100644 --- a/test/CodeGen/PowerPC/mcm-4.ll +++ b/test/CodeGen/PowerPC/mcm-4.ll @@ -1,7 +1,15 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \ +; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \ +; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \ +; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \ +; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=medium \ +; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-P9 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=large \ +; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-P9 %s ; Test correct code generation for medium and large code model ; for loading a value from the constant pool (TOC-relative). @@ -41,3 +49,17 @@ entry: ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]] + +; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]: +; MEDIUM-P9: .quad 4562098671269285104 +; MEDIUM-P9-LABEL: test_double_const: +; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha +; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l +; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]]) + +; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]: +; LARGE-P9: .quad 4562098671269285104 +; LARGE-P9-LABEL: test_double_const: +; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha +; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) +; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]]) |