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| author | Tom Stellard <tstellar@redhat.com> | 2018-11-30 04:51:41 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-11-30 04:51:41 +0000 |
| commit | e8af9b4c407003c1c771aa16fe2b3c747a0d344e (patch) | |
| tree | af0993261335513870a3c1a7594c249fd3597148 /test/CodeGen/PowerPC/load-v4i8-improved.ll | |
| parent | f8ee49e3d8b9a064d424e30c1d97086509e8556d (diff) | |
Merging r339260:
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r339260 | syzaara | 2018-08-08 08:20:43 -0700 (Wed, 08 Aug 2018) | 13 lines
[PowerPC] Improve codegen for vector loads using scalar_to_vector
This patch aims to improve the codegen for vector loads involving the
scalar_to_vector (load X) sequence. Initially, ld->mv instructions were used
for scalar_to_vector (load X), so this patch allows scalar_to_vector (load X)
to utilize:
LXSD and LXSDX for i64 and f64
LXSIWAX for i32 (sign extension to i64)
LXSIWZX for i32 and f64
Committing on behalf of Amy Kwan.
Differential Revision: https://reviews.llvm.org/D48950
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@347957 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/load-v4i8-improved.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/load-v4i8-improved.ll | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/test/CodeGen/PowerPC/load-v4i8-improved.ll b/test/CodeGen/PowerPC/load-v4i8-improved.ll index 36f347222d5..f1fa2996074 100644 --- a/test/CodeGen/PowerPC/load-v4i8-improved.ll +++ b/test/CodeGen/PowerPC/load-v4i8-improved.ll @@ -1,15 +1,27 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck \ +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck --check-prefix=CHECK-LE \ ; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck \ +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \ ; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s define <16 x i8> @test(i32* %s, i32* %t) { +; CHECK-LE-LABEL: test: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: lfiwzx f0, 0, r3 +; CHECK-LE-NEXT: xxpermdi vs0, f0, f0, 2 +; CHECK-LE-NEXT: xxspltw v2, vs0, 3 +; CHECK-LE-NEXT: blr + +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfiwzx f0, 0, r3 +; CHECK-NEXT: xxsldwi vs0, f0, f0, 1 +; CHECK-NEXT: xxspltw v2, vs0, 0 +; CHECK-NEXT: blr entry: %0 = bitcast i32* %s to <4 x i8>* %1 = load <4 x i8>, <4 x i8>* %0, align 4 %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> ret <16 x i8> %2 -; CHECK-LABEL: test -; CHECK: lxsiwax 34, 0, 3 -; CHECK: xxspltw 34, 34, 1 } |